CN116187256A

CN116187256A - Grating calculation method of layout and full-chip simulation method

Info

Publication number: CN116187256A
Application number: CN202211700014.5A
Authority: CN
Inventors: 吴家俊; 谢理; 包涵; 陈红
Original assignee: Shenzhen Guowei Fuxin Technology Co ltd
Current assignee: Shenzhen Guowei Fuxin Technology Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-05-30

Abstract

The invention discloses a rasterization calculation method of a layout and a full-chip simulation method. The rasterization calculation method of the layout comprises the following steps: selecting part of pixel points and calculating a rasterization result; dividing a Manhattan graph on the layout into a plurality of rectangles; judging whether the top point of the rectangle is a selected partial pixel point or not; if so, finding out the rasterization results of four middle rectangles which are formed by respectively extending by taking the four vertexes of the rectangle as the original points from the calculated rasterization results according to the coordinates of the four vertexes of the rectangle; and carrying out corresponding superposition based on the four middle rectangular rasterization results to obtain rectangular rasterization results. The invention can greatly reduce the calculation amount of the rasterization of the layout.

Description

Grating calculation method of layout and full-chip simulation method

Technical Field

The invention relates to the technical field of photoetching of semiconductor manufacturing, in particular to a rasterization calculation method of a layout.

Background

In the manufacture of integrated circuits (ICs, integrated circuit), in order to obtain a target pattern on a wafer, it is necessary to implement a transfer of the pattern from a reticle to a silicon wafer (wafer) surface, a so-called photolithography process. Photolithography typically requires an exposure step, a development step and a subsequent etching step. When exposing, the light emitted from the light source irradiates the silicon wafer coated with the photoresist through the light-transmitting area in the mask, the photoresist is not blocked by the mask, and the area irradiated by the light has chemical reaction; in the development step, photoetching patterns are formed by utilizing the difference of the dissolution degree of photosensitive photoresist and non-photosensitive photoresist on a developer, so that the transfer of the patterns from a mask plate to the photoresist is realized; in the etching step, the silicon wafer is etched based on the photoetching pattern formed by the photoresist layer, and the pattern of the mask plate is further transferred to the silicon wafer. With the advancement of moore's law, the minimum size of a design pattern is gradually reduced to be closer to the limit of a photoetching imaging system, the diffraction effect of light becomes more and more obvious, the imaging pattern obtained by exposure is severely distorted compared with the pattern on a mask plate, and the actual pattern and the design pattern formed by photoetching on a silicon wafer are different, so that the phenomenon is called optical proximity effect (OPE: optical Proximity Effect).

In order to correct the optical proximity effect, optical proximity correction (OPC: optical Proximity Correction) is generated, and the optical proximity effect is counteracted by correcting the pattern on the mask plate, so that the photoetching result which meets the expected target better is obtained.

In order to perform optical proximity correction, the entire lithographic process needs to be modeled first. In optical system modeling, a relatively accurate way is to use abbe imaging principles for modeling. In the calculation, use (f _x `,f _y (f) represents the direction of light from the light source toward the mask _x ,f _y ) The deflection angle of the diffracted light with respect to the main optical axis direction is shown.

I(x,y,f _x `,f _y `)＝E(x,y,f _x `,f _y `)·E ^* (x,y,f _x `,f _y `)

Wherein E (x, y, f) _x `,f _y ') is an electric field function, and is obtained by the following formula:

wherein T is _m (f _x ,f _y ) The mask transmission coefficient is obtained by carrying out Fourier transform on a mask function M (x, y); p (f) _x ,f _y ) As pupil functions, expressed as:

and (5) expanding to obtain a light intensity calculation formula:

the strict application of Abbe imaging principle has great disadvantages, in full chip simulation, the chip size is large, and the mask transmission function T _m (f _x ,f _y ,f _x `,f _y And related to the light source, the optical system cannot perform independent calculation with the mask system, and the calculation is time-consuming. The manner in which accuracy is sacrificed is generally employed. Approximating the mask as a thin mask:

T _m (f _x ,f _y ,f _x `,f _y `)≈T _m (f _x -f _x `,f _y -f _y `)

by this approximation, the Hopkins model (Hopkins model) can be used to alter the computational flow of the imaging by first computing the illuminant and lens group pupil to obtain the cross-transmission matrix (TCC), and then computing with a thin mask.

The mask part and the optical imaging part are separated by the Hopkins theory, so that for full-chip simulation, fixed optical conditions can be adopted, and the full-chip can be simulated by only changing different layouts.

However, from the existing layout data structure to the computation of aerial images from the Hopkins model, an important step, the so-called "rasterization", is also required. The data provided by the layout, whether GDSII or OASIS, are endpoints of all polygons on the layout. To calculate the diffraction and imaging of the mask in a given area, a pixel array (bitmap) of the area is required, and the transmittance of light in the area corresponding to the pixel is recorded on each pixel point on the bitmap. For the most common 0/1 mask, the transmittance is 0 or 1 according to whether the pixel position transmits light or not; for more complex Phase Shift masks (Phase Shift masks), the transmittance has more complex values. Converting the polygon data structure into a required pixel array is an item with great calculation overhead;

in addition, the whole layout is subjected to pixelation processing, the generated data volume is huge, filtering is needed through convolution, blurring processing is carried out on layout information, namely so-called rasterization processing is carried out, and a mask function M (x, y) and a mask transmission function T which can be used in actual calculation of a model are obtained _m (f _x ,f _y ,f _x `,f _y "A"). And because the chip layout is large in general size, the rasterization calculation for realizing the full layout is too large overhead for the OPC of the full chip, and acceleration is required to be realized through an algorithm.

Disclosure of Invention

In order to solve the technical problem of large calculation amount of layout rasterization in the prior art, the invention provides a layout rasterization calculation method and a full-chip simulation method.

The invention relates to a rasterization calculation method of a layout, which comprises the following steps:

selecting part of pixel points and calculating a rasterization result;

dividing a Manhattan graph on the layout into a plurality of rectangles;

judging whether the top point of the rectangle is a selected partial pixel point or not; if so, finding out the rasterization results of four middle rectangles which are formed by respectively extending by taking the four vertexes of the rectangle as the original points from the calculated rasterization results according to the coordinates of the four vertexes of the rectangle;

and carrying out corresponding superposition based on the four middle rectangular rasterization results to obtain rectangular rasterization results.

Further, selecting a part of pixels and calculating a rasterization result thereof comprises the following steps:

setting the size of a pixel unit;

dividing the corresponding area into grid arrays with the pixel unit size as square grid side length;

the rasterization result for each point on the grid array is calculated.

Further, a lookup table is established for the coordinates of each point on the grid array and its corresponding rasterization result.

Further, the rasterization result of each point on the grid array adopts a formula

The M (x, y) is obtained through calculation and is a mask function, and the K (x, y) is a convolution kernel required in blurring calculation.

Further, if the vertex of the rectangle is not a selected partial pixel point, the linear difference value is adopted to obtain the rasterization result of the vertex of the rectangle through the coordinate point of the grid nearest to the vertex of the rectangle.

Further, the formula is adopted

And calculating a rasterization result of the vertex of the rectangle.

Further, a concave point splitting method is adopted to split the Manhattan graph on the layout into a plurality of rectangles.

Further, the four middle rectangles are respectively formed by extending upwards and rightwards from the top point of the lower left corner of the rectangle; and when the four middle rectangles are overlapped, generating a negative value from the rasterization result of the middle rectangle taking the top left corner vertex and the bottom right corner vertex of the rectangle as the bottom left corner vertex, and then overlapping the negative value with the rasterization result of the middle rectangle taking the bottom left corner vertex and the top right corner vertex of the rectangle as the bottom left corner vertex to obtain the rasterization result of the rectangle.

The full-chip simulation method provided by the invention adopts the layout rasterization calculation method of the layout, which is described in the technical scheme, to perform rasterization calculation on the layout of the chip.

According to the method, the rasterization result of part of pixel points is calculated firstly, then the Manhattan layout is divided, the divided rectangle is calculated by adopting an superposition method, a fast mask rasterization calculation algorithm can be provided for any size of process nodes, the algorithm can be applied to a full-chip simulation flow, and particularly for process nodes below 28nm, as the smaller the node is, the higher the requirements on speed and precision are, and the calculation speed and precision of mask rasterization of process nodes below 28nm can be met by adopting the method. The invention can provide high-speed thin mask simulation pictures aiming at the layout of Manhattan graphics, and the efficiency is about 100 times of that of the traditional algorithm.

Drawings

The invention is described in detail below with reference to examples and figures, wherein:

FIG. 1 is a flow chart of an embodiment of the present invention.

FIG. 2 is a schematic overlay of rectangular rasterization results in accordance with one embodiment of the present invention.

FIG. 3 is a schematic diagram of the arrangement of dots of a non-grid array in accordance with an embodiment of the present invention.

FIG. 4 is a schematic illustration of a split line drawing of a Manhattan polygon in accordance with one embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.

As shown in fig. 1, the method for rasterizing calculation of a layout proposed by the present invention includes the following steps in one embodiment.

Selecting part of pixel points and calculating a rasterization result;

dividing a Manhattan graph on the layout into a plurality of rectangles;

judging whether the top point of the rectangle is a selected partial pixel point or not; if so, finding out the rasterization results of four middle rectangles which are formed by respectively extending by taking the four vertexes of the rectangle as the original points from the calculated rasterization results according to the coordinates of the four vertexes of the rectangle; and carrying out corresponding superposition based on the four middle rectangular rasterization results to obtain rectangular rasterization results. The rasterization result of four middle rectangles formed by respectively extending rightward with the four vertexes of the rectangle as the lower left corner vertexes is found, for example, from the rasterization results which have been calculated. For example, the middle rectangle can be obtained by extending from the top right corner to the bottom left, and then overlapping. Likewise, from the upper left or lower right corner is also possible.

For any layout file, the conventional method is to discretize the layout file, smooth the layout file and sample the layout file. However, since accuracy needs to be ensured, resolution of the picture after discretization and smoothing is high, calculation is time-consuming. Because of the particularity of the layout file, the invention adopts the method to convert any Manhattan graph on the layout into the mutual addition and subtraction operation among the calculation results of the known graph for the layout file with only Manhattan graphs, namely the graph on the layout is polygonal, and all polygonal edges are along the horizontal or vertical direction.

In one embodiment, the invention generates a negative value from the rasterization result of the middle rectangle taking the top left corner vertex and the bottom right corner vertex of the rectangle as the bottom left corner vertex, and then superimposes the negative value with the rasterization result of the middle rectangle taking the bottom left corner vertex and the top right corner vertex of the rectangle as the bottom left corner vertex to obtain the rasterization result of the rectangle.

Referring specifically to fig. 2, to obtain the black rectangle on the left of the equal sign in fig. 2, the first black middle rectangle on the right of the equal sign may be added to the second black middle rectangle, and subtracting the third black middle rectangle and the fourth black middle rectangle may obtain the black rectangle on the left of the equal sign. The example is given in which the pixel of the large black portion is 1 and the pixel of the large white portion is 0.

The first black middle rectangle is a middle rectangle obtained by extending the top left corner vertex of the black rectangle to the right and the top right, so that the pixels in the range of the first black middle rectangle are all 1, the second black middle rectangle is a middle rectangle obtained by extending the top right corner vertex of the black rectangle to the right and the top right, when the second black middle rectangle is overlapped with the first black middle rectangle, the pixels in the range of the second black middle rectangle are all 2, the pixels of the first black middle rectangle except the second black middle rectangle are all 1, then the pixels of the third black middle rectangle are middle rectangles obtained by extending the top left corner vertex of the black rectangle to the right and the top right, and as the pixel value is a negative value, the pixels in the range of the second black middle rectangle are all 1 after being overlapped with the two previous black middle rectangles, the pixels in the range of the second black middle rectangle are all 0, and the pixels in the left side of the second black middle rectangle are still 1. Finally, the fourth black middle rectangle is a middle rectangle obtained by extending from the right lower corner vertex of the black rectangle to the right upper side, and because the pixel value of the fourth black middle rectangle is negative, after the fourth black middle rectangle is overlapped with the previous three black middle rectangles, the pixel in the range of the second black middle rectangle becomes 0, and the pixel of the first black middle rectangle below the second black middle rectangle becomes 0. The rectangle to the left of the equal sign is eventually formed.

In one embodiment, the present invention selects a portion of the pixels and calculates the rasterization results thereof using the following method.

Firstly, setting the size of a pixel unit;

dividing the corresponding area (namely the local area of the layout) into grid arrays with the pixel unit size as square grid side length;

the rasterization result for each point on the grid array is calculated.

In one embodiment, the coordinates of each point on the grid array and its corresponding rasterization result may also be used to build a lookup table. The rasterization result for each point on the grid array may employ the formula

The M (x, y) is calculated as a mask function, and the K (x, y) is a convolution kernel required in the blurring calculation, namely, a convolution kernel required in the rasterization processing calculation.

The following description will take the example of creating a lookup table of rasterization results.

For a selected area, the selected area is selected by a user according to the needs of the user, the user gives a pixel unit size a, and the area is divided into a square close-packed grid array with a side length of a. For a given calculation region of size (a x m, a x n), the calculation region in the present invention generally refers to a rectangular shape after the manhattan polygon is divided, and may be divided into a grid array of (m, n) dimensions. The lower left corner of the array is set to (0, 0) and the upper right corner is set to (m, n). For each point (x, y) on the array, a value is calculated that establishes a correspondence of the grid on the lookup table, the value being used to represent when the rectangular area is defined by the (x, y) point and the (m, n) point, i.e., the (x, y) point is the lower left corner vertex of the defined rectangular area, extending to the upper right to the (m, n) point, such that the (m, n) point is referred to as the upper right corner of the defined rectangular area.

The calculation result is realized by a convolution method. Assuming that the mask function is M (x, y), the function distribution after the rasterization calculation is completed is:

where K (x, y) is the convolution kernel required in the blurring calculation, the size of the convolution kernel is (p, q), and a Gaussian function is generally used in practical applications. In practical application, two-dimensional convolution calculation is performed on each pixel point, so that huge calculation cost is brought, and calculation acceleration is realized by calculating partial convolution results in advance and multiplexing the results.

If the vertex of the rectangle is not a selected partial pixel point, a linear method is adopted to obtain the rasterization result of the vertex of the rectangle through the coordinate point of the grid nearest to the vertex of the rectangle.

In one embodiment, the present invention employs bilinear interpolation. As shown in FIG. 3, dst is the target vertex, src is the divided mesh vertex, and the result calculated by each src point rasterization already exists in the rasterization result lookup table, so that a formula is adopted

The rasterization result of the vertices of the rectangle that do not fall onto the vertices of the mesh can be calculated.

In one embodiment, the present invention employs a concave point splitting method to split the Manhattan pattern on the layout into a plurality of rectangles. There are many methods in the prior art for segmenting manhattan patterns based on pits in the manhattan pattern.

Any Manhattan polygon on the layout can be split into a plurality of rectangles. Considering the characteristics of Manhattan polygons on a layout and the calculated amount, the Manhattan polygons are required to be split into rectangles with the quantity as small as possible, and the corresponding concave point splitting method is adopted for splitting.

Taking the manhattan polygon of fig. 4 as an example, first, all points (also called vertices) of the manhattan polygon are screened, and all points in the manhattan polygon are selected, where the points represent points with 270 degrees in the polygon on a very small circle centered on the points. Then, among the concave points, the opposite concave point pair is selected and connected, and it should be noted that one concave point may correspond to more than one point and all the concave points need to be connected. Then, finding out the concave point pairs with the cross in the connecting lines (excluding the condition that common endpoints exist), optionally removing one connecting line, reserving the largest number of the concave point connecting lines which are not crossed with each other as far as possible, and dividing the polygon by the connecting lines, wherein the largest number refers to the largest number of the concave point connecting lines which are not crossed with each other; and finally, taking out the concave points which are not segmented from all the concave points, and segmenting the sub-polygons segmented in advance along any (x or y) direction, wherein the rectangular segmentation of the polygons is completed.

Since the Manhattan polygon is a combination of multiple rectangles, it can be expressed as an expression

And the rasterization of the original polygon can be realized by recombining rasterization of all the divided rectangles:

the concave point segmentation method is adopted, so that the segmentation efficiency is ensured, the minimum number of Manhattan polygons can be segmented, and the minimum calculation cost is realized in the subsequent calculation.

Thereafter, the rasterization result of each split rectangle is calculated. I.e. any rectangle can be converted into a superposition of four intermediate rectangles. The 4 overlapped middle rectangles are obtained by taking out the result according to the lookup table with the four vertex orientations of the rectangle to be calculated.

The invention also protects a full-chip simulation method, which adopts the rasterization calculation method of the layout of the technical scheme to perform rasterization calculation on the layout of the chip.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. A rasterization calculation method of a layout is characterized by comprising the following steps:

selecting part of pixel points and calculating a rasterization result;

dividing a Manhattan graph on the layout into a plurality of rectangles;

2. The method for rasterizing computation of a layout according to claim 1, wherein selecting a part of pixels and computing a rasterizing result thereof comprises the steps of:

setting the size of a pixel unit;

the rasterization result for each point on the grid array is calculated.

3. The method of rasterizing computation of claim 2, wherein a look-up table is built up of coordinates of each point on the grid array and its corresponding rasterizing result.

4. The method of rasterizing computation of a layout of claim 2, wherein the rasterization result for each point on the grid array uses a formula

5. The method for rasterizing computation of a layout according to claim 2, wherein if the vertex of the rectangle is not a selected partial pixel point, the rasterizing result of the vertex of the rectangle is obtained by using a linear difference value through a coordinate point of a grid nearest to the vertex of the rectangle.

6. The method for rasterizing computation of a layout according to claim 5, wherein a formula is adopted

And calculating a rasterization result of the vertex of the rectangle.

7. The method for rasterizing computation of a layout according to claim 1, wherein a manhattan pattern on the layout is divided into a plurality of rectangles by a concave point division method.

8. The method for rasterizing and calculating a layout according to claim 1, wherein the four middle rectangles are respectively formed by extending upwards and upwards to the right from the left lower corner vertex of each rectangle; and when the four middle rectangles are overlapped, generating a negative value from the rasterization result of the middle rectangle taking the top left corner vertex and the bottom right corner vertex of the rectangle as the bottom left corner vertex, and then overlapping the negative value with the rasterization result of the middle rectangle taking the bottom left corner vertex and the top right corner vertex of the rectangle as the bottom left corner vertex to obtain the rasterization result of the rectangle.

9. A full-chip simulation method, characterized in that a rasterization calculation method of the layout according to any one of claims 1 to 8 is adopted to perform rasterization calculation on the layout of the chip.