CN116149567B - Memristor-based memory calculation integrated system and online deep learning method - Google Patents
Memristor-based memory calculation integrated system and online deep learning methodInfo
- Publication number
- CN116149567B CN116149567B CN202310170150.6A CN202310170150A CN116149567B CN 116149567 B CN116149567 B CN 116149567B CN 202310170150 A CN202310170150 A CN 202310170150A CN 116149567 B CN116149567 B CN 116149567B
- Authority
- CN
- China
- Prior art keywords
- memristor
- deep learning
- array
- iwc
- learning method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
- G06N3/084—Backpropagation, e.g. using gradient descent
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Biophysics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- General Health & Medical Sciences (AREA)
- Artificial Intelligence (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Evolutionary Computation (AREA)
- Human Computer Interaction (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
本发明公开了基于忆阻器的存算一体化系统及在线深度学习方法，属于信息存储领域，包括：存储模块和控制器；存储模块包括多个Tile，每个Tile包括多个PE，每个PE包含一个或多个忆阻器阵列；控制器用于执行基于映射表的阵列间磨损均衡策略，包括：将每M次写入划分为一个磨损均衡周期；为每一个PE维护总写入次数TWC和磨损均衡周期内写入次数IWC；循环执行：将各PE的IWC均置为0；将运行阶段中PE内阵列的写入次数累积记录到IWC，直至当前磨损均衡周期结束；将各PE的IWC累加到对应的TWC；重建映射表，使得IWC越大，对应的逻辑ID所映射的物理ID对应的TWC越小；进行数据交换。本发明能够提高基于忆阻器的存算一体化系统中磨损均衡的效果，从而提高系统的整体寿命。
This invention discloses a memristor-based in-memory computing system and an online deep learning method, belonging to the field of information storage. It includes a storage module and a controller. The storage module comprises multiple tiles, each tile containing multiple physical instances (PEs), and each PE containing one or more memristor arrays. The controller executes a wear leveling strategy based on a mapping table, including: dividing every M writes into a wear leveling cycle; maintaining a total write count (TWC) and an inter-array write count (IWC) for each PE; iteratively executing: setting the IWC of each PE to 0; accumulating and recording the write counts of the arrays within each PE during the running phase into the IWC until the current wear leveling cycle ends; adding the IWC of each PE to the corresponding TWC; reconstructing the mapping table so that the larger the IWC, the smaller the TWC corresponding to the physical ID mapped by the logical ID; and performing data exchange. This invention can improve the wear leveling effect in a memristor-based in-memory computing system, thereby increasing the overall lifespan of the system.
Description
Technical Field
The invention belongs to the field of information storage, and particularly relates to a memristor-based memory and calculation integrated system and an online deep learning method.
Background
With the advent of the big data age, demands on computing speed, power consumption and the like of traditional computing systems are increasing, and the von neumann problem has become an important bottleneck for limiting the further development of current computer systems. Memristors have been proposed since, and have become one of the development objects of the next generation of semiconductor memories with great prospect due to the characteristics of non-volatile, high integration, low power consumption and the like. The characteristic of integration of calculation and storage of memristors also becomes a powerful foundation for constructing a novel calculation and storage integrated architecture. Due to the characteristics of high density and high energy efficiency, the memristor-based memory and calculation integrated architecture has extremely high potential in deep neural network acceleration application.
FIG. 1 shows a classical memristor-based integrated neural network accelerator architecture employing a 3-layer architecture design (Tile/PE/Crossbar), wherein the memory structure comprises a plurality of tiles, each Tile further comprises a plurality of PEs, each PE comprises a plurality of memristor arrays, and memristor cells in the memristor arrays are often organized in a cross-point array.
In large-scale streaming data scenarios, represented by online deep learning, frequent writing of memristor arrays can result, which is a great challenge for the limited lifetime of memristor arrays. In addition, write imbalance can lead to dramatic reduction in memristor-based memory integration system lifetime, "short plate effect" is prominent, and in large-scale streaming data scenarios, write imbalance issues are more pronounced.
In order to address the effect of write imbalance on memristor lifetime, researchers have proposed a corresponding wear leveling strategy, the overall idea of which is to distribute the writes as evenly as possible into different cells. Fig. 2 shows a schematic implementation diagram of three existing intra-array wear leveling strategies, in which (a) is a column shift (columnshift, CS) scheme, and specifically, wear leveling is achieved by circularly shifting all columns in the array, (b) is a row swap (rowswap, RS) scheme, and specifically, wear leveling is achieved by swapping rows in the matrix, and (c) is a column swap (rowcolumnswap, RCS) scheme, and specifically, wear leveling is achieved by swapping rows and columns in the array. These wear leveling strategies can extend the life of the array to some extent, however, the existing wear leveling strategies are all performed in the array and cannot perform wear leveling at the system level, so that the life-improving effect is very limited.
Disclosure of Invention
Aiming at the defects and improvement demands of the prior art, the invention provides a memristor-based memory and calculation integrated system and an online deep learning method, and aims to improve the effect of wear balance in the memristor-based memory and calculation integrated system so as to prolong the overall service life of the system.
In order to achieve the above object, according to one aspect of the present invention, there is provided a memristor-based memory integrated system, including a memory module and a controller;
the storage module comprises a plurality of interconnected tiles, wherein each Tile comprises a plurality of interconnected PE, each PE comprises N memristor arrays, the mapping relation from the logic ID to the physical ID of each PE is recorded in a mapping table, N is a positive integer, and N is more than or equal to 1;
The controller is used for executing an inter-array wear balancing strategy based on a mapping table, and comprises the following steps:
Dividing each M times of writing into a wear leveling period, wherein M is a preset positive integer, maintaining metadata TWC and IWC for each PE, respectively recording the total writing times of the PE and the writing times in the current wear leveling period, and executing the following steps in each wear leveling period:
(S1) setting IWC of each PE to 0;
(S2) cumulatively recording the writing times of the memristor array in the PE in the operation stage to the corresponding IWC until the current wear balancing period is finished;
(S3) accumulating IWCs of the PEs to the corresponding TWCs;
(S4) rebuilding the mapping table such that the larger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID is;
(S5) exchanging data stored in the PE based on the current mapping table.
Further, n=1.
Further, the IWCs of each PE are stored in registers internal to their memristor array.
Further, the plurality of tiles in the memory module are interconnected by Torus routing.
Further, one or more memristor arrays in the storage module are divided into dedicated metadata storage areas;
The TWC of each PE is stored in the metadata storage area.
According to another aspect of the invention, an online deep learning method based on the memristor-based memory and calculation integrated system is provided, wherein the memristor-based memory and calculation integrated system is used for accelerating online deep learning;
The online deep learning method comprises the following steps:
In the back propagation process, if the contribution rate α k of any kth hidden layer is smaller than a preset threshold epsilon and the number of data instances spaced from the last update of the hidden layer weight W k is smaller than a preset value gamma, the weight W k of the hidden layer is not updated, otherwise, the weight W k of the hidden layer is updated.
Further, the online deep learning method provided by the invention further comprises the step of updating the hidden layer weight and the step (S5) are executed simultaneously.
Further, γ=2.
Further, the memristor-based memory and calculation integrated system further comprises an auxiliary calculation unit, a vector calculation unit and a calculation unit, wherein the auxiliary calculation unit is used for executing vector operation;
and, in the process of back propagation of the online deep learning method, the calculation of the weight gradient is completed by an auxiliary calculation unit.
Further, the memristor-based memory and calculation integrated system further comprises a global cache;
in addition, in the back propagation process of the online deep learning method, intermediate data required by weight gradient calculation are stored in a global cache.
In general, through the above technical solutions conceived by the present invention, the following beneficial effects can be obtained:
(1) The memristor-based storage and calculation integrated system adopts an inter-array wear balancing strategy based on a mapping table, wherein the strategy maintains metadata TWC and IWC for each PE, the TWC is used for recording total write-in times of PE and reflecting total wear degree of the array in the whole life cycle, the IWC is used for recording write-in times of the current wear balancing cycle and reflecting short-term write-in heat of the array, and the mapping table is rebuilt when each wear balancing cycle is finished, so that the bigger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logic ID is, the thermal logic array is remapped to the physical array with less wear, the wear balancing among the arrays is realized, and compared with the existing wear balancing method in the arrays, the wear balancing effect can be improved, and finally the whole service life of the system is improved.
The inter-array wear balance strategy based on the mapping table is orthogonal to the existing intra-array wear balance strategy, can be used in combination with the existing intra-array wear balance strategy, realizes intra-array wear balance on the basis of realizing inter-array wear balance, and further improves the wear balance effect.
In addition, the inter-array wear balancing strategy based on the mapping table may enable the physical arrays belonging to the same logic matrix to be distributed in a plurality of tiles after the mapping table is reconstructed, so that the calculation tasks are distributed in the plurality of tiles, and bandwidth contention in the tiles is relieved.
(2) According to the memristor-based storage and calculation integrated system, in the preferred scheme, each PE only comprises a single memristor array, namely PE layers in the original three-level (Tile/PE/Crossbar) architecture are removed, the system architecture is simplified from the three-level (Tile/PE/Crossbar) architecture to the two-level (Tile/Crossbar) architecture, so that unnecessary communication expenditure can be reduced, the calculation speed is increased, and the overall performance of the system is further improved.
(3) In the invention, the IWC is temporary metadata and is frequently updated, and in the preferred scheme of the invention, the IWC is stored in a register inside the memristor array under a two-level hierarchical architecture, so that frequent writing to the memristor array due to IWC updating is avoided.
(4) In the preferred scheme of the invention, under the two-level hierarchical architecture, a plurality of tiles in the storage module are interconnected through the Torus route, so that the communication overhead can be further reduced.
(5) In the invention, TWC is important metadata which records the total number of unit writing in the life cycle of the memristor array, and in the preferred scheme of the invention, the metadata TWC of each PE is intensively stored in the special memristor array, thereby realizing nonvolatile storage of the metadata TWC and ensuring the storage safety of the metadata TWC.
(6) According to the online deep learning method provided by the invention, the memristor-based memory calculation integrated system is utilized to realize a deep learning network, only the hidden layer weight with higher contribution rate is updated in the back propagation process, the weight of a non-key hidden layer is not updated, the hidden layer weight is forcedly updated by gamma data examples, and the number of times of updating the hidden layer weight is effectively reduced under the condition of ensuring the deep learning effect, so that the writing of an array in the memory calculation integrated system is reduced, the energy consumption expense is reduced, and the service life of the system is prolonged.
(7) In the online deep learning method provided by the invention, in the preferred scheme, the hidden layer weight is updated while the data exchange operation in the inter-array wear balance strategy based on the mapping table is executed, and the additional writing introduced by the data exchange is reduced by overlapping the data exchange and the weight update because the data exchange is hidden in the weight update.
(8) According to the online deep learning method, in the preferred scheme, the number of data instances spaced by forced weight updating is set to be gamma=2, so that the maximum balance between the deep learning effect and the memristor array service life improving effect can be achieved.
(9) The data on which the online deep learning depends are large-scale streaming data, in the back propagation process, matrix operation of gradient calculation is degraded into vector operation, and in the preferred scheme of the invention, calculation of weight gradient is transferred from the memristor array to an auxiliary calculation unit, so that writing of the memristor array can be reduced, energy expenditure is reduced, service life is prolonged, and meanwhile, space waste is avoided.
(10) In deep learning, intermediate data is needed for calculation of weight gradients as input, and in online deep learning, the intermediate data storage requirement is smaller, and in the preferred scheme of the invention, the storage position of the intermediate data needed for calculation of weight gradients is transferred from the memristor array to the global cache, so that space waste can be avoided.
Drawings
FIG. 1 is a diagram of a prior memristor-based memory integrated system architecture;
FIG. 2 is a schematic diagram illustrating the implementation of three prior intra-array wear leveling strategies, wherein (a) is a column shift (columnshift, CS) scheme, (b) is a row switch (rowswap, RS) scheme, and (c) is a column switch (rowcolumnswap, RCS) scheme;
FIG. 3 is a schematic diagram of a memristor-based integrated memory system provided by an embodiment of the present disclosure;
FIG. 4 is a flowchart of an inter-array wear leveling strategy based on a mapping table according to an embodiment of the present invention;
FIG. 5 is an exemplary diagram of an inter-array wear leveling strategy based on a mapping table provided by an embodiment of the present invention;
Fig. 6 is a schematic diagram of an online deep learning network structure of a conventional HBP, wherein (a) is a forward propagation process and (b) is a backward propagation process.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
In the present invention, the terms "first," "second," and the like in the description and in the drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
In order to solve the technical problem that an existing in-array wear balancing method is poor in effect of improving the overall service life of a system in a memristor-based memory-calculation integrated system, the invention provides the memristor-based memory-calculation integrated system, and the overall thought of the memristor-based memory-calculation integrated system is that a wear balancing algorithm is improved, and a 'hot' logic array is periodically remapped to a physical array with less wear so as to realize wear balancing among the arrays, so that the overall service life of the system is finally improved. On the basis, the online deep learning method is provided, and the whole thought is that writing of the memristor array is reduced on the basis of not affecting the online deep learning effect, so that the defects of low service life of the system caused by frequent weight updating and writing and unbalanced writing in a memory and calculation integrated system based on the memristor in the online deep learning are overcome.
The following are examples.
Example 1:
A memristor-based memory and calculation integrated system is shown in fig. 3, and comprises a memory module and a controller.
The storage module comprises a plurality of interconnected tiles, each Tile comprises a plurality of interconnected PE, each PE comprises N memristor arrays, the mapping relation from the logic ID of each PE to the physical ID is recorded in a mapping table, the logic ID is a virtual reference distributed to an upper application by a system and is used for accessing the physical array, and the physical ID uniquely represents the PE in the storage and calculation integrated system.
As shown in fig. 3, in this embodiment, each PE contains only a single memristor array, i.e., n=1. Therefore, the memristor-based memory and calculation integrated system provided by the embodiment is equivalent to removing the PE level in the original three-level (Tile/PE/Crossbar) architecture, simplifying the system architecture from the traditional three-level (Tile/PE/Crossbar) architecture to the two-level (Tile/Crossbar) architecture, thereby reducing unnecessary communication overhead and accelerating the calculation speed. In this embodiment, a plurality of tiles are interconnected by Torus routing, and it should be noted that, here, the interconnection method of the tiles is only a preferred embodiment, and is not to be construed as a unique limitation of the present invention, and other interconnection methods, such as Mesh, may be used in the present invention.
As shown in FIG. 3, in this embodiment, each Tile is composed of a plurality of memristor arrays and Tile-level input/output buffers, and is interconnected by an H-Tree.
As shown in FIG. 3, the memristor cells in each memristor array are connected by a Crossbar, i.e., a cross-point array, and optionally, in this embodiment, in order to mitigate the effects of write disturbance and sneak current, the memristor cells in the memristor array are 1T1R cells.
In this embodiment, the controller is configured to execute a mapping table-based inter-array wear-leveling (TIWL) strategy, where the strategy includes:
dividing each M times of writing into a wear balancing period, wherein M is a preset positive integer and can be correspondingly determined according to actual requirements, maintaining metadata TWC and IWC for each PE, and respectively recording the total writing times of the PE and the writing times in the current wear balancing period;
as shown in fig. 4 and 5, TIWL performs the following steps at each wear leveling cycle:
(S1) setting IWC of each PE to 0;
(S2) cumulatively recording the writing times of the memristor array in the PE in the operation stage to the corresponding IWC until the current wear balancing period is finished;
(S3) accumulating IWCs of the PEs to the corresponding TWCs;
(S4) rebuilding the mapping table such that the larger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID is;
likewise, each PE contains only 1 memristor array, and the logical ID and physical ID of the PE are the logical ID and physical ID of the memristor array, respectively;
The IWC reflects short-term writing heat of the memristor array, the TWC reflects total abrasion degree in the life cycle of the memristor array, and the embodiment realizes abrasion balance of a system level, namely abrasion balance among arrays by re-mapping the hot logic array to a physical array with less abrasion through rebuilding a mapping table, and compared with the existing abrasion balance in the array, the abrasion balance effect is better, and the service life of the whole system can be effectively prolonged;
(S5) exchanging data stored in the PE based on the current mapping table;
In the process of reconstructing the mapping table, the mapping relationship between the logical ID and the physical ID may change, and for the physical ID whose mapping relationship has changed, data stored in the corresponding memristor array needs to be exchanged to ensure the correctness of the mapping relationship.
The IWC is temporary metadata and frequently updated, in order to avoid introducing frequent writing to the memristor array due to IWC updating, as a preferred implementation, the present embodiment records the IWC into a register inside each memristor array, i.e. "wear counter" in fig. 3; TWCs are important metadata, recording the total number of cell writes in the memristor array lifecycle, requiring nonvolatile storage media for storage, in order to ensure the storage security of the TWC, in this embodiment, one or more memristor arrays in the storage module are divided into dedicated metadata storage areas;
The TWC of each PE is stored in the metadata storage area.
In contrast to the in-array wear leveling method TIWL, there is no need to record the aging state of each word line or bit line, nor to acquire the temperature of the cell. Thus, storage and computation overhead is reduced. The relevant overhead is briefly analyzed as follows:
Assuming that the IWC and TWC are respectively 32-bit and 64-bit, a memristor-based memory integrated system with the capacity of 4GB is constructed by using an array with the size of 128 multiplied by 128, the abrasion metadata occupies 24MB (accounting for 0.59 percent of 4 GB), the mapping table occupies 16MB (accounting for 0.15 percent of 4 GB), the memory overhead is in an acceptable range, when the array size is increased to 512 multiplied by 512, the memory overhead of the abrasion metadata and the mapping table is respectively reduced to 1.14MB (accounting for 0.03 percent of 4 GB) and 1.5MB (accounting for 0.04 percent of 4 GB), and the metadata of the array is fixed to 96-bit which is far smaller than the existing in-array abrasion balance strategy, namely, the row switching strategy (N multiplied by T, wherein N represents the row number and T is the bit width of a register).
In general, the memristor-based memory and calculation integrated system provided by the embodiment adopts the mapping table-based inter-array wear balancing strategy (TIWL) which can remap the hot logic array to the physical array with less wear, so that the wear balancing among the arrays is realized, and compared with the existing intra-array wear balancing method, the wear balancing effect can be improved, and finally the overall service life of the system is prolonged. In addition, the inter-array wear balance strategy of the mapping table provided by the embodiment is orthogonal to the existing intra-array wear balance strategy, can be used in combination with the existing intra-array wear balance strategy, realizes intra-array wear balance on the basis of realizing inter-array wear balance, further improves the wear balance effect, and can enable physical arrays belonging to one logic matrix to be distributed in a plurality of tiles after the mapping table is reconstructed based on the inter-array wear balance strategy of the mapping table, so that calculation tasks are dispersed in the plurality of tiles, and bandwidth contention in the tiles is relieved.
It should be noted that, according to the inter-array wear balancing strategy (TIWL) based on the mapping table provided in this embodiment, while the wear balancing effect is improved, since the calculation tasks are dispersed into multiple tiles, additional communication overhead is introduced, but the communication overhead is within an acceptable range. In addition, the communication overhead caused by TIWL can be effectively relieved by optimizing the system architecture and the Tile interconnection mode. In general, the present embodiments can obtain greater benefits with a small amount of overhead for improving the overall lifetime of memristor-based computational integration systems.
It will be readily appreciated that the above two-level (Tile/Crossbar) hierarchy architecture is merely a preferred embodiment of the present invention and should not be construed as the only limitation of the present invention. TIWL can obtain a friendly balance between mapping overhead and mapping income by adjusting scheduling granularity (namely PE size), when the number of memristor arrays contained in the PE is greater than 1, the implementation of TIWL in the integrated architecture is similar to the process, and the difference is that after the mapping relation between the logic ID and the physical ID of the PE is determined by the reconstruction mapping table, the remapping of the logic ID to the physical ID of the memristor arrays is completed according to the sequence of the memristor arrays in the PE, and in addition, metadata IWC of the PE is shared by a plurality of memristor arrays therein and is required to be stored in a register corresponding to the PE.
It is also easy to understand that in this embodiment, the implementation of TIWL does not depend on the specific structure inside the Tile, and when the internal structure of the Tile changes, for example, when the memristor unit changes, the overall life of the memristor-based integrated storage and calculation system provided by the present invention can still be effectively improved.
Example 2:
the online deep learning method based on the memristor-based memory integrated system provided in the embodiment 1, wherein the memristor-based memory integrated system is used for accelerating online deep learning.
Before explaining the technical scheme of the embodiment in detail, the following brief description is made on the existing online deep learning method:
The online deep learning can learn streaming data, keep model continuous training evolution, and can learn in streaming data scenes better than offline batch training. Fig. 6 shows a schematic diagram of a classical HBP online deep learning network structure, wherein (a) is a forward propagation process and (b) is a backward propagation process. The online deep learning network structure consists of two parts, namely a hidden layer h, wherein the hidden layer is propagated layer by layer from the first layer as in the traditional offline learning deep neural network, and the other part is an output layer o, and each output layer is connected with a Softmax classifier and is used for evaluating the learning condition of the current hidden layer. In the figure, alpha n represents the contribution weight ratio of the nth layer in all hidden layers, o k represents the Softmax output of the output layer of the kth layer classifier, and h k represents the output of the kth layer after the activation of the hidden layer.
Assuming that the number of hidden layers of a deep neural network is N, the final output of the online deep learning HBP model can be expressed by the following formula:
Wherein the method comprises the steps of
h0=x
The HBP model requires 3 parameters to learn, Θ k,Wk and α k respectively.
Where Θ k represents the parameter weight of the k-th output layer, W k represents the parameter weight of the k-th hidden layer, α k controls the contribution weight duty ratio of each layer to the output, and the classifier output of each layer obtains the final output result after weighted summation. The loss function of the model can be defined as: i.e. the classifier loss functions of each layer are weighted summed.
The contribution weight ratio α k for each layer is initialized to be uniformly distributed: In each iteration process, the output of each layer of classifier is o k, the loss function calculation is carried out through the sum of the real results, and the contribution weight ratio alpha k of each layer is updated through the following formula: Wherein t represents iteration round, beta epsilon (0, 1) is attenuation coefficient, and the contribution weight of each layer is attenuated according to the loss function after each iteration with the proportion alpha (l) After updating all contribution weight proportion, it will be standardized to make it conform to
As for the weight Θ k of the output layer, the weight is updated by the online gradient descent method, and the update process of the weight Θ k is as follows, as in the conventional offline learning:
For the update of hidden layer weights W k, unlike the conventional back propagation method, the error bias is back propagated by all output layers (i.e., each classifier o k), so its update process is expressed using the following formula:
Wherein the method comprises the steps of Is obtained by each classifier through error back propagation. It should be noted that the weight update of the k-th hidden layer requires weighted accumulation of the error bias of all the hidden layers behind itObtained.
Since the HBP optimization method reduces the weight ratio α k of the deep network to be very small, in order to limit the influence of the deep network on learning, a smoothing parameter s (s e (0, 1)) is used to control the update of α k, and the deep network is modified after the weight is updated each time: preventing deep networks from being unable to participate in the back propagation process.
On-line deep learning involves a large number of matrix operations, and memristor arrays can accelerate matrix vector multiplication operations, whereas deep learning applications involve a large number of matrix vector multiplication operations, so that acceleration can be performed by using memristor arrays, specifically, network weights W are stored in arrays, the arrays are input as vectors, and the arrays are output as calculation results.
Currently, online deep learning acceleration is still challenged with memristor-based memory and computation integration systems. Firstly, online deep learning is carried out on large-scale streaming data, the number of weight updating times (generally more than million levels) is far greater than that of traditional offline batch training, which can cause frequent writing of a memristor array and is a great challenge for the limited service life of the memristor array, secondly, the writing imbalance of the array during weight updating can lead to rapid reduction of the service life of a system, the short plate effect is prominent, and the problem of writing imbalance is more prominent due to large-scale continuous training in an online deep learning scene.
According to the online deep learning method provided by the embodiment, the memristor-based memory-calculation integrated system provided by the embodiment 1 is utilized to realize a deep learning network, and because the memory-calculation integrated system adopts an inter-array wear balancing strategy based on a mapping table, the influence of weight update of the online deep learning method on the service life of the system can be relieved under the condition that the array writing is unbalanced due to weight update, and the effective realization of the online deep learning method is ensured.
Considering that the contribution rate α of the shallow network gradually decreases and the contribution rate of the deep network gradually increases with the input of training data, the training of the online deep learning network such as HBP starts training from the shallow neurons and then gradually trains the neurons of the deep network. The final network result is obtained by weighted summation of all layers of classifiers according to the contribution rate alpha, and the network layers with low alpha have less influence on the output of the network. Based on the consideration, the embodiment improves the weight updating mode in the back propagation process of the online deep learning method, and proposes a write-optimization weight updating strategy (write-optimized parameter update, WARP) which dynamically controls the weight updating of the hidden layer according to the weight proportion of the network layer, avoids unnecessary weight writing and reduces the array abrasion.
More specifically, if α k of the hidden layer of the k-th layer is smaller than the threshold epsilon (a set constant, preferably 1/N) at each training iteration, then the contribution of that layer to the final output result of the network is also smaller, thus reducing the updating of the hidden layer weight W k. Meanwhile, considering that if the hidden layer weight is not updated continuously, the network convergence is too slow, in order to control the degree of reducing the weight update, the hidden layer weight is forcedly updated every other gamma data examples, and the weight update process can be expressed as follows:
Based on the weight updating mode, the embodiment effectively reduces the number of times of updating the weight of the hidden layer under the condition of ensuring the deep learning effect, thereby reducing the writing of an array in the integrated system, reducing the energy consumption expense and prolonging the service life of the system. As a preferred embodiment, in this embodiment, γ=2, and experiments show that setting the number of data instances spaced by the forced weight update in this way can achieve the greatest balance between the deep learning effect and the memristor array lifetime enhancement effect.
As a preferred implementation manner, the embodiment further comprises that the updating of the hidden layer weight is performed simultaneously with the step (S5), namely, the data exchange operation in TIWL is performed in the memristor-based memory-integrated system, and the embodiment reduces the extra writing introduced by the data exchange by overlapping the data exchange and the weight update because the data exchange is hidden in the weight update, thereby further reducing the energy consumption and improving the service life of the system.
In the online deep learning method, weight gradientRequires intermediate data x as input: the forward phase requires x to be stored. In the existing memristor-based memory calculation integrated system on-line deep learning method, main calculation and storage are completed by a memristor array, and weight gradient is calculated by using the memristor Two problems can exist, namely (1) frequent rewriting of the memristor array can introduce energy expenditure and shorten service life, and matrix operation of gradient calculation is degraded into vector operation in online deep learning based on large-scale streaming data, vector data is stored by directly utilizing the memristor array, and space waste of the memristor array can be caused. (2) Storing striped intermediate data in the memristor array wastes space, exacerbating wear imbalance. The intermediate data store for online deep learning is small compared to offline batch training, e.g., for training a 16-layer network (hidden layer size 100) using HBP, only about 9KB of intermediate data is needed.
Therefore, as shown in fig. 3, in this embodiment, an auxiliary computing unit (Auxiliarycomputeunit, ACU) is further disposed in the memristor-based memory-integrated system to perform vector operations, and in this embodiment, the calculation of the weight gradient is completed by the auxiliary computing unit during the back propagation of the online deep learning method, by transferring the calculation of the weight gradient from the memristor array to the auxiliary computing unit, writing of the memristor array can be reduced, energy overhead can be reduced, lifetime can be prolonged, and space can be avoided, and based on the same consideration, in this embodiment, the auxiliary computing unit is further used to complete processing of array results from different tiles, including ReLU activation, pooling pooling, cumulative summation, and the like, as an alternative implementation.
In addition, in the embodiment, a global cache is further arranged in the memristor-based memory and calculation integrated system, as shown in fig. 3, and in the embodiment, intermediate data required by weight gradient calculation is stored in the global cache, and in the embodiment, space waste can be avoided by transferring the storage position of the intermediate data from the memristor array to the global cache.
In general, the memristor-based memory integrated system provided in the embodiment 1 realizes an online deep learning method, and by further improvement, the defects of low service life of the system caused by frequent weight update and write and unbalanced write in the memristor-based memory integrated architecture of the online deep learning can be overcome.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. The memristor-based memory and calculation integrated system is characterized by comprising a storage module and a controller;
The storage module comprises a plurality of interconnected tiles, wherein each Tile comprises a plurality of interconnected PE (polyethylene), each PE comprises N memristor arrays, the mapping relation from logical ID to physical ID of each PE is recorded in a mapping table, N is a positive integer, and N is more than or equal to 1;
The controller is configured to execute an inter-array wear leveling strategy based on a mapping table, including:
Dividing each M times of writing into a wear balancing period, wherein M is a preset positive integer, maintaining metadata TWC and IWC for each PE, and recording the total writing times of the PE and the writing times in the current wear balancing period respectively;
The following steps are performed at each wear leveling cycle:
(S1) setting IWC of each PE to 0;
(S2) cumulatively recording the writing times of the memristor array in the PE in the operation stage to the corresponding IWC until the current wear balancing period is finished;
(S3) accumulating IWCs of the PEs to the corresponding TWCs;
(S4) rebuilding the mapping table such that the larger the IWC is, the smaller the TWC corresponding to the physical ID mapped by the corresponding logical ID is;
(S5) exchanging data stored in the PE based on the current mapping table.
2. The memristor-based memory integrated system of claim 1, wherein N = 1.
3. The memristor-based memory integration system of claim 2, wherein the IWCs of each PE are stored in registers internal to their memristor array.
4. The memristor-based memory-computation integration system of claim 2, wherein the plurality of tiles in the memory module are interconnected by Torus routing.
5. An online deep learning method based on a memristor-based memory integrated system as set forth in any one of claims 1 to 4, wherein the memristor-based memory integrated system is used for accelerating online deep learning;
The online deep learning method comprises the following steps:
during the back propagation, if the contribution rate of any kth hidden layer Less than a preset thresholdAnd weights from the hidden layerThe number of data instances spaced at the last update is less than a predetermined valueThen the hidden layer is not weightedUpdating otherwise, weight of the hidden layerAnd updating.
6. The online deep learning method of claim 5 further comprising updating hidden layer weights concurrently with step (S5).
7. The online deep learning method of claim 5,。
8. The online deep learning method of any one of claims 5-7, wherein the memristor-based memory and computation integration system further comprises an auxiliary computing unit for performing vector operations;
and, the calculation of the weight gradient is completed by the auxiliary calculation unit in the back propagation process of the online deep learning method.
9. The online deep learning method of claim 8 wherein the memristor-based memory computing integration system further comprises a global cache;
In addition, in the back propagation process of the online deep learning method, intermediate data required by weight gradient calculation are stored in the global cache.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310170150.6A CN116149567B (en) | 2023-02-27 | 2023-02-27 | Memristor-based memory calculation integrated system and online deep learning method |
| PCT/CN2024/070448 WO2024179183A1 (en) | 2023-02-27 | 2024-01-03 | Computing in memory system based on memristor, and online deep learning method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310170150.6A CN116149567B (en) | 2023-02-27 | 2023-02-27 | Memristor-based memory calculation integrated system and online deep learning method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116149567A CN116149567A (en) | 2023-05-23 |
| CN116149567B true CN116149567B (en) | 2025-11-21 |
Family
ID=86356111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310170150.6A Active CN116149567B (en) | 2023-02-27 | 2023-02-27 | Memristor-based memory calculation integrated system and online deep learning method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116149567B (en) |
| WO (1) | WO2024179183A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116149567B (en) * | 2023-02-27 | 2025-11-21 | 华中科技大学 | Memristor-based memory calculation integrated system and online deep learning method |
| CN119357123B (en) * | 2024-12-25 | 2025-04-18 | 湘潭大学 | Memory architecture of basic linear algebra subroutine and implementation method thereof |
| CN120179606B (en) * | 2025-05-21 | 2025-08-05 | 赛飞特工程技术集团有限公司 | Storage and computing integrated parallel processing system and method |
| CN120872899B (en) * | 2025-07-22 | 2026-08-11 | 华中科技大学 | Integrated memory and calculation microcontroller and data processing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112689829A (en) * | 2018-08-23 | 2021-04-20 | 美光科技公司 | Hybrid wear leveling for in-place data replacement media |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105068938B (en) * | 2015-08-12 | 2018-04-24 | 华中科技大学 | A kind of abrasion equilibrium method of the nonvolatile memory based on multilevel-cell |
| CN106933490A (en) * | 2015-12-29 | 2017-07-07 | 伊姆西公司 | The method and apparatus that control is written and read operation to disk array |
| CN108108128A (en) * | 2017-12-19 | 2018-06-01 | 深圳忆联信息系统有限公司 | A kind of abrasion equilibrium method and SSD for mixing SSD |
| US10811112B2 (en) * | 2018-09-29 | 2020-10-20 | Western Digital Technologies, Inc. | Wear leveling with wear-based attack detection for non-volatile memory |
| CN109800870B (en) * | 2019-01-10 | 2020-09-18 | 华中科技大学 | A Neural Network Online Learning System Based on Memristor |
| US11386319B2 (en) * | 2019-03-14 | 2022-07-12 | International Business Machines Corporation | Training of artificial neural networks |
| CN110298442B (en) * | 2019-06-04 | 2024-03-22 | 上海新储集成电路有限公司 | An intelligent partition processing method for weight information |
| CN110837253A (en) * | 2019-10-31 | 2020-02-25 | 华中科技大学 | An intelligent addressing system based on memristive synapses |
| CN110796241B (en) * | 2019-11-01 | 2022-06-17 | 清华大学 | Training method and training device of neural network based on memristor |
| CN112101549B (en) * | 2020-09-22 | 2024-05-10 | 清华大学 | Training method and device of neural network based on memristor array |
| CN112686373B (en) * | 2020-12-31 | 2022-11-01 | 上海交通大学 | Memristor-based online training reinforcement learning method |
| CN113571138B (en) * | 2021-08-10 | 2024-03-29 | 郑州大学 | Grey correlation and weight contribution-based alkali-activated mortar bonding performance analysis method |
| CN114282667B (en) * | 2021-12-08 | 2025-09-09 | 南京理工大学 | Method for enhancing security of memristor computing system through heterogeneous architecture |
| CN116149567B (en) * | 2023-02-27 | 2025-11-21 | 华中科技大学 | Memristor-based memory calculation integrated system and online deep learning method |
-
2023
- 2023-02-27 CN CN202310170150.6A patent/CN116149567B/en active Active
-
2024
- 2024-01-03 WO PCT/CN2024/070448 patent/WO2024179183A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112689829A (en) * | 2018-08-23 | 2021-04-20 | 美光科技公司 | Hybrid wear leveling for in-place data replacement media |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024179183A1 (en) | 2024-09-06 |
| CN116149567A (en) | 2023-05-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN116149567A (en) | Memory-computing integrated system based on memristor and online deep learning method | |
| CN110334799B (en) | A neural network inference and training accelerator based on the integration of storage and computing and its operation method | |
| US20250217212A1 (en) | Command processor, neural processing system and method for transmitting data thereof | |
| US20240054075A1 (en) | Neural processing device and load/store method of neural processing device | |
| CN115829002A (en) | Scheduling storage method based on memory CNN | |
| CN118626019A (en) | Memory access method, memory controller, chip and electronic device | |
| CN110738310A (en) | sparse neural network accelerators and implementation method thereof | |
| CN117271391B (en) | Cache structure and electronic equipment | |
| CN115775020B (en) | An intermediate cache scheduling method supporting in-memory CNN | |
| CN111273865B (en) | Task allocation and scheduling method based on variable scratch pad memory | |
| CN115965067B (en) | Neural network accelerator for ReRAM | |
| CN100383792C (en) | Cache database data organization method | |
| Xiao et al. | Pasm: Parallelism aware space management strategy for hybrid ssd towards in-storage dnn training acceleration | |
| CN119512500B (en) | Integrated memory and calculation acceleration circuit, chip and equipment supporting multimode convolution | |
| US20250138872A1 (en) | Command processor, neural core soc and method for obtaining context data using the same | |
| CN114819124A (en) | Memory access performance improving method of deep neural network inference processor | |
| CN119396420A (en) | A method and device for implementing large language model deployment | |
| US12287729B2 (en) | Neural processing device and method for transmitting data thereof | |
| TWI843934B (en) | A method and system for processing unstructured source data | |
| TWI721660B (en) | Device and method for controlling data reading and writing | |
| CN117687937A (en) | A page management optimization strategy based on variable memory in embedded systems | |
| Zhou et al. | Odlpim: A write-optimized and long-lifetime reram-based accelerator for online deep learning | |
| CN120069019B (en) | Momentum parallel tempering Xin Chuli circuit with low storage overhead and high resource utilization rate | |
| CN114281710B (en) | A data allocation method for multi-core embedded system based on variable scratch pad memory | |
| US20250053850A1 (en) | System and methods for generating inference information on a revisable model on a storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |