CN116110894B - Digital isolator and electronic equipment - Google Patents

Digital isolator and electronic equipment Download PDF

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Publication number
CN116110894B
CN116110894B CN202211691645.5A CN202211691645A CN116110894B CN 116110894 B CN116110894 B CN 116110894B CN 202211691645 A CN202211691645 A CN 202211691645A CN 116110894 B CN116110894 B CN 116110894B
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coil
integrated circuit
winding
signal
chip
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CN116110894A (en
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方向明
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Shenzhen Line Easy Microelectronics Co.,Ltd.
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Chongqing Xianyi Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10—Inductors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Near-Field Transmission Systems (AREA)
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Abstract

The invention provides a digital isolator and electronic equipment, which relate to the technical field of isolators, and can ensure the safety distance between a first coil and a second coil so as to improve the voltage-resistant capability of the digital isolator.

Description

Digital isolator and electronic equipment
Technical Field
The invention relates to the technical field of isolators, in particular to a digital isolator and electronic equipment.
Background
Currently, there are two main types of isolation techniques, digital isolators and optocouplers. Digital isolators are generally of two types: one is a capacitive-to-digital isolator based on an on-chip isolation capacitor, and the other is a magnetic-to-digital isolator based on an on-chip transformer. Both of these spacers are formed by forming an insulating film on the surface of the integrated circuit to provide isolation. The material of the insulating film is typically silicon dioxide or polyimide, and the thickness is typically between 10-30um DTI (distance through insulation). The optocoupler works on the principle that the light emitting diode emits light and the phototriode receives light, and a semitransparent plastic packaging material is needed to be provided in the package for light transmission, and the distance DTI between the light emitting diode and the phototriode of the optocoupler is 100-1000um.
The digital isolator has the advantages of low transmission delay and high transmission data rate (up to 100-500 Mbps) by transmitting the modulated high-frequency signals, but the dielectric layer can be damaged under high-voltage impact due to small DTI. The ultra-wide DTI of the optical coupler provides additional security, but the data rate of the optical coupler is limited in principle due to physical processes such as composite luminescence of carriers, and the data rate of the optical coupler is mainly concentrated in the range of 1k to several Mbps. On the other hand, since the material inside the package must transmit light, the manufacturing process of the optocoupler is relatively complicated.
Therefore, the isolator mainly used at present is difficult to achieve the balance between the process-accessible safety and the signal transmission, and the use efficiency of the isolator is reduced.
Disclosure of Invention
Accordingly, an objective of the present invention is to provide a digital isolator and an electronic device for alleviating the above-mentioned problems.
In a first aspect, an embodiment of the present invention provides a digital isolator, including: a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit, and a package; the first lead frame comprises a first base island and a preset number of frame exposed conductors communicated with the first base island; the second lead frame comprises a second base island and a preset number of frame exposed conductors communicated with the second base island; the frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package for soldering the digital isolator to a printed circuit board; the longitudinal height of the first base island is smaller than that of the second base island, the first base island and the second base island are overlapped in the longitudinal direction, and a preset height difference is arranged from the upper surface of the first base island to the lower surface of the second base island; the first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit is fixed on the lower surface of the second base island; the first integrated circuit is provided with a first coil, the second integrated circuit is provided with a second coil, and the projections of the first coil and the second coil in the longitudinal direction are overlapped according to a preset area; the first integrated circuit and the second integrated circuit are used for controlling the first coil and the second coil respectively so as to control signal transmission between the first coil and the second coil.
Further, in a possible embodiment, the first integrated circuit provided in the embodiment of the present invention is disposed on a first chip, and is fixed on the upper surface of the first base island through the first chip; the second integrated circuit is arranged on a second chip and is fixed on the lower surface of the second base island through the second chip.
Further, in a possible embodiment, the first coil provided in the embodiment of the present invention is disposed on the first chip, and the second coil is disposed on the second chip.
Further, in one possible embodiment, the first coil provided in the embodiment of the present invention is fixed on a first coil chip, and is fixed on the upper surface of the first base island through the first coil chip; the second coil is fixed on a second coil chip, and is fixed on the lower surface of the second base island through the second coil chip.
Further, in a possible embodiment, an upper surface of the first integrated circuit provided by the embodiment of the present invention faces to a lower surface of the second base island; the upper surface of the second integrated circuit faces to the upper surface of the first base island; the first island includes at least one set of first bonding wires for forming an electrical coupling between a pad on an upper surface of the first integrated circuit and the first leadframe; the second island includes at least one set of second bonding wires for forming an electrical coupling between pads on an upper surface of the second integrated circuit and the second leadframe.
Further, in a possible embodiment, the first chip provided in the embodiment of the present invention is electrically coupled to the first coil chip through a third bonding wire; the second chip is electrically coupled to the second coil chip by a fourth bonding wire.
Further, in a possible embodiment, the preset height difference between the upper surface of the first base island and the lower surface of the second base island provided by the embodiment of the present invention is expressed as: h=t1+t2+ts; wherein T1 represents the thickness of the first integrated circuit, T2 represents the thickness of the second integrated circuit, and Ts represents a preset safety distance.
Further, in one possible embodiment, the range of the above-mentioned safe distance provided by the embodiment of the present invention includes: 100um-1000um.
Further, in a possible embodiment, an area of the first base island provided by the embodiment of the present invention is larger than an area of the first chip; the area of the second base island is larger than that of the second chip, and the projections of the first base island and the second base island in the longitudinal direction are overlapped; the projections of the first chip and the second chip in the longitudinal direction are overlapped.
Further, in a possible embodiment, the first coil and the second coil provided by the embodiment of the present invention are spiral coils, and centers of the first coil and the second coil are longitudinally aligned; the area surrounded by the projection outer boundary of the first coil and the area surrounded by the projection outer boundary of the second coil are partially overlapped, the partially overlapped area occupies the area surrounded by the projection outer boundary of the first coil to be larger than a preset area threshold, and the partially overlapped area occupies the area surrounded by the projection outer boundary of the second coil to be larger than the preset area threshold.
Further, in one possible embodiment, the area threshold is at least 40%.
Further, in a possible embodiment, the number of the first integrated circuits on the first base island provided by the embodiment of the present invention is plural; the number of the second integrated circuits on the second base island is plural; each of the first integrated circuits is provided with one of the first coils, and each of the second integrated circuits is provided with one of the second coils.
Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention includes a coding circuit and a coil driver connected in sequence, where the coil driver is further connected to the first coil; wherein the encoding circuit is configured to receive an input signal, and the coil driver is configured to drive the first coil to generate a magnetic field signal between the first coil and the second coil according to the input signal; the second integrated circuit comprises a decoding circuit and a coil receiver which are sequentially connected; the coil receiver is connected with the second coil; the coil receiver is used for receiving the magnetic field signal, recovering the magnetic field signal into a digital signal, and the decoding circuit is used for transmitting the digital signal.
Further, in a possible embodiment, the first integrated circuit provided in the embodiment of the present invention includes a first coil driver and a first coil signal receiver; the first coil driver is connected with the first coil, and the first coil signal receiver is also connected with the first coil; the second integrated circuit is provided with a second coil driver and a second coil signal receiver, the second coil driver is connected with the second coil, and the coil signal receiver is also connected with the second coil; the first integrated circuit controls the enabling states of the first coil driver and the first coil signal receiver through a preset state level; the second integrated circuit controls the enabling states of the second coil driver and the second coil signal receiver through a preset state level so as to realize bidirectional transmission through the digital isolator; the state level of the first integrated circuit alternates between a first coil driver enabled state and a first coil signal receiver enabled state; the state level of the second integrated circuit alternates between a second coil driver enabled and a second coil signal receiver enabled state.
Further, in a possible embodiment, the first coil provided by the embodiment of the present invention includes a first winding and a second winding; the first coil driver is connected with the first winding, and the first coil signal receiver is connected with the second winding; the second coil comprises a third winding and a fourth winding; the second coil driver is connected to the third winding, and the second coil signal receiver is connected to the fourth winding.
Further, in a possible embodiment, an inductance value of the fourth winding provided in the embodiment of the present invention is greater than an inductance value of the first winding; the inductance value of the second winding is greater than the inductance value of the third winding.
Further, in a possible embodiment, the first winding and the second winding provided in the embodiment of the present invention are provided with a preset overlapped routing area; the third winding and the fourth winding are provided with preset overlapped wiring areas.
Further, in a possible embodiment, the first winding and the second winding provided in the embodiments of the present invention are spiral coils, and at least a portion of the second winding is located inside a routing area of the first winding and the second winding that are preset to overlap; the third winding and the fourth winding are also spiral coils, and at least one part of the fourth winding is positioned inside a preset overlapped wiring area of the third winding and the fourth winding.
Further, in a possible embodiment, the first integrated circuit provided by the embodiment of the present invention further includes a first signal conversion module; the first signal conversion module comprises a plurality of input interfaces, and the output end of the first signal conversion module is connected with the coding circuit; the second integrated circuit further comprises a second signal conversion module; the second signal conversion module comprises a multipath output interface, and the input end of the second signal conversion module is connected with the decoding circuit; the first signal conversion module is used for converting multiple paths of input signals into serial signals and transmitting the serial signals to the second integrated circuit; the decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the second signal conversion module.
Further, in a possible embodiment, the first integrated circuit provided in the embodiment of the present invention includes a first signal conversion module connected to the first coil driver, and a second signal conversion module connected to the first coil signal receiver; the second integrated circuit comprises a third signal conversion module connected with the second coil driver and a fourth signal conversion module connected with the second coil signal receiver; the first signal conversion module corresponds to the fourth signal conversion module, and is used for converting multiple paths of input signals of the first integrated circuit into serial signals and transmitting the serial signals to the second integrated circuit; the decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the fourth signal conversion module; the second signal conversion module corresponds to the third signal conversion module, and the third signal conversion module is used for converting multiple paths of input signals of the second integrated circuit into serial signals and transmitting the serial signals to the first integrated circuit; the decoding circuit of the first integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the third signal conversion module so as to realize bidirectional transmission of the digital isolator.
In a second aspect, an embodiment of the present invention further provides an electronic device, where the electronic device is configured with the digital isolator according to the first aspect.
The embodiment of the invention has the following beneficial effects:
the embodiment of the invention provides a digital isolator and electronic equipment, wherein the digital isolator comprises a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit and a package body; the first lead frame comprises a first base island and a preset number of frame exposed conductors communicated with the first base island; the second lead frame comprises a second base island and a preset number of frame exposed conductors communicated with the second base island; the frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package for soldering the digital isolator to the printed circuit board; the longitudinal height of the first base island is smaller than that of the second base island, the first base island and the second base island are overlapped longitudinally, and a preset height difference is arranged from the upper surface of the first base island to the lower surface of the second base island; the first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit is fixed on the lower surface of the second base island; the first integrated circuit is provided with a first coil, the second integrated circuit is provided with a second coil, and the projections of the first coil and the second coil in the longitudinal direction are overlapped according to a preset area; the first integrated circuit and the second integrated circuit are respectively used for driving the first coil and the second coil so as to control signal transmission between the first coil and the second coil, and as the preset height difference is arranged from the upper surface of the first base island to the lower surface of the second base island, the safe distance between the first coil and the second coil can be ensured, and then the voltage-resisting capacity of the digital isolator is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are some embodiments of the invention and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a digital isolator according to an embodiment of the present invention;
fig. 2 is a schematic perspective view of a digital isolator according to an embodiment of the present invention;
FIG. 3 is a top view of a digital isolator according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another digital isolator according to an embodiment of the present invention;
FIG. 5 is a top view of another digital isolator provided in an embodiment of the present invention;
FIG. 6 is a schematic diagram of a coil according to an embodiment of the present invention;
FIG. 7 is a top view of another digital isolator provided in an embodiment of the present invention;
fig. 8 is a schematic diagram of signal transmission according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of another signal transmission according to an embodiment of the present invention;
FIG. 10 is a timing diagram according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a coil according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a winding according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of another signal transmission according to an embodiment of the present invention;
fig. 14 is a schematic diagram of another signal transmission according to an embodiment of the present invention.
Icon: 11-a first lead frame; 12-a second lead frame; 13-a first integrated circuit; 14-a second integrated circuit; 10-packaging; 111-a first island; 111 a-the frame exposed conductors of the first lead frame; 121-a second island; 121 a-a frame exposed conductor of the second leadframe; 132-a first coil; 142-a second coil; 13 a-a first chip; 14 a-a second chip; 161-a first coil chip; 171-a second coil chip; 151-first bonding wires; 152-second bonding wires; 181-third bonding wire; 191-fourth bonding wires.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The digital isolator has the advantages of low transmission delay and high transmission data rate (up to 100-500 Mbps) by transmitting the modulated high-frequency signals, but the dielectric layer can be damaged under high-voltage impact due to small DTI. The optocoupler is also an isolator, and extra safety guarantee is provided by ultra-wide DTI, but the data rate of the optocoupler is limited in principle due to the physical processes of composite luminescence of carriers and the like, and the data rate of the optocoupler is mainly concentrated in the range of 1k to several Mbps. On the other hand, since the material inside the package must transmit light, the manufacturing process of the optocoupler is complicated.
Based on the above, the embodiment of the invention provides the digital isolator and the electronic equipment, so that the digital isolator has the advantages of high data transmission and low power consumption of the traditional on-chip insulating film type isolator; the traditional optocoupler has the advantages of large DTI, safety and reliability; meanwhile, the transparent material is not required to be used for secondary packaging, and the manufacturing process complexity of the digital isolator is remarkably simplified.
For the sake of understanding the present embodiment, a digital isolator disclosed in the embodiment of the present invention will be described in detail first.
In one possible implementation manner, the embodiment of the present invention provides a digital isolator, specifically, a structural schematic diagram of the digital isolator as shown in fig. 1, where fig. 1 shows a side view of the digital isolator, and as shown in fig. 1, the digital isolator in the embodiment of the present invention includes: a first lead frame 11, a second lead frame 12, a first integrated circuit 13, a second integrated circuit 14, and a package 10.
For convenience of explanation, fig. 2 also shows a schematic perspective view of a digital isolator corresponding to the side view shown in fig. 1, and fig. 3 also shows a top view of a digital isolator.
Further, as can be seen from fig. 2 and 3, the first lead frame includes a first base island 111 and a predetermined number of frame-exposed conductors 111a communicating with the first base island 111, and the second lead frame includes a second base island 121 and a predetermined number of frame-exposed conductors 121a communicating with the second base island 121; the frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package body 10 for soldering the digital isolator to the printed circuit board.
Exposed conductors of the frame refer to conductors exposed outside the molded package body for electrically coupling the external circuit and the internal chip circuit, such as gull-wing pins in SOP packages, in-line pins in DIP packages, or pads in "leadless" packages such as DFN/QFN, etc.
Further, as can be seen from fig. 1 and 2, the longitudinal height of the first base island 111 is smaller than the longitudinal height of the second base island 121, and the first base island 111 and the second base island 121 overlap in the longitudinal direction, and a preset height difference is provided from the upper surface of the first base island 111 to the lower surface of the second base island 121;
the first integrated circuit 13 is fixed on the upper surface of the first base island, and the second integrated circuit 14 is fixed on the lower surface of the second base island;
the first integrated circuit 13 is provided with a first coil 132, the second integrated circuit 14 is provided with a second coil 142, and the projections of the first coil 132 and the second coil 142 in the longitudinal direction are overlapped according to a preset area;
the first integrated circuit 13 and the second integrated circuit 14 are used for controlling the first coil 132 and the second coil 142, respectively, to control signal transmission between the first coil and the second coil.
In actual use, the longitudinal direction in the embodiment of the present invention refers to the direction indicated by arrow 21 in fig. 1 and 2, which is perpendicular to the plane of the printed circuit board when the digital isolator is soldered to the printed circuit board.
Further, in the embodiment of the present invention, the first base island and the second base island have different longitudinal heights, where in the embodiment of the present invention, taking the longitudinal height of the first base island is smaller than the longitudinal height of the second base island as an example, in other embodiments, the longitudinal height of the first base island may be set to be greater than the longitudinal height of the second base island, so long as the longitudinal heights of the first base island and the second base island meet a preset height difference, and in particular, the embodiment of the present invention is not limited to this practical use.
In addition, the digital isolator provided by the embodiment of the invention has the advantages that the upper surface of the first base island is provided with the preset height difference to the lower surface of the second base island, so that the safety distance between the first coil and the second coil can be ensured, the voltage-resistant capability of the digital isolator is further improved, meanwhile, the first coil and the second coil are controlled through the first integrated circuit and the second integrated circuit, and the light isolation is realized without a photosensitive device, so that no special requirement is required for the light transmittance of the material of the packaging body, the process requirement is reduced, the balance between the process and the signal transmission is facilitated, the use efficiency of the isolator is also improved, and the application cost is reduced.
In actual use, the first integrated circuit is usually disposed on a first chip, and is fixed on the upper surface of the first base island through the first chip; further, the second integrated circuit is also disposed on the second chip, and is fixed on the lower surface of the second base island through the second chip.
For example, the substrate (back surface) of the first chip may be bonded to the upper surface of the first island using an adhesive, and the substrate (back surface) of the second chip may be bonded to the lower surface of the second island using an adhesive.
Further, the first coil may be disposed on the first chip, and the second coil may be disposed on the second chip, that is, the coil and the integrated circuit are disposed on the same chip, which is advantageous for simplifying the packaging process of the digital isolator.
In the isolator shown in fig. 1 to 3, the coil and the integrated circuit are provided on the same chip.
Furthermore, in other embodiments, the integrated circuit and the coil may also be provided on different chips, i.e. the chip for fixing the coil and the chip for constituting the integrated circuit are provided separately. Specifically, the first coil may be fixed on the first coil chip, and the first coil may be fixed on the upper surface of the first base island through the first coil chip; the second coil is fixed on the second coil chip, and the second coil is fixed on the lower surface of the second base island through the second coil chip.
For ease of understanding, fig. 4 also shows a schematic diagram of another digital isolator, in which an integrated circuit and a coil are manufactured on different chips, and fig. 4 is also a side view, and includes, in addition to the first lead frame and the second lead frame structure shown in fig. 1, a first chip 13a provided with a first integrated circuit, a second chip 14a provided with a second integrated circuit, and a first coil chip 161 and a second coil chip 171, corresponding to the side view shown in fig. 4, fig. 5 is a top view of another digital isolator, and also includes, in addition to the first lead frame and the second lead frame structure, a first chip 13a, a second chip 14a, a first coil chip 161, and a second coil chip 171.
In practical use, the first coil chip and the second coil chip are bonded and fixed to the substrate (back surface) of the chip by an adhesive, and the digital isolator shown in fig. 4 and 5 can be manufactured by different processes because the integrated circuits and the coils are manufactured on different chips, and the manufacturing process and the area of the coils can be independently adjusted, so that better performance and cost performance are obtained.
Further, according to the structure of the first lead frame and the second lead frame in the embodiment of the invention, the upper surface of the first integrated circuit faces to the lower surface of the second base island; the upper surface of the second integrated circuit faces to the upper surface of the first base island; and the first base island comprises at least one group of first bonding wires, wherein the first bonding wires are used for forming electric coupling between the bonding pads on the upper surface of the first integrated circuit and the first lead frame; the first bonding wire 151 is shown in fig. 1 to 3. The corresponding second islands also contain at least one set of second bonding wires, second bonding wires 152 in fig. 1-3, for forming electrical couplings between pads on the upper surface of the second integrated circuit and the second leadframe.
Further, for embodiments in which the integrated circuit and coil are fabricated on different chips, the digital isolator is also provided with bonding wires. Specifically, as shown in fig. 4 and 5, the first chip 13a is electrically coupled to the first coil chip 161 through the third bonding wire 181; the second chip 14a is electrically coupled to the second coil chip 171 through the fourth bonding wire 191. Meanwhile, in fig. 4 and 5, a first bonding wire 151 is further included, and in this case, the first bonding wire 151 forms an electrical coupling between a pad provided on a surface of the first chip 13a on the first integrated circuit and the first lead frame, and similarly, the second bonding wire 152 forms an electrical coupling between a pad provided on the second chip 14a of the second integrated circuit and the second lead frame.
Further, the preset height difference between the upper surface of the first island and the lower surface of the second island in the embodiment of the present invention is generally expressed as: h=t1+t2+ts;
wherein T1 represents the thickness of the first integrated circuit, such as T1 shown in fig. 4, may include the thickness of the first chip and the first coil chip, and generally refers to the thickness of the chip including the coil structure; similarly, as shown in fig. 4, T2 represents the thickness of the second integrated circuit, and Ts represents a predetermined safety distance. In specific implementation, the range of the safety distance includes: the safety distance is preferably between 200um and 500um, in particular between 100um and 1000 um. In actual use, the safe distance is selected to provide galvanic isolation (galvanic isolation) between the first and second integrated circuits, which when disposed between the first and second chips, likewise provide galvanic isolation between the first and second chips.
Specifically, the safety distance of the embodiment of the present invention is different from the conventional capacitive-coupled digital isolator and magnetic-coupled digital isolator in that: 1. the safety distance in the embodiment of the invention is between 100um and 1000um, which is 10 times to 100 times that of the traditional digital isolator, and can realize extremely high pressure resistance; 2. the isolation medium, i.e. the packaging material, such as epoxy material, resin material for plastic packaging, or plastic packaging material filled with insulator filler (filler), etc. may be disposed between the safety distances, and the physical location of the safety distances is located outside the chips of the integrated circuit, so that when EOS (electrostatic overstress) event, ESD (electrostatic discharge) event, or other destructive event occurs on the chips of the integrated circuit, such as the first chip or the second chip itself, the isolation medium located outside the two chips will not be destructively affected. Therefore, even if two chips are damaged, isolation protection can be provided between the first chip and the second chip, and the stability of the digital isolator is further improved.
Further, in actual use, since the first chip and the first coil chip are generally disposed on the first base island, the area of the first base island in the embodiment of the present invention is generally larger than that of the first chip; similarly, the area of the second base island is larger than that of the second chip.
Preferably, the area of the first base island is larger than the area covered by the range of 200um of each of four sides of the first chip; the area of the second base island is larger than the area covered by the range of 200um of each of four sides of the second chip; for example, taking the top view shown in fig. 3 as an example, since the first base island and the second base island overlap in the longitudinal direction, the second base island and the second chip use a dotted line in fig. 3 for convenience of drawing. In the embodiment of the invention, the areas of the first base island and the second base island are larger than the areas of the chips (the first chip and the second chip) mainly have two purposes: firstly, in order to facilitate the chip to be fixed on the base island, physical support is provided for the chip; and secondly, the base island is used as a good conductor, can play a role of shielding an external electromagnetic field from interfering the first chip and the second chip, and can reduce the outward radiation of the electromagnetic field generated by the first chip/coil and the second chip/coil.
Further, in order to facilitate signal transmission between the first coil and the second coil, in the embodiment of the present invention, the projections of the first base island and the second base island in the longitudinal direction are coincident; the first chip and the second chip are overlapped in the longitudinal projection, and meanwhile, the first coil and the second coil are overlapped in the longitudinal projection.
Specifically, in the embodiment of the present invention, the first coil and the second coil are spiral coils, and the centers of the first coil and the second coil are longitudinally aligned, where the longitudinal direction is consistent with the direction indicated by the arrow 21 in fig. 1 and fig. 2, and the longitudinal alignment of the centers of the first coil and the second coil means that the projections of the centers of the first coil and the second coil in the longitudinal direction can be overlapped, or the distance between the projections of the centers of the first coil and the second coil in the longitudinal direction is less than a certain threshold value, so as to meet the alignment requirement.
For ease of understanding, fig. 6 shows a schematic diagram of a coil including a first coil 132 and a second coil 142, specifically, as shown in fig. 6, an area surrounded by a projection outer boundary of the first coil 132 and an area surrounded by a projection outer boundary of the second coil 142 are partially overlapped, and the partially overlapped area occupies an area surrounded by the projection outer boundary of the first coil to be greater than a preset area threshold, and the partially overlapped area occupies an area surrounded by the projection outer boundary of the second coil to be greater than the preset area threshold. In the embodiment of the present invention, the area threshold is generally expressed as a percentage, and is generally set to 40%, that is, 40% or more, preferably 80% or more of the area surrounded by the projection outer boundary of the first coil or the second coil.
It should be noted that, in the embodiment of the present invention, the area surrounded by the projected outer boundary of the first coil and the area surrounded by the projected outer boundary of the second coil refer to the area surrounded by the projected outer boundary of the coil, and the area of the hollow portion inside the coil is not subtracted. Because of design requirements, the area surrounded by the projection outer boundary of the first coil and the area surrounded by the projection outer boundary of the second coil can be the same or different, and therefore, the proportion of the projection overlapping area to the peripheral area of the first coil and the second coil is required in the embodiment of the invention. Moreover, due to manufacturing process variations, the two coils cannot be aligned completely at the center, so that the alignment degree is described by the proportion of the projected area to the total area, so as to ensure the performance of the digital isolator.
Further, for some usage scenarios with a large bandwidth requirement, the number of the first integrated circuits on the first base island may be plural in order to obtain a larger communication bandwidth; meanwhile, the number of the second integrated circuits on the second base island is plural. For ease of understanding, fig. 7 also shows a top view of another digital isolator, wherein fig. 7 shows an embodiment comprising two first integrated circuits and two second integrated circuits, in particular, in fig. 7, a first base island 111 is shown, and two first integrated circuits 13 on the first base island 111, and a second base island 121, and two second integrated circuits 14 on the second base island 121. In addition, a plurality of bonding wires are also shown in fig. 7, and in fig. 7, a separate schematic view (left side) of the first lead frame and the second lead frame, and an overall schematic view (right side) of the assembly into a digital isolator are shown. Specifically, as shown in fig. 7, each first integrated circuit is configured with one first coil 132, and each second integrated circuit is configured with one second coil 142. Based on the embodiment of the plurality of coils shown in fig. 7, the first coil and the second coil of each group have overlapping areas in the longitudinal direction, and the overlapping area of the area surrounded by the first coil projection outer boundary and the area surrounded by the second coil projection outer boundary occupies 40% or more, preferably 80% or more of the area surrounded by the first coil projection outer boundary (and the area surrounded by the second coil projection outer boundary).
It should be understood that fig. 7 is an illustration taking an example in which each base island includes two sets of coils, and in other embodiments, the number of coils may be set according to actual use, which is not limited by the embodiment of the present invention.
In actual use, in order to realize that the integrated circuit controls the coil, the first integrated circuit in the embodiment of the invention comprises a coding circuit and a coil driver which are sequentially connected, and the coil driver is also connected with the first coil; the encoding circuit is used for receiving an input signal, the coil driver is used for driving the first coil according to the input signal, and a magnetic field signal is generated between the first coil and the second coil; the second integrated circuit comprises a decoding circuit and a coil receiver which are connected in sequence; the coil receiver is connected with the second coil; the coil receiver is used for receiving the magnetic field signal, recovering the magnetic field signal into a digital signal, and the decoding circuit is used for transmitting the digital signal.
For ease of understanding, fig. 8 shows a schematic diagram of signal transmission, specifically, fig. 8 shows an encoding circuit B111 and a coil driver B11, where in the embodiment of the present invention, the coil driver is denoted by TX, and the coil driver is connected to a first coil 132, and further, fig. 8 shows a decoding circuit B211 and a coil receiver B21 in a second integrated circuit, where in the embodiment of the present invention, the coil receiver is denoted by RX; the coil receiver is connected to the second coil 142. In addition, fig. 8 also shows a safety distance, that is, DTI, and in fig. 8, a diagonal line is used to indicate that an isolation medium is generally disposed in the safety distance, so that an isolation medium layer is formed, and a specific material of the isolation medium may be set according to actual use requirements, which is not limited in the embodiment of the present invention.
Specifically, the encoding circuit B111 generates an encoded signal according to the level of the input signal, for example, when the level of the input signal is high, the encoded signal forms a first characteristic signal at a first coil through the coil driver B11; when the level of the input signal is low, the encoded signal forms a second characteristic signal on the first coil through the coil driver B11, the first coil forms a magnetic field, namely B13 indicated by an arrow, under the action of the first characteristic signal and the second characteristic signal, the magnetic field propagates to the vicinity of the second coil in a medium of a preset height difference, such as an insulating medium, namely a magnetic field B23 indicated by an arrow, and forms a receiving signal at both ends of the second coil.
At this time, the coil receiver B21 of the second integrated circuit restores the received signal to a digital signal, and then determines that the signal satisfies the first characteristic or the second characteristic through the decoding circuit B211 of the second integrated circuit, so as to set the output level to be consistent with the input level, thereby realizing the transmission of the signal.
Specifically, the first characteristic signal may be a first number of pulses, and the second characteristic signal corresponds to a second number of pulses; or: the first characteristic signal is a pulse of a first polarity and the second characteristic signal corresponds to a pulse of a second polarity, or: the first characteristic signal is an oscillation of a first duration, the second characteristic signal is an oscillation-free or second duration signal, or the first characteristic signal is a signal combination of at least one of the above three signals, the second characteristic signal is a corresponding combined signal, etc., and specifically, the signal is based on an actual input signal, which is not limited in the embodiment of the present invention.
It should be understood that fig. 8 illustrates an implementation of unidirectional transmission of digital signals, and in other embodiments, the digital isolator in the embodiments of the present invention may also implement bidirectional transmission of digital signals.
Corresponding to the implementation of the bidirectional transmission, the first integrated circuit in the embodiment of the invention comprises a first coil driver and a first coil signal receiver; the first coil driver is connected with the first coil, and the first coil signal receiver is also connected with the first coil; the corresponding second integrated circuit is provided with a second coil driver and a second coil signal receiver, the second coil driver is connected with the second coil, and the coil signal receiver is also connected with the second coil; when signal bidirectional transmission is realized, the first integrated circuit controls the enabling states of the first coil driver and the first coil signal receiver through a preset state level; the second integrated circuit controls the enabling states of the second coil driver and the second coil signal receiver through a preset state level so as to realize bidirectional transmission through the digital isolator.
For ease of understanding, fig. 9 shows another signal transmission schematic diagram to further explain the bidirectional transmission process.
Specifically, as shown in fig. 9, the coil signal processing device includes a first coil driver TX1 and a first coil signal receiver RX1, a second coil driver TX2 and a second coil signal receiver RX2, and an encoding circuit connected to each coil driver and a decoding circuit connected to each coil signal receiver.
In particular, the first integrated circuit has two STATEs controlled by a STATE level (STATE): a first level driving state (e.g., logic level 0 for example and without limitation) and a second level receiving state (e.g., logic level 1 for example); the corresponding second integrated circuit has two states controlled by logic levels: a drive state (for example, logic level 0, without limitation) and a receive state (for example, logic level 1); when the logic control of the integrated circuit is in a driving state, the coil driver can be set to an enabling state through the control state circuit; when the logic control of the integrated circuit is in the receive state, the coil driver may be set to a disabled state, e.g., TX1 output to a high resistance state, by the control state circuit. For example, when the state level of the first chip corresponding to the first integrated circuit is a first level, if the input of the first chip is at a high level at this time, a first characteristic signal is transmitted to the first coil, and if the input of the first chip is at a low level at this time, a second characteristic signal is transmitted to the first coil; if the first chip receives the first characteristic signal at the moment when the state level is the second level, setting the output to be high level through the decoding circuit; if the first chip receives the second characteristic signal at this time, the output is set to a low level by the decoding circuit, and a similar signal transmission mode is also adopted for the second chip corresponding to the second integrated circuit, and the specific level state can be set according to the actual use condition, which is not limited by the embodiment of the invention.
Further, when the state level of the first chip corresponding to the first integrated circuit is the first level and the transmission of the characteristic signal is completed by a first delay (delta ta), the time sequence circuit of the first chip can control the state level of the first integrated circuit to be converted into the second level;
when the state level of the first chip corresponding to the first integrated circuit is a second level, after a second delay (delta tb) is performed after the characteristic signal is received, the time sequence circuit of the first chip can control the state level of the first integrated circuit to be converted into the first level;
the second chip of the second integrated circuit may also be subjected to the similar level conversion process, so as to realize automatic triggering of state change between the first integrated circuit and the second integrated circuit, realize alternating signal transmission and reception, and thus realize bidirectional signal transmission by using a single channel, for convenience of understanding, fig. 10 shows a timing chart, as shown in fig. 10, respectively showing the state level of the first chip corresponding to the first integrated circuit and the state level of the second chip of the second integrated circuit, where the timing of the state level of the first chip is represented by state1, the timing of the state level of the second chip is represented by state2, and in fig. 10, the Input (Input), the Output (Output) of the first integrated circuit and the timing chart of the driver TX are also respectively shown.
Also, as can be seen from fig. 10, the state level of the first integrated circuit alternates between the first coil driver enabled and the first coil signal receiver enabled states; the state level of the second integrated circuit alternates between a second coil driver enabled and a second coil signal receiver enabled state. And, a change from the driver enable state to the receiver enable state is determined by the drive signal time and the first delay time; a change from a receiver-enabled state to a transmitter-enabled state is determined by a second delay time from when the receiver receives the signal to begin timing; and the second delay time is greater than the sum of the drive signal time and the first delay time.
In practical use, after the first chip or the second chip transmits the signal, the first chip or the second chip usually automatically shifts to the receiving state after waiting for a certain time. When the first chip or the second chip is in a receiving state, the signal is received, and a period of time is waited for to complete the signal receiving, namely, the transmission mode is shifted.
In general, the second delay must be greater than the duration of the longer of the first and second characteristic signals, so as to ensure that the signal is received long enough to ensure that the transmitted signal is received in its entirety. If the second delay is too short, only a portion of the transmitted signal may be received, possibly resulting in an output error, and therefore, the second delay may be set to meet the signal reception requirements.
Further, in order to facilitate the bidirectional transmission, the first coil in the embodiment of the present invention includes a first winding and a second winding, specifically, fig. 11 shows a schematic coil diagram including a first winding B1A and a second winding B1B, where the first coil driver TX1 is connected to the first winding B1A, and the first coil signal receiver RX1 is connected to the second winding B1B; the corresponding second coil also includes two windings, namely, a third winding B2A and a fourth winding B2B in fig. 11, wherein the second coil driver TX2 is connected to the third winding B2A, and the second coil signal receiver RX2 is connected to the fourth winding B2B.
Preferably, the inductance value of the fourth winding in the embodiment of the present invention is greater than the inductance value of the first winding; the inductance value of the second winding is larger than that of the third winding, that is, the coil shown in (1) in fig. 11, and the coil length is shown as an example of the inductance value, the length of the fourth winding B2B is larger than that of the first winding B1A, and the length of the second winding B1B is larger than that of the third winding B2A.
The requirement of the inductance value in the embodiment of the present invention is generally determined by the safety distance, and since the distance between the two coils in the embodiment of the present invention is longer, that is, the range of the safety distance includes: 100um-1000um, so the coupling coefficient is not high, and the coupling coefficient is mainly determined by the outer diameter of the coil and the distance between the receiving coil and the transmitting coil, so the ratio of the fourth winding to the first winding to the ratio of the second winding to the third winding are improved, the voltage gain can be increased, and the higher voltage gain can be realized under the condition of weaker coupling coefficient.
However, since the area of the chip on which the coils are disposed is limited, or the areas of the first base island and the second base island are limited, and considering that the cost of disposing two sets of mutually independent coils is high, the first winding and the second winding in the embodiment of the present invention are provided with the preset overlapped routing areas; meanwhile, the third winding and the fourth winding are also provided with preset overlapped wiring areas. I.e. the overlapping schematic of the two sets of coils shown in fig. 11 (2), it can be seen that the first winding and the second winding have a common trace portion; the third winding and the fourth winding have a common trace portion.
Based on the coil schematic diagram shown in fig. 11, the first winding and the second winding, and the third winding and the fourth winding share a part of wiring, which is beneficial to saving the area of the whole digital isolator, realizing miniaturization and reducing the cost of the digital isolator. Meanwhile, for any side of the coil, the structure of the winding connected to the circuit changes with time, and at different moments, the physical structure of the winding connected to the circuit is different (equivalent to a dynamically changing coil), so that higher voltage gain can be obtained, and meanwhile, bidirectional transmission of signals is realized.
Further, in the embodiment of the present invention, the first winding and the second winding are spiral coils, and at least a portion of the second winding is located inside a routing area of the first winding and the second winding, which are preset to overlap; similarly, the third winding and the fourth winding are spiral coils, and at least one part of the fourth winding is positioned inside a preset overlapped wiring area of the third winding and the fourth winding.
For ease of understanding, fig. 12 also shows a schematic diagram of a winding, with reference to fig. 12, showing one embodiment where the coils have a common trace, and for ease of illustration, only one coil is used for illustration.
As shown in fig. 12, it is assumed that the second windings are in the order of helixA and D are connected to a second coil signal receiver RX2, while the first winding is +.>Thus (S)>Is a common wiring part of the first winding and the second winding, and +.>This part is located +.>This has two benefits: and at least one part of the second winding is positioned in the common wiring part of the first winding and the second winding, so that the inductance value of the second winding is larger than that of the first winding, and meanwhile, the coupling between the second winding and the first winding is determined by the common wiring part of the two coils positioned on the outer side, and the coupling coefficient is higher.
Furthermore, the digital isolator provided by the embodiment of the invention can also meet the isolation and transmission of multiple paths of signals. Specifically, for the implementation of unidirectional signal transmission, the first integrated circuit in the embodiment of the present invention further includes a first signal conversion module; the first signal conversion module comprises multiple paths of input interfaces, and the output end of the first signal conversion module is connected with the coding circuit; the second integrated circuit further comprises a second signal conversion module; the second signal conversion module comprises a multipath output interface, and the input end of the second signal conversion module is connected with the decoding circuit; the first signal conversion module is used for converting the multipath input signals into serial signals and transmitting the serial signals to the second integrated circuit; the decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the second signal conversion module.
Specifically, fig. 13 shows another signal transmission schematic diagram, corresponding to the signal transmission schematic diagram shown in fig. 8, where the first integrated circuit further includes a first signal conversion module 120, and in a specific implementation, the first signal conversion module is usually a parallel-to-serial P2S module, and can convert INPUT signals INPUT1 to INPUT of the multiple INPUT interfaces into serial signals to be transmitted to the second integrated circuit, and the serial signals are decoded by a decoding circuit of the second integrated circuit, and then the multiple signals are recovered and output by a second signal conversion module 122 disposed in the second integrated circuit, where the second signal conversion module is a serial-to-parallel S2P module, so as to recover the multiple signals into INPUT1 to INPUT for output.
Further, corresponding to the bidirectional transmission process shown in fig. 9, fig. 14 also shows another signal transmission schematic diagram, specifically, as shown in fig. 14, in the embodiment of the present invention, the first integrated circuit includes a first signal conversion module 130 connected to the first coil driver, and a second signal conversion module 131 connected to the first coil signal receiver; correspondingly, the second integrated circuit includes a third signal conversion module 140 connected to the second coil driver, and a fourth signal conversion module 141 connected to the second coil signal receiver.
The first signal conversion module is corresponding to the fourth signal conversion module, and is used for converting multiple paths of input signals of the first integrated circuit into serial signals and transmitting the serial signals to the second integrated circuit; the decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the fourth signal conversion module;
further, the second signal conversion module corresponds to a third signal conversion module, and the third signal conversion module is used for converting multiple paths of input signals of the second integrated circuit into serial signals and transmitting the serial signals to the first integrated circuit; the decoding circuit of the first integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the third signal conversion module so as to realize bidirectional transmission of the digital isolator.
In particular, in fig. 14, the first signal conversion module 130 on the first integrated circuit is equivalent to an N-way parallel-to-serial P2S module, and converts N-way input signals into serial types, and is sent by the first coil driver; the fourth signal conversion module on the second integrated circuit is equivalent to an N-path serial-to-parallel S2P module, and the received signals are recovered into N-path parallel signals to be output; similarly, the third signal conversion module on the second integrated circuit is equivalent to an M-path parallel-to-serial P2S module, and converts the M-path input signal into a serial signal to be sent out by the second coil driver; the second signal conversion module on the first integrated circuit is equivalent to an M-path serial-to-parallel S2P module, and recovers the received signals into M-path parallel signals for output.
Through the embodiments of fig. 13 and fig. 14, unidirectional or bidirectional transmission of multiple signals can be implemented, and the specific number of signal channels can be set according to actual use conditions, which is not limited in this embodiment of the present invention.
In summary, the digital isolator provided by the embodiment of the invention has the advantages of high data transmission and low power consumption of the traditional on-chip insulating film isolator; the traditional optocoupler has the advantages of large DTI, safety and reliability; meanwhile, the secondary packaging is not required to be performed by using a transparent material, so that the complexity of the manufacturing process of the isolator is remarkably simplified, and meanwhile, high-speed signal transmission can be realized.
Further, on the basis of the above embodiment, the embodiment of the present invention further provides an electronic device, which is configured with the digital isolator described in the above embodiment.
The electronic equipment provided by the embodiment of the invention has the same technical characteristics as the digital isolator provided by the embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
The digital isolator and the computer program product of the electronic device provided by the embodiments of the present invention include a computer readable storage medium storing program codes, where the instructions included in the program codes may be used to execute the method described in the previous embodiment, and the specific implementation may refer to the previous embodiment and will not be repeated herein.
It will be clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the electronic device described above may refer to the corresponding process in the foregoing embodiment, which is not described herein again.
In addition, in the description of embodiments of the present invention, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood by those skilled in the art in specific cases.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention for illustrating the technical solution of the present invention, but not for limiting the scope of the present invention, and although the present invention has been described in detail with reference to the foregoing examples, it will be understood by those skilled in the art that the present invention is not limited thereto: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (20)

1. A digital isolator, the digital isolator comprising: a first lead frame, a second lead frame, a first integrated circuit, a second integrated circuit, and a package;
the first lead frame comprises a first base island and a preset number of frame exposed conductors communicated with the first base island; the second lead frame comprises a second base island and a preset number of frame exposed conductors communicated with the second base island;
The frame exposed conductors of the first lead frame and the frame exposed conductors of the second lead frame extend to the outside of the package for soldering the digital isolator to a printed circuit board;
the longitudinal height of the first base island is smaller than that of the second base island, the first base island and the second base island are overlapped in the longitudinal direction, and a preset height difference is arranged from the upper surface of the first base island to the lower surface of the second base island;
the first integrated circuit is fixed on the upper surface of the first base island, and the second integrated circuit is fixed on the lower surface of the second base island;
the first integrated circuit is provided with a first coil, the second integrated circuit is provided with a second coil, and the projections of the first coil and the second coil in the longitudinal direction are overlapped according to a preset area;
the first integrated circuit and the second integrated circuit are respectively used for controlling the first coil and the second coil so as to control signal transmission between the first coil and the second coil;
wherein the first integrated circuit comprises a first coil driver and a first coil signal receiver;
the first coil driver is connected with the first coil, and the first coil signal receiver is also connected with the first coil;
The second integrated circuit is provided with a second coil driver and a second coil signal receiver, the second coil driver is connected with the second coil, and the coil signal receiver is also connected with the second coil;
the first integrated circuit controls the enabling states of the first coil driver and the first coil signal receiver through a preset state level; the second integrated circuit controls the enabling states of the second coil driver and the second coil signal receiver through a preset state level so as to realize bidirectional transmission through the digital isolator;
the state level of the first integrated circuit alternates between a first coil driver enabled state and a first coil signal receiver enabled state;
the state level of the second integrated circuit alternates between a second coil driver enabled and a second coil signal receiver enabled state.
2. The digital isolator of claim 1, wherein the first integrated circuit is disposed on a first chip, and is secured to an upper surface of the first island by the first chip;
the second integrated circuit is arranged on a second chip and is fixed on the lower surface of the second base island through the second chip.
3. The digital isolator of claim 2, wherein the first coil is disposed on the first chip and the second coil is disposed on the second chip.
4. The digital isolator of claim 2, wherein the first coil is secured to a first coil chip, the first coil chip being secured to an upper surface of the first island;
the second coil is fixed on a second coil chip, and is fixed on the lower surface of the second base island through the second coil chip.
5. The digital isolator of claim 1, wherein an upper surface of the first integrated circuit is oriented toward a lower surface of the second island;
the upper surface of the second integrated circuit faces to the upper surface of the first base island;
the first island includes at least one set of first bonding wires for forming an electrical coupling between a pad on an upper surface of the first integrated circuit and the first leadframe;
the second island includes at least one set of second bonding wires for forming an electrical coupling between pads on an upper surface of the second integrated circuit and the second leadframe.
6. The digital isolator of claim 4, wherein the first chip is electrically coupled to the first coil chip by a third bond wire;
the second chip is electrically coupled to the second coil chip by a fourth bonding wire.
7. The digital isolator of claim 1, wherein the predetermined height difference between the upper surface of the first island and the lower surface of the second island is expressed as:
H＝T1+T2+Ts；
wherein T1 represents the thickness of the first integrated circuit, T2 represents the thickness of the second integrated circuit, and Ts represents a preset safety distance.
8. The digital isolator of claim 7, wherein the range of safe distances comprises: 100um-1000um.
9. The digital isolator of claim 2, wherein an area of the first base island is greater than an area of the first chip;
the area of the second base island is larger than that of the second chip;
the projections of the first base island and the second base island in the longitudinal direction are overlapped;
the projections of the first chip and the second chip in the longitudinal direction are overlapped.
10. The digital isolator of claim 1, wherein the first coil and the second coil are helical coils, and wherein centers of the first coil and the second coil are longitudinally aligned;
The area surrounded by the projection outer boundary of the first coil and the area surrounded by the projection outer boundary of the second coil are partially overlapped, the partially overlapped area occupies the area surrounded by the projection outer boundary of the first coil to be larger than a preset area threshold, and the partially overlapped area occupies the area surrounded by the projection outer boundary of the second coil to be larger than the preset area threshold.
11. The digital isolator of claim 10, wherein the area threshold is at least 40%.
12. The digital isolator of claim 1, wherein the number of the first integrated circuits on the first island is a plurality; the number of the second integrated circuits on the second base island is plural;
each of the first integrated circuits is provided with one of the first coils, and each of the second integrated circuits is provided with one of the second coils.
13. The digital isolator of claim 1, wherein the first integrated circuit comprises a coding circuit and a coil driver connected in sequence, the coil driver further connected to the first coil;
wherein the encoding circuit is configured to receive an input signal, and the coil driver is configured to drive the first coil to generate a magnetic field signal between the first coil and the second coil according to the input signal;
The second integrated circuit comprises a decoding circuit and a coil receiver which are sequentially connected; the coil receiver is connected with the second coil;
the coil receiver is used for receiving the magnetic field signal, recovering the magnetic field signal into a digital signal, and the decoding circuit is used for transmitting the digital signal.
14. The digital isolator of claim 1, wherein the first coil comprises a first winding and a second winding;
the first coil driver is connected with the first winding, and the first coil signal receiver is connected with the second winding;
the second coil comprises a third winding and a fourth winding;
the second coil driver is connected to the third winding, and the second coil signal receiver is connected to the fourth winding.
15. The digital isolator of claim 14, wherein an inductance value of the fourth winding is greater than an inductance value of the first winding;
the inductance value of the second winding is greater than the inductance value of the third winding.
16. The digital isolator of claim 14, wherein the first winding and the second winding are provided with a predetermined overlapping trace area;
The third winding and the fourth winding are provided with preset overlapped wiring areas.
17. The digital isolator of claim 15, wherein the first winding and the second winding are helical coils and at least a portion of the second winding is located inside a predetermined overlapping trace area of the first winding and the second winding;
the third winding and the fourth winding are also spiral coils, and at least one part of the fourth winding is positioned inside a preset overlapped wiring area of the third winding and the fourth winding.
18. The digital isolator of claim 13, wherein the first integrated circuit further comprises a first signal conversion module;
the first signal conversion module comprises a plurality of input interfaces, and the output end of the first signal conversion module is connected with the coding circuit;
the second integrated circuit further comprises a second signal conversion module;
the second signal conversion module comprises a multipath output interface, and the input end of the second signal conversion module is connected with the decoding circuit;
the first signal conversion module is used for converting multiple paths of input signals into serial signals and transmitting the serial signals to the second integrated circuit;
The decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the second signal conversion module.
19. The digital isolator of claim 1, wherein the first integrated circuit includes a first signal conversion module coupled to the first coil driver and a second signal conversion module coupled to the first coil signal receiver;
the second integrated circuit comprises a third signal conversion module connected with the second coil driver and a fourth signal conversion module connected with the second coil signal receiver;
the first signal conversion module corresponds to the fourth signal conversion module, and is used for converting multiple paths of input signals of the first integrated circuit into serial signals and transmitting the serial signals to the second integrated circuit; the decoding circuit of the second integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the fourth signal conversion module;
the second signal conversion module corresponds to the third signal conversion module, and the third signal conversion module is used for converting multiple paths of input signals of the second integrated circuit into serial signals and transmitting the serial signals to the first integrated circuit; the decoding circuit of the first integrated circuit is used for decoding the serial signal and recovering and outputting the serial signal through the third signal conversion module so as to realize bidirectional transmission of the digital isolator.
20. An electronic device, characterized in that it is provided with a digital isolator as claimed in any one of claims 1 to 19.
CN202211691645.5A 2022-12-27 2022-12-27 Digital isolator and electronic equipment Active CN116110894B (en)

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CN102906833A (en) * 2010-06-30 2013-01-30 美国国家半导体公司 Galvanic isolation transformer
CN110010509A (en) * 2018-01-05 2019-07-12 光宝新加坡有限公司 Double lead frame magnetic coupling encapsulating structure and its manufacturing method
CN114664801A (en) * 2022-03-02 2022-06-24 矽力杰半导体技术(杭州)有限公司 Digital isolator element

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US8462003B2 (en) * 2010-09-21 2013-06-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Transmitting and receiving digital and analog signals across an isolator
US9960671B2 (en) * 2014-12-31 2018-05-01 Avago Technologies General Ip (Singapore) Pte. Ltd. Isolator with reduced susceptibility to parasitic coupling

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Publication number Priority date Publication date Assignee Title
JP2009071253A (en) * 2007-09-18 2009-04-02 Fuji Electric Device Technology Co Ltd Isolator
CN102906833A (en) * 2010-06-30 2013-01-30 美国国家半导体公司 Galvanic isolation transformer
CN110010509A (en) * 2018-01-05 2019-07-12 光宝新加坡有限公司 Double lead frame magnetic coupling encapsulating structure and its manufacturing method
CN114664801A (en) * 2022-03-02 2022-06-24 矽力杰半导体技术(杭州)有限公司 Digital isolator element

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