CN116069116A - LDO circuit of low dropout linear regulator, dynamic compensation method and electronic equipment - Google Patents

LDO circuit of low dropout linear regulator, dynamic compensation method and electronic equipment Download PDF

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CN116069116A
CN116069116A CN202310219621.8A CN202310219621A CN116069116A CN 116069116 A CN116069116 A CN 116069116A CN 202310219621 A CN202310219621 A CN 202310219621A CN 116069116 A CN116069116 A CN 116069116A
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tube
ldo circuit
value
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load
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贾要水
徐佳豪
黄浩键
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Beijing Eswin Computing Technology Co Ltd
Guangzhou Quanshengwei Information Technology Co Ltd
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Beijing Eswin Computing Technology Co Ltd
Guangzhou Quanshengwei Information Technology Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The embodiment of the application discloses a low dropout linear regulator LDO circuit, a dynamic compensation method and electronic equipment, and relates to the field of integrated circuits. The LDO circuit comprises a controlled resistor, a load element and a control unit, wherein the control unit is respectively connected with the controlled resistor and the load element. The control unit determines a first resistance value of a controlled resistor in the LDO circuit and power of a load element in the LDO circuit based on a load current value of the LDO circuit; the first resistance is inversely related to a load current value in the LDO circuit; determining a first frequency corresponding to a compensation zero point in the LDO circuit based on the first resistance value; and compensating a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency. By adopting the embodiment of the application, the consistent change rate of the controlled resistor and the load element along with the load current value is realized, and the frequency of the output pole is effectively and dynamically compensated through the compensation zero point which dynamically changes along with the frequency of the output pole, so that the oscillation of the LDO circuit is avoided.

Description

LDO circuit of low dropout linear regulator, dynamic compensation method and electronic equipment
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to an LDO circuit, a dynamic compensation method, and an electronic device.
Background
LDO (Low Dropout Regulator, low dropout linear regulator) circuits generally consist of error amplifiers, output power transistors, resistor feedback networks, frequency compensation networks, off-chip load capacitors and other modules, and a negative feedback loop is formed by the modules, so that stable, high-interference-resistance and low-ripple power supply voltage (namely, the output voltage of the LDO circuit) is provided for electronic equipment.
Along with the development trends of increasingly smaller process size, increasingly higher integration level, increasingly stronger performance, increasingly lower power consumption, increasingly lower noise and the like of the integrated circuit, higher requirements are put forward on the stability of the output voltage of the LDO circuit. If the loop of the LDO circuit is unstable, oscillation phenomenon can occur during operation, so that the output voltage is abnormal, and the whole system applying the LDO circuit can be disabled when serious.
Under the condition that the load current in the LDO circuit is large, the load current can reach more than an ampere level, the output pole of the LDO circuit can be changed, the working frequency of the LDO circuit is wide in change range, an oscillation phenomenon occurs, and the output voltage is abnormal. The fixed loop compensation technology provided in the related art can only compensate for the fixed pole in the loop, but cannot effectively compensate for the dynamically variable pole in the loop, and still has the technical problems of oscillation phenomenon, abnormal output voltage and the like when the LDO circuit works.
Disclosure of Invention
The embodiment of the application provides an LDO circuit, which aims to solve the technical problems that in the related art, an oscillation phenomenon occurs when the LDO circuit works, so that output voltage is abnormal and the like.
Correspondingly, the embodiment of the application also provides a dynamic compensation method and electronic equipment, which are used for guaranteeing the implementation and application of the method.
In one aspect, embodiments of the present application provide a low dropout linear regulator LDO circuit comprising a controlled resistor, a load element, and a control unit, the control unit being connected to the controlled resistor and the load element, respectively, wherein,
the control unit is used for determining a first resistance value of a controlled resistor in the LDO circuit and power of a load element in the LDO circuit based on a load current value of the LDO circuit; wherein, the first resistance value is inversely related to the load current value in the LDO circuit;
the control unit is further used for determining a first frequency corresponding to the compensation zero point in the LDO circuit based on the first resistance value;
the control unit is also used for compensating a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency.
In another aspect, an embodiment of the present application provides a circuit compensation method, including:
Determining a first resistance of a controlled resistor in the LDO circuit and a power of a load element in the LDO circuit based on a load current value of the low dropout linear regulator LDO circuit; wherein the first resistance is inversely related to a load current value in the LDO circuit;
determining a first frequency corresponding to a compensation zero point in the LDO circuit based on the first resistance value;
and compensating a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency.
In another aspect, an embodiment of the present application provides an electronic device, including: the LDO circuit provides input voltage for the electronic element.
In the embodiment of the application, the first resistance value of the controlled resistor is in negative correlation with the load current value in the LDO circuit, so that the change rate of the controlled resistor and the load element along with the load current value is consistent, and the phenomenon that the controlled resistor and the load element generate temperature drift along with the change of the circuit temperature due to the fact that the change rate of the controlled resistor and the load element along with the load current value is inconsistent is avoided, and the stability of the LDO circuit is affected. The power of the load element which changes based on the change of the load current value is combined, the power corresponding to the output pole generated based on the load element is compensated based on the frequency corresponding to the compensation zero point generated by the controlled resistor, the compensation zero point which dynamically changes along with the frequency of the output pole can be generated in the LDO circuit no matter what the power of the load element is, the frequency of the output pole is counteracted through the frequency of the compensation zero point, the effective dynamic compensation of the frequency of the output pole is realized, the stable output voltage is output, and the oscillation of the LDO circuit is avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a circuit diagram of an LDO provided by an embodiment of the present application;
FIG. 2-1 illustrates a frequency compensation relationship diagram provided by an embodiment of the present application;
FIG. 2-2 illustrates another frequency compensation relationship provided by embodiments of the present application;
FIG. 3 shows a controlled resistance generation circuit diagram in an LDO circuit provided by an embodiment of the present application;
FIG. 4 illustrates another LDO circuit provided by an embodiment of the present application;
fig. 5 shows a flow chart of a dynamic compensation method according to an embodiment of the present application;
fig. 6 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The embodiment of the application provides an LDO circuit, which is used for improving the stability of the output voltage of the LDO circuit and solving the technical problems that an oscillation phenomenon, abnormal output voltage and the like occur when the LDO circuit works.
As shown in fig. 1, the LDO circuit 10 includes a controlled resistor 11, a load element 12, and a control unit 13, the control unit 13 being connected to the controlled resistor 11 and the load element 12,
wherein the control unit 13 is configured to: determining a first resistance value of a controlled resistor 11 in the LDO circuit 10 and a power of a load element 12 in the LDO circuit 10 based on a load current value of the LDO circuit 10; wherein the first resistance is inversely related to the load current value in the LDO circuit 10;
the control unit 13 is also adapted to: determining a first frequency corresponding to a compensation zero in the LDO circuit 10 based on the first resistance value;
the control unit 13 is also adapted to: based on the power of the load element 12 and the first frequency, a second frequency corresponding to an output pole in the LDO circuit 10 is compensated to a target frequency.
In one possible implementation, the power of the load element may be determined based on the parameter value of the load element and the load current value. For example, when the load element is a load resistor, the power of the load element is the power of the load resistor, and the power of the load resistor can be calculated by multiplying the resistance value of the load resistor by the square of the load current value.
The LDO circuit may be in a light load state or in a heavy load/full load state. In the embodiment of the present application, the symbol "/" may indicate that the former and the latter are in an "or" relationship, or may indicate that the former and the latter are in an "and" relationship. The LDO circuit is in a light load state, which may mean that the power of a load element in the LDO circuit is low or the impedance corresponding to the load element is high. The LDO circuit is in a heavy load state/a full load state, which may refer to a higher power of a load element or a lower impedance corresponding to the load element in the LDO circuit, and the full load state refers to a maximum load state that the LDO circuit can carry. When the LDO circuit is in a light load state, the output pole point of the LDO circuit is in low frequency (namely, the frequency of the output pole point of the LDO circuit is lower, and the working frequency of the LDO circuit is lower) and becomes a main pole point; when the LDO circuit is in a heavy load state/full load state (in the lower case, the output pole point of the LDO circuit appears at an intermediate frequency or a high frequency (i.e., the frequency of the output pole of the LDO circuit is higher, and the operating frequency of the LDO circuit becomes higher), the LDO circuit becomes a non-dominant pole.
If the LDO circuit is in a light load state, another compensation frequency which occurs in high frequency is generated, and if the LDO circuit is in a heavy load state, another compensation frequency which occurs in low frequency is generated, the output pole in the LDO circuit can be effectively compensated, so that the LDO circuit can work under stable frequency.
Based on this, in the embodiment of the application, by generating a zero (which may also be referred to as a compensation zero, a tracking zero, and a dynamic zero) dynamically changing with the frequency of the output pole in the LDO circuit, the frequency change of the output pole is tracked, so that the frequency dynamic compensation of the output pole can be realized, and the LDO circuit can work at a stable frequency no matter in which state the LDO circuit is, thereby realizing the effective compensation of the LDO circuit.
The output pole in the LDO circuit is associated with a load capacitance, and the load element in the LDO circuit comprises a load resistor R connected in parallel with each other L And a load capacitance C L For example, the output pole P of the LDO circuit POW Can be expressed as
Figure BDA0004121180230000041
The compensation zero in the LDO circuit is also associated with a capacitance, which is typically fixed in value and does not change with changes in current in the LDO circuit. In the embodiment of the application, the dynamic compensation zero point can be generated by dynamically controlling the resistance value of the controlled resistor and combining the dynamic controlled resistor and the capacitor with fixed capacitance value, namely
Figure BDA0004121180230000051
In this case, since the capacitance required for generating the compensation zero is set to compensate the frequency of the output pole, it can be considered as "controlled", and in this embodiment, the capacitance can be also referred to as a controlled capacitance or a compensation capacitance.
Output pole P combined with LDO circuit POW The frequency compensation relation diagrams as shown in figures 2-1 and 2-2 can be obtained under the variation conditions of different states, namely, no matter in which state the output pole is, only the zero Z is compensated C Frequency and output pole P of (2) POW The frequencies of (2) can be as close as possible, so that the zero Z can be compensated C Frequency versus output pole P of (2) POW And (3) frequency offset, and oscillation of the LDO circuit is avoided. Specifically:
as shown in FIG. 2-1, if the LDO circuit is in a light load state, the compensation zero Z of the LDO circuit C At higher frequencies, i.e.
Figure BDA0004121180230000052
Can be applied to the lower frequency P of the output pole POW Counteracting is carried out, so that the frequency oscillation range of the LDO circuit is the lowest, and the LDO circuit is effectively compensated; as shown in FIG. 2-2, when the LDO circuit is in a full load state, the compensation zero Z of the LDO circuit is as follows C At lower frequencies, i.e. +.>
Figure BDA0004121180230000053
Can be applied to the higher frequency P of the output pole POW And the offset is carried out, so that the frequency oscillation range of the LDO circuit is the lowest, and the LDO circuit is effectively compensated.
Combining the above pass compensation zero Z C Frequency versus output pole P of (2) POW If the zero point Z is compensated for in such a way that the frequencies of (a) cancel C And output pole P POW The frequencies corresponding to the two should be the same. I.e. at a controlled resistance R Z And a controlled capacitance C Z The compensation of the frequency of the output pole can be achieved based on the frequency of the compensation zero in the LDO circuit when the following conditions are met:
Figure BDA0004121180230000054
by deforming this formula (1), the following formula (2) can be obtained:
Figure BDA0004121180230000055
as described above, the capacitance value in the circuit is usually fixed, and when the load current changes, the temperature may be affected, so that a temperature drift is generated, the resistance value of the resistor is affected, and the rate of change of the resistance value of different resistors with temperature may be different. I.e. controlled capacitance C Z And a load capacitance C L Is a fixed value, the load resistance R L Resistance value and controlled resistance R of (2) Z Will vary with the current in the circuit. Due to the load resistance R L Resistance value of (2) and load current i out In negative correlation, therefore, in the present embodiment, also with the load current i by controlling the controlled resistance out In negative correlation, the load resistance R can be controlled L And a controlled resistance R Z And the second frequency compensation of the output pole in the LDO circuit is realized.
In the embodiment of the application, the first resistance value of the controlled resistor is in negative correlation with the load current value in the LDO circuit, so that the change rate of the controlled resistor and the load element along with the load current value is consistent, and the phenomenon that the controlled resistor and the load element generate temperature drift along with the change of the circuit temperature due to the fact that the change rate of the controlled resistor and the load element along with the load current value is inconsistent is avoided, and the stability of the LDO circuit is affected. The power of the load element which changes based on the change of the load current value is combined, the power corresponding to the output pole generated based on the load element is compensated based on the frequency corresponding to the compensation zero point generated by the controlled resistor, the compensation zero point which dynamically changes along with the frequency of the output pole can be generated in the LDO circuit no matter what the power of the load element is, the frequency of the output pole is counteracted through the frequency of the compensation zero point, the effective dynamic compensation of the frequency of the output pole is realized, the stable output voltage is output, and the oscillation of the LDO circuit is avoided.
In one possible implementation, the specific compensation parameters may be determined by:
the compensating the second frequency corresponding to the output pole in the LDO circuit to the target frequency may include:
the target frequency is smaller than or equal to the first frequency under the condition that the power of the load element is in a first preset power range;
the target frequency is greater than or equal to the second frequency under the condition that the power of the load element is in a second preset power range;
the minimum value of the first preset power range is larger than the maximum value of the second preset power range.
As described above, the power of the load element is related to the load current, and the load current varies widely during practical application, for example, the load current may be any current value from 100uA to 2.4A.
In the practical application process, the boundary value, the first frequency value and the target frequency value in the first preset power range and the second preset power range can be determined based on the actual change range of the load current in the LDO circuit and the specific parameters of the load element, which is not limited in the embodiment of the present application.
By controlling the frequency corresponding to the compensation zero to be slightly larger than the frequency corresponding to the output pole in the LDO circuit when the power of the load element is in the first preset power range, i.e. the power of the load element is lower
Figure BDA0004121180230000071
So that the compensated target frequency of the output pole is lower than the first frequency of the compensation zero point, the lower frequency P of the output pole can be calculated POW And (5) performing offset. By controlling the frequency corresponding to the compensation zero to be slightly smaller than the frequency corresponding to the output pole, i.e. & lt & gt, when the power of the load element in the LDO circuit is in the second preset power range, i.e. when the power of the load element is higher>
Figure BDA0004121180230000072
So that the compensated target frequency of the output pole is higher than the first frequency of the compensation zero point, the higher frequency P of the output pole can be calculated POW And (5) performing offset. The lowest frequency oscillation range of the LDO circuit can be realized as far as possible no matter what state the power of the load element of the LDO circuit is, and the LDO circuit is effectively compensated, so that the output voltage of the LDO circuit is controlled to be stable.
In this embodiment of the present application, considering that in the actual application process, the frequency corresponding to the compensation zero may not be controlled to be completely equal to the frequency corresponding to the output pole, therefore, based on different situations, it may be ensured that the frequency corresponding to the compensation zero is as close as possible to the frequency corresponding to the output pole, i.e. the frequency corresponding to the compensation zero is controlled to be slightly greater than the frequency corresponding to the output pole, or the frequency corresponding to the compensation zero is controlled to be slightly less than the frequency corresponding to the output pole.
In one possible implementation, the resistance of the controlled resistor may be inversely related to the load current value, in particular by.
Optionally, the LDO circuit may further comprise a load current detection tube and an output power tube,
the source electrode of the load current detection tube and the source electrode of the output power tube are connected with the load element, the grid electrode of the load current detection tube is connected with the grid electrode of the output power tube, and the drain electrode of the load current detection tube is connected with the controlled resistor;
the ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube is a preset ratio relation.
In this implementation, both the load current detection tube and the output power tube may be NMOS (N-Metal-Oxide-Semiconductor) tubes.
In the technical field, the width-to-length ratio of a MOS (Metal-Oxide-Semiconductor) transistor is the ratio of the width to the length of a conductive channel of the MOS transistor. Based on a drain current calculation formula (namely an NMOS saturation current calculation formula) of the MOS transistor,
Figure BDA0004121180230000073
Figure BDA0004121180230000074
it can be known that the width-to-length ratio of the MOS transistor is proportional to the drain current, i.e., the larger the width-to-length ratio of the MOS transistor, the larger the corresponding drain current, in the case where parameters other than the width-to-length ratio are certain. Wherein, in the drain current calculation formula of the MOS tube, W is the width (width) of the conducting channel of the MOS tube, L is the length (length) of the conducting channel of the MOS tube, u n Is the electron mobility of the MOS tube, C ox Is the thickness of the gate oxide layer of the MOS tube, V GS Is the gate-source voltage of the MOS tube, V THN To preset threshold value, V THN May be constant.
In this embodiment of the present application, the gate of the load current detection tube and the gate of the output power tube may be connected to a certain reference power supply, for example, when an amplifier is present in the LDO circuit, the gate of the load current detection tube and the gate of the output power tube may be connected to the output end of the amplifier, so as to better adjust the output voltage based on the operational amplifier gain.
In the embodiment of the application, the source electrode of the load current detection tube and the source electrode of the output power tube are connected with the load element, the grid electrode of the load current detection tube is connected with the grid electrode of the output power tube, and the grid source voltage of the load current detection tube can be controlled to be equal to the grid source voltage of the output power tube, so that the ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube and the drain current calculation mode of the MOS tube can be combined, the drain current of the load current detection tube can be determined, and the first resistance value of the controlled resistor can be further determined accurately through the connection relation between the drain electrode of the load current detection tube and the controlled resistor.
Specifically, the first resistance value may be determined by:
optionally, the control unit may be specifically configured to, when determining the first resistance value of the controlled resistor in the LDO circuit based on the load current value in the LDO circuit:
obtaining a first current value based on a relation between a load current value and a preset ratio;
a first resistance value is determined based on the first current value.
Assuming that the ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube is a preset ratio relation of 1: n, and through M C1 Representing a load current sense tube, through M POW Representing the output power tube, the aspect ratio of the two can be expressed as
Figure BDA0004121180230000081
The load current detection tube M can be obtained based on the drain current calculation formula of the MOS tube C1 I is the first current value (i.e., the drain current value) sense And output power tube M POW Drain current value i of (2) out The ratio between them is 1: n, i.e. the first current value is: />
Figure BDA0004121180230000082
Therefore, in the process of changing the load current value, the first current value of the load current detection tube can be determined by combining the ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube and the drain current calculation mode of the MOS tube, and the first resistance value of the controlled resistor is accurately determined based on the first current value through the connection relation between the drain electrode of the load current detection tube and the controlled resistor.
Optionally, the LDO circuit may further include a voltage conversion unit, where a drain of the load current detection tube is connected to the controlled resistor through the voltage conversion unit;
the control unit may be specifically configured to, when determining the first resistance value based on the first current value:
performing voltage conversion operation on the first current value through a voltage conversion unit to obtain a first voltage value of the controlled resistor;
a first resistance value is determined based on the first voltage value.
In the implementation manner, the first voltage value of the controlled resistor is determined by performing voltage conversion operation on the first current value detected by the load current detection tube, so that the first resistance value of the controlled resistor is determined conveniently based on the first voltage value and the parameter value of the controlled resistor.
Alternatively, the voltage converting unit may comprise a first current mirror, a second current mirror and a third current mirror,
the drain electrode of the first current mirror tube is connected with the drain electrode of the load current detection tube;
the grid electrode of the second current mirror tube is connected with the grid electrode of the first current mirror tube, and the source electrode of the second current mirror tube is connected with the source electrode of the first current mirror tube;
and the source electrode of the third current mirror tube is connected with one end of the controlled resistor, and the grid electrode of the third current mirror tube is connected with the other end of the controlled resistor.
In this implementation, the first current mirror tube and the second current mirror tube may be PMOS tubes, and the third current mirror tube may be NMOS tubes.
The grid electrode of the second current mirror tube and the grid electrode of the first current mirror tube can be connected between the drain electrode of the first current mirror tube and the drain electrode of the load current detection tube, and the source electrode of the second current mirror tube and the source electrode of the first current mirror tube can be connected to the power end of the LDO circuit so as to work under the voltage provided by the power end.
By connecting the drain of the first current mirror tube and the drain of the load current detection tube, the drain currents of the first current mirror tube and the load current detection tube can be made equal. The grid electrode of the second current mirror tube is connected with the grid electrode of the first current mirror tube, and the source electrode of the second current mirror tube is connected with the source electrode of the first current mirror tube, so that the grid source voltages of the second current mirror tube and the first current mirror tube are equal. And then the source electrode of the third current mirror tube is connected with one end of the controlled resistor, and the grid electrode of the third current mirror tube is connected with the other end of the controlled resistor, so that the first voltage value of the controlled resistor is equal to the grid source voltage of the third current mirror tube.
Specifically, the specific procedure of performing the voltage conversion operation on the first current value by the voltage conversion unit may be as follows:
optionally, when the control unit performs voltage conversion operation on the first current value through the voltage conversion unit to obtain the first voltage value of the controlled resistor, the control unit may be specifically configured to:
determining, by the first current mirror, a second voltage value based on the first current value;
determining a second current value based on the second voltage value through a second current mirror;
determining a third voltage value based on the second current value through a third current mirror;
the first voltage value is determined based on the third voltage value.
In this implementation manner, the control unit may determine the drain current value of the first current mirror tube, that is, the drain current value of the load current detection tube, that is, the first current value, based on the connection relationship between the first current mirror tube and the load current detection tube. And the drain current calculation mode of the MOS tube is reversely deduced,
Figure BDA0004121180230000101
Figure BDA0004121180230000102
and determining the gate-source voltage of the first current mirror tube, namely a second voltage value, based on the first current mirror tube and the formula. And further determining the drain current of the second current mirror tube, namely a second current value, by the second current mirror tube based on the second voltage value and the drain current calculation mode of the MOS tube. And determining a drain current value of the third current mirror tube, namely a drain current value of the second current mirror tube, namely a second current value, through a connection relation between the third current mirror tube and the second current mirror tube. And further performing back-pushing by the third current mirror tube based on the second current value and the drain current calculation mode of the MOS tube, and determining the gate-source voltage of the third current mirror tube, namely a third voltage value. Further, based on the connection relation between the third current mirror tube and the controlled resistor, the first voltage value of the controlled resistor, namely the gate-source voltage of the third current mirror tube, namely the third voltage value is determined.
In order to further improve the stability of the LDO circuit, the embodiments of the present application further provide the following optional implementations:
optionally, the LDO circuit may further include a controlled MOS transistor of a metal-oxide-semiconductor field effect transistor and an amplifier, the controlled MOS transistor is connected to the first output terminal of the amplifier through a controlled capacitor, and the controlled resistor is an on-resistance of the controlled MOS transistor.
In this implementation, the controlled MOS transistor may be implemented by an NMOS transistor.
The controlled MOS tube realized based on the NMOS tube is controlled to be connected to the first output end of the amplifier through the controlled capacitor, so that direct current passing through the controlled MOS tube cannot flow into the first output end of the amplifier, the controlled MOS tube is always in a deep linear region, the controlled resistor of the LDO circuit can be generated through the on-resistance of the controlled MOS tube in the deep linear region, the occurrence of unstable LDO circuit caused by temperature drift is better reduced, and the controlled capacitor can be enabled to continuously work under the alternating current voltage output by the first output end of the amplifier.
Optionally, a source electrode of the third current mirror tube is connected with one end of the controlled resistor, and a gate electrode of the third current mirror tube is connected with the other end of the controlled resistor, including:
The source electrode of the third current mirror tube is connected with the source electrode of the controlled MOS tube, and the grid electrode of the third current mirror tube is connected with the grid electrode of the controlled MOS tube;
based on the first voltage value, determining the first resistance value may include:
the first resistance value is determined based on the first voltage value and the drain current determination mode.
The grid electrode of the third current mirror tube is connected with the grid electrode of the controlled MOS tube through controlling the source electrode of the third current mirror tube to be connected with the source electrode of the controlled MOS tube, so that the grid source voltages of the third current mirror tube and the controlled MOS tube are consistent, namely, the connection mode of the controlled MOS tube and the third current mirror tube can determine that the grid source voltage of the controlled MOS tube (namely, the first voltage value of the controlled resistor) is equal to the grid source voltage of the third current mirror tube, and the first voltage value of the controlled resistor is better determined.
And further, based on the first voltage value and the determination mode of the drain current, reversely pushing to obtain the resistance value of the on-resistance of the controlled MOS tube, namely the first resistance value of the controlled resistance.
Based on the description of the LDO circuit, an embodiment of the present application provides a controlled resistance generating circuit as shown in fig. 3, in which the output power tube M POW Load current detection tube M C1 Third current mirror tube M C4 Controlled MOS transistor M Z Are all realized based on NMOS tubes, and the process deviation generated in the production process can be reduced as much as possible for the controlled MOS tube M Z The on-resistance r of (2) ON,MZ I.e. controlled resistance R Z Is a function of (a) and (b). First current mirror tube M C2 And a second current mirror tube M C3 Are all realized based on PMOS tubes, and the controlled resistor R can be controlled by setting parameters of each MOS tube (namely, all elements realized based on NMOS and elements realized based on PMOS tubes related by the circuit are collectively called as elements realized based on PMOS tubes) Z Thereby better compensating for the output pole in the LDO circuit.
The process of generating the controlled resistance will be described in detail below by taking the controlled resistance generating circuit shown in fig. 3 as an example.
Load current detection tube M C1 Gate of (c) and output power tube M POW Are connected to the second output terminal V of the amplifier EA2 On, load current detecting tube M C1 Source and output power tube M of (2) POW Are all connected to the output voltage terminal V OUT I.e. connected to the load element, the load current sense tube M C1 Gate-source voltage of (2)
Figure BDA0004121180230000121
And output power tube M POW Gate-source voltage of (2)
Figure BDA0004121180230000122
Are all identical, i.e
Figure BDA0004121180230000123
Due to the load current sense tube M C1 Aspect ratio and output power tube M POW The ratio relationship between the width to length ratio of (2) is 1: n, i.e
Figure BDA0004121180230000124
The load current detection tube M can be obtained based on the drain current calculation formula of the MOS tube C1 Drain current value i of (2) sense And output power tube M POW Drain current value i of (2) out The ratio between them is 1: n, i.e
Figure BDA0004121180230000125
First current mirror tube M C2 Drain electrode of (d) and load current detection tube M C1 Is connected with the drain electrode of the first current mirror tube M C2 Drain electrode of (d) and load current detection tube M C1 The drains of the components in the same branch are connected with the same current, so that the first current mirror tube M C2 Drain current i of (2) C2 And a load current detection tube M C1 Drain current i of (2) sense Equal, i.e. i C2 ＝i sense 。
Based on a first current mirror tube M C2 Drain current i of (2) C2 And the drain current calculation formula of the MOS tube, and reversely pushing to obtain,
Figure BDA0004121180230000126
a first current mirror tube M can be obtained C2 Gate-source voltage +.>
Figure BDA0004121180230000127
I.e. V Z1 。
Second current mirror tube M C3 Source of (c) and first current mirror tube M C2 Are all connected to the power supply terminal V DD Second current mirror tube M C3 Gate of (c) and first current mirror tube M C2 Are all short-circuited to V Z1 A second current mirror tube M can be obtained C3 Gate-source voltage of (2)
Figure BDA0004121180230000128
And a first current mirror tube M C2 Gate-source voltage +.>
Figure BDA0004121180230000129
Equal.
Based on a second current mirror tube M C3 Gate-source voltage of (2)
Figure BDA00041211802300001210
And a drain current calculation formula of the MOS tube to obtain a second current mirror tube M C3 Drain current i of (2) C3 And can further determine the second current mirror tube M C3 Gate-source voltage +.>
Figure BDA0004121180230000131
First current mirror tube M C2 Gate-source voltage +.>
Figure BDA0004121180230000132
Load current detection tube M C1 Gate-source voltage +.>
Figure BDA0004121180230000133
Are all equal, and further, i can be obtained C3 ＝i C2 ＝i sense 。
Third current mirror tube M C4 Drain electrode of (d) and second current mirror tube M C3 Drain connection of (a) third current mirror M C4 Drain electrode of (d) and second current mirror tube M C3 The drains of the components in the same branch are connected with the same current, the third current mirror tube M C4 Drain current i of (2) C4 And a second current mirror tube M C3 Drain current i of (2) C3 Equality, further, i can be obtained C4 ＝i C3 ＝i C2 ＝i sense 。
Third current mirror tube M C4 Is short-circuited to ground V SS The M can be obtained by back-pushing based on a drain current calculation formula of the MOS tube C4 Gate-source voltage of (2)
Figure BDA0004121180230000134
Figure BDA0004121180230000135
Controlled MOS tube M Z Gate of (c) and third current mirror tube M C4 Is short-circuited to V Z2 Controlled MOS tube M Z Source of (d) and third current mirror tube M C4 The source electrodes of the MOS transistor M are short-circuited to the ground Z And a third current mirror tube M C4 The gate-source voltages of (a) are the same, i.e
Figure BDA0004121180230000136
As described above, due to the controlled MOS transistor M Z Through a controlled capacitance G Z Connected to the first end V of the amplifier EA1 Resulting in direct current not passing through the controlled MOS tube M Z So that the MOS tube M is controlled Z Always working in the deep linear region, so the controlled MOS tube MZ can be equivalent to a controlled resistor R Z On-resistance r for the controlled MOS transistor operating in deep linear region ON，MZ I.e. R Z ＝r ON，MZ The on-resistance r ON，MZ The determination may be made by:
Figure BDA0004121180230000141
based on the formula, the controlled resistance R can be obtained Z Resistance value of (2) and load current i out Is inversely related and due to the load resistance R L The resistance of (2) is also equal to the load current i out Inversely proportional, i.e. controlled resistance R is achieved Z And a load resistor R L The output pole of the LDO circuit can be compensated by changing the output pole along with the load current, and the change rates of the output pole and the load current are consistent.
In order to further improve the stability of the LDO circuit, the present application further provides the following optional implementation manners:
the LDO circuit may further include a source follower;
the grid electrode of the source electrode follower is connected with the first output end of the amplifier;
the source electrode of the source electrode follower is respectively connected with the second output end of the amplifier, the grid electrode of the load current detection tube and the grid electrode of the output power tube.
In this implementation, the source follower may be implemented based on PMOS transistors.
The LDO circuit as shown in fig. 4 includes an error amplifier EA, a PMOS source follower, a pole-zero tracking network, an NMOS power transistor, and a load element. The load element can be realized by a load resistor and a load capacitor. The isolation between the pole-zero tracking network and the NMOS power tube can be established through a PMOS source follower, namely, the pole-zero tracking network and the grid electrode of the PMOS source follower are connected to the first output end of the error amplifier EA, the source electrode of the PMOS source follower and the grid electrode of the NMOS power tube are connected to the second output end of the error amplifier EA, and the drain electrode of the PMOS of the source follower is grounded. Wherein V is EA2 ＝V EA1 -V GS，PMOS 。
In the LDO circuit, the frequency of the output pole of the circuit can be compensated by the frequency of the compensation zero generated by the pole-zero tracking network. The pole-zero tracking network comprises a controlled resistor R Z And a controlled capacitance C Z Is realized by a small signal pair ground circuit, wherein, the resistance R is controlled Z I.e. by the controlled resistance generating circuit of the output of fig. 3. The error amplifier EA can form single-gain negative feedback, and V can be obtained by virtual short and virtual break of the operational amplifier OUT ＝V REF ＝V EA1 。
In the LDO circuit, the isolation between the pole-zero tracking network and the NMOS power tube is established through the source follower, so that the noise in the circuit can be further reduced, the stability of the circuit is improved, and meanwhile, the gain of the operational amplifier is ensured.
In the LDO circuit, there is only one current path, a load current detecting tube and a current source I S The current of the LDO circuit directly flows to the ground from another channel, and the newly added dynamic zero compensation circuit can not influence the stability of the whole LDO circuit, but also improves the stability of the LDO circuit.
The LDO circuit can realize the load current i under the action of a dynamic compensation network out Under the condition of being in the range of 100uA to 2.4A, the phase margin in stb simulation is kept above 56 degrees, the gain is kept above 40dB, the low-frequency PSR (power supply rejection, power supply inhibition) performance is improved, and the low-frequency PSR can be kept below-58 dB.
Based on the same principle as the LDO circuit provided by the embodiment of the application, the embodiment of the application also provides a dynamic compensation method. As shown in fig. 5, the method includes:
step S510: determining a first resistance of a controlled resistor in the LDO circuit and a power of a load element in the LDO circuit based on a load current value of the low dropout linear regulator LDO circuit; wherein the first resistance is inversely related to a load current value in the LDO circuit;
step S520: determining a first frequency corresponding to a compensation zero point in the LDO circuit based on the first resistance value;
step S530: and compensating a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency.
In the embodiment of the application, the first resistance value of the controlled resistor is in negative correlation with the load current value in the LDO circuit, so that the change rate of the controlled resistor and the load element along with the load current value is consistent, and the phenomenon that the controlled resistor and the load element generate temperature drift along with the change of the circuit temperature due to the fact that the change rate of the controlled resistor and the load element along with the load current value is inconsistent is avoided, and the stability of the LDO circuit is affected. The power of the load element which changes based on the change of the load current value is combined, the power corresponding to the output pole generated based on the load element is compensated based on the frequency corresponding to the compensation zero point generated by the controlled resistor, the compensation zero point which dynamically changes along with the frequency of the output pole can be generated in the LDO circuit no matter what the power of the load element is, the frequency of the output pole is counteracted through the frequency of the compensation zero point, the effective dynamic compensation of the frequency of the output pole is realized, the stable output voltage is output, and the oscillation of the LDO circuit is avoided.
Optionally, determining the first resistance of the controlled resistor in the LDO circuit based on the load current value of the LDO circuit may include:
obtaining a first current value based on a relation between a load current value and a preset ratio;
a first resistance value is determined based on the first current value.
Optionally, the LDO circuit may further comprise a load current detection tube and an output power tube,
the source electrode of the load current detection tube is connected with the source electrode of the output power tube, the grid electrode of the load current detection tube is connected with the grid electrode of the output power tube, and the drain electrode of the load current detection tube is connected with the controlled resistor;
the preset ratio relation is a ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube.
Optionally, determining the first resistance value based on the first current value may include:
performing voltage conversion operation on the first current value to obtain a first voltage value of the controlled resistor;
a first resistance value is determined based on the first voltage value.
Optionally, performing a voltage conversion operation on the first current value to obtain a first voltage value of the controlled resistor may include:
determining a second voltage value of the first current mirror based on the first current value;
determining a second current value of the second current mirror based on the second voltage value;
Determining a third voltage value of a third current mirror based on the second current value;
the first voltage value is determined based on the third voltage value.
Optionally, the drain electrode of the first current mirror tube is connected with the drain electrode of the load current detection tube;
the grid electrode of the second current mirror tube is connected with the grid electrode of the first current mirror tube, and the source electrode of the second current mirror tube is connected with the source electrode of the first current mirror tube;
and the source electrode of the third current mirror tube is connected with one end of the controlled resistor, and the grid electrode of the third current mirror tube is connected with the other end of the controlled resistor.
Optionally, the LDO circuit may further include a controlled MOS transistor of a metal-oxide-semiconductor field effect transistor and an amplifier, the controlled MOS transistor is connected to a first output terminal of the amplifier through a controlled capacitor, and the controlled resistor is an on-resistance of the controlled MOS transistor;
the source of the third current mirror tube is connected with one end of the controlled resistor, the grid of the third current mirror tube is connected with the other end of the controlled resistor, and the third current mirror tube comprises:
the source electrode of the third current mirror tube is connected with the source electrode of the controlled MOS tube, and the grid electrode of the third current mirror tube is connected with the grid electrode of the controlled MOS tube.
Optionally, determining the first voltage value based on the third voltage value may include:
determining the third voltage value as the first voltage value;
Determining a first resistance value based on the first voltage value, comprising:
the first resistance value is determined based on the first voltage value and the drain current determination mode.
Optionally, the LDO circuit may further include a source follower;
the grid electrode of the source electrode follower is connected with the first output end of the amplifier;
the source electrode of the source electrode follower is respectively connected with the second output end of the amplifier, the grid electrode of the load current detection tube and the grid electrode of the output power tube.
Optionally, compensating the second frequency corresponding to the output pole in the LDO circuit to the target frequency may include:
the target frequency is smaller than or equal to the first frequency under the condition that the power of the load element is in a first preset power range;
the target frequency is greater than or equal to the first frequency when the power of the load element is in a second preset power range;
the minimum value of the first preset power range is larger than the maximum value of the second preset power range.
The principle of the effect achieved by the connection relationship between each step in the dynamic compensation method and each element in the LDO circuit in the embodiment of the present application corresponds, and the detailed description of each step in the dynamic compensation method may be referred to the description in the LDO circuit shown in the foregoing, which is not repeated here.
Based on the same principle as the LDO circuit provided in the embodiment of the present application, as shown in fig. 6, an electronic device (e.g. a server) is further provided in the embodiment of the present application, where the electronic device 60 may include: an electronic component 61 and the LDO circuit 62, wherein the LDO circuit 61 provides an input voltage to the electronic component 62.
The electronic component is any electronic component in the electronic device, which is not limited in the embodiment of the present application.
In the embodiment of the application, the first resistance value of the controlled resistor is in negative correlation with the load current value in the LDO circuit, so that the change rate of the controlled resistor and the load element along with the load current value is consistent, and the phenomenon that the controlled resistor and the load element generate temperature drift along with the change of the circuit temperature due to the fact that the change rate of the controlled resistor and the load element along with the load current value is inconsistent is avoided, and the stability of the LDO circuit is affected. The power of the load element which changes based on the change of the load current value is combined, the power corresponding to the output pole generated based on the load element is compensated based on the frequency corresponding to the compensation zero point generated by the controlled resistor, the compensation zero point which dynamically changes along with the frequency of the output pole can be generated in the LDO circuit no matter what the power of the load element is, the frequency of the output pole is counteracted through the frequency of the compensation zero point, the effective dynamic compensation of the frequency of the output pole is realized, stable voltage is output, and stable input voltage can be provided for the electronic element, so that oscillation of the LDO circuit is avoided.
The terms "first," "second," and the like in the claims and specification and drawings of this application are used for distinguishing between different objects and not for describing a particular sequential order.
Furthermore, as used herein, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless expressly stated otherwise. The terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or electronic device that comprises a list of steps or elements is not limited to the list of steps or elements but may, alternatively, include other steps or elements not listed or inherent to such process, method, article, or electronic device.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments. The term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The foregoing disclosure is only illustrative of the preferred embodiments of the present application and is not to be construed as limiting the scope of the claims, and therefore, equivalent variations in terms of the claims are intended to be included herein.

Claims (21)

1. The LDO circuit of the low dropout linear regulator is characterized by comprising a controlled resistor, a load element and a control unit, wherein the control unit is respectively connected with the controlled resistor and the load element,
the control unit is used for determining a first resistance value of a controlled resistor in the LDO circuit and power of a load element in the LDO circuit based on a load current value of the LDO circuit; wherein the first resistance is inversely related to a load current value in the LDO circuit;
The control unit is further used for determining a first frequency corresponding to a compensation zero point in the LDO circuit based on the first resistance value;
the control unit is further configured to compensate a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency.
2. The LDO circuit of claim 1, further comprising a load current sense tube and an output power tube,
the source electrode of the load current detection tube and the source electrode of the output power tube are connected with the load element, the grid electrode of the load current detection tube is connected with the grid electrode of the output power tube, and the drain electrode of the load current detection tube is connected with the controlled resistor;
the ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube is a preset ratio relation.
3. The LDO circuit of claim 2, wherein the control unit, when determining the first resistance value of the controlled resistance in the LDO circuit based on the load current value of the LDO circuit, is to:
obtaining a first current value based on the relation between the load current value and the preset ratio;
The first resistance value is determined based on the first current value.
4. The LDO circuit of claim 3, further comprising a voltage conversion unit through which a drain of the load current detection tube is connected to the controlled resistor;
the control unit, when determining the first resistance value based on the first current value, is configured to:
performing voltage conversion operation on the first current value through the voltage conversion unit to obtain a first voltage value of the controlled resistor;
the first resistance value is determined based on the first voltage value.
5. The LDO circuit of claim 4, wherein the voltage conversion unit comprises a first current mirror, a second current mirror, and a third current mirror,
the drain electrode of the first current mirror tube is connected with the drain electrode of the load current detection tube;
the grid electrode of the second current mirror tube is connected with the grid electrode of the first current mirror tube, and the source electrode of the second current mirror tube is connected with the source electrode of the first current mirror tube;
and the source electrode of the third current mirror tube is connected with one end of the controlled resistor, and the grid electrode of the third current mirror tube is connected with the controlled resistor.
6. The LDO circuit of claim 5, wherein the control unit is configured to, when performing a voltage conversion operation on the first current value by the voltage conversion unit, obtain a first voltage value of the controlled resistor:
determining, by the first current mirror, a second voltage value based on the first current value;
determining a second current value based on the second voltage value through the second current mirror;
determining a third voltage value based on the second current value through the third current mirror;
the first voltage value is determined based on the third voltage value.
7. The LDO circuit of claim 5 or 6, further comprising a metal-oxide-semiconductor field effect transistor controlled MOS transistor and an amplifier, the controlled MOS transistor connected to a first output of the amplifier through a controlled capacitance, the controlled resistance being an on-resistance of the controlled MOS transistor;
the source electrode of the third current mirror tube is connected with one end of the controlled resistor, the grid electrode of the third current mirror tube is connected with the controlled resistor, and the method comprises the following steps:
the source electrode of the third current mirror tube is connected with the source electrode of the controlled MOS tube, and the grid electrode of the third current mirror tube is connected with the grid electrode of the controlled MOS tube.
8. The LDO circuit of claim 7, wherein,
the determining the first voltage value based on the third voltage value includes:
determining the third voltage value as the first voltage value;
the determining the first resistance value based on the first voltage value includes:
and determining the first resistance value based on the first voltage value and a drain current determination mode.
9. The LDO circuit of claim 7 or 8, further comprising a source follower;
the grid electrode of the source electrode follower is connected with the first output end of the amplifier;
and the source electrode of the source electrode follower is respectively connected with the second output end of the amplifier, the grid electrode of the load current detection tube and the grid electrode of the output power tube.
10. The LDO circuit of claim 1, wherein the compensating the second frequency corresponding to the output pole in the LDO circuit to the target frequency comprises:
the target frequency is less than or equal to the first frequency when the power of the load element is in a first preset power range;
the target frequency is greater than or equal to the first frequency when the power of the load element is in a second preset power range;
Wherein the minimum value of the first preset power range is larger than the maximum value of the second preset power range.
11. A method of dynamic compensation, comprising:
determining a first resistance value of a controlled resistor in a low dropout linear regulator (LDO) circuit and a power of a load element in the LDO circuit based on a load current value of the LDO circuit; wherein the first resistance is inversely related to a load current value in the LDO circuit;
determining a first frequency corresponding to a compensation zero point in the LDO circuit based on the first resistance value;
and compensating a second frequency corresponding to an output pole in the LDO circuit to a target frequency based on the power of the load element and the first frequency.
12. The method of claim 11, wherein the determining a first resistance value of a controlled resistance in the LDO circuit based on a load current value of the LDO circuit comprises:
obtaining a first current value based on the relation between the load current value and a preset ratio;
the first resistance value is determined based on the first current value.
13. The method of claim 12, wherein the LDO circuit further comprises a load current sense tube and an output power tube,
The source electrode of the load current detection tube is connected with the source electrode of the output power tube, the grid electrode of the load current detection tube is connected with the grid electrode of the output power tube, and the drain electrode of the load current detection tube is connected with the controlled resistor;
the preset ratio relation is a ratio relation between the width-to-length ratio of the load current detection tube and the width-to-length ratio of the output power tube.
14. The method according to claim 12 or 13, wherein the determining the first resistance value based on the first current value comprises:
performing voltage conversion operation on the first current value to obtain a first voltage value of the controlled resistor;
the first resistance value is determined based on the first voltage value.
15. The method of claim 14, wherein performing a voltage conversion operation on the first current value to obtain a first voltage value for the controlled resistor comprises:
determining a second voltage value of the first current mirror based on the first current value;
determining a second current value of a second current mirror based on the second voltage value;
determining a third voltage value of a third current mirror based on the second current value;
The first voltage value is determined based on the third voltage value.
16. The method of claim 15, wherein the step of determining the position of the probe is performed,
the drain electrode of the first current mirror tube is connected with the drain electrode of the load current detection tube;
the grid electrode of the second current mirror tube is connected with the grid electrode of the first current mirror tube, and the source electrode of the second current mirror tube is connected with the source electrode of the first current mirror tube;
the third current mirror tube is connected with the controlled resistor.
17. The method of claim 15 or 16, wherein the LDO circuit further comprises a metal-oxide-semiconductor field effect transistor controlled MOS transistor and an amplifier,
the controlled MOS tube is connected to the first output end of the amplifier through a controlled capacitor;
the source electrode of the controlled MOS tube is connected with the source electrode of the third current mirror tube, the grid electrode of the controlled MOS tube is connected with the grid electrode of the third current mirror tube, and the controlled resistor is the on-resistance of the controlled MOS tube.
18. The method of claim 17, wherein the step of determining the position of the probe is performed,
the determining the first voltage value based on the third voltage value includes:
determining the third voltage value as the first voltage value;
The determining the first resistance value based on the first voltage value includes:
and determining the first resistance value based on the first voltage value and a drain current determination mode.
19. The method of claim 17 or 18, wherein the LDO circuit further comprises a source follower;
the grid electrode of the source electrode follower is connected with the first output end of the amplifier;
and the source electrode of the source electrode follower is respectively connected with the second output end of the amplifier, the grid electrode of the load current detection tube and the grid electrode of the output power tube.
20. The method of claim 19, wherein the compensating the second frequency corresponding to the output pole in the LDO circuit to the target frequency comprises:
the target frequency is less than or equal to the first frequency when the power of the load element is in a first preset power range;
the target frequency is greater than or equal to the first frequency when the power of the load element is in a second preset power range;
wherein the minimum value of the first preset power range is larger than the maximum value of the second preset power range.
21. An electronic device, comprising:
An electronic component;
the low dropout linear regulator LDO circuit of any of claims 1 to 10;
the LDO circuit provides an input voltage for the electronic element.
CN202310219621.8A 2023-03-01 2023-03-01 LDO circuit of low dropout linear regulator, dynamic compensation method and electronic equipment Pending CN116069116A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116707467A (en) * 2023-08-04 2023-09-05 核芯互联科技(青岛)有限公司 class-AB structure voltage buffer suitable for large capacitive load

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116707467A (en) * 2023-08-04 2023-09-05 核芯互联科技(青岛)有限公司 class-AB structure voltage buffer suitable for large capacitive load
CN116707467B (en) * 2023-08-04 2023-12-05 核芯互联科技(青岛)有限公司 class-AB structure voltage buffer suitable for large capacitive load

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