CN1159848C - Phase detector - Google Patents

Phase detector Download PDF

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Publication number
CN1159848C
CN1159848C CNB01134475XA CN01134475A CN1159848C CN 1159848 C CN1159848 C CN 1159848C CN B01134475X A CNB01134475X A CN B01134475XA CN 01134475 A CN01134475 A CN 01134475A CN 1159848 C CN1159848 C CN 1159848C
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signal
phase
delay
circuit
time
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CN1359195A (en
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林有为
陈佳欣
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Via Technologies Inc
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Via Technologies Inc
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Abstract

The present invention relates to a phase detector which comprises a phase detector, an inverse phase logic circuit, a delay device, a latching device and an OR logic circuit. The phase detector is used for detecting phases arranged among reference signals and feedback signals and outputting a delay control signal. The phase detector can acquire states among the feedback signals by the reference signals so as to produce detection signals. The inverse phase logic circuit and the delay device can slightly delay the detection signals reversed, and the detection signals are fed in the latching device so as to produce latching signals. The detection signals and the latching signals are fed in the OR logic circuit, and a delay circuit satisfies different requirements for time delay, such as T/4, T/2, T, etc., by the OR logic circuit according to the delay control signal fed in a counter.

Description

Phase detection device
Technical field
The invention belongs to a kind of checkout gear, relate in particular to a kind of phase detection device of delay locked loop.
Background technology
In logical circuit, often need signal delay be exported at design requirement.The design of delay circuit is a lot, utilizes delay locked loop (Delay-Lock Loop DLL), then can exactly input signal be postponed the time of 1/4 cycle, half period or one-period, the different demands when satisfying circuit design.
In accompanying drawing 1, a kind of prior art scheme is disclosed, it has illustrated the phase relation between reference signal and inhibit signal.As shown in Figure 1, reference signal S is the square wave kenel, if delayed 1/4 cycle (being T/4) opportunity of reference signal S appearance, then can form inhibit signal SD.Therefore, inhibit signal SD is identical with the wave mode of reference signal S, and phase place then differs T/4.
In accompanying drawing 2, it discloses the delay locked loop block diagram.Delay locked loop comprises delay circuit 210, phase detectors 220 and counter 230, and its purpose is to postpone the opportunity that reference signal 20 occurs.With Fig. 2 is example, and behind the reference signal 20 feed-in delay circuits 210, delay circuit 210 can determine the length of time of delay according to the count signal 23 by counter 230 feed-ins; That is different count signals 23 can make reference signal 20 reach different carryover effects.For instance, when count signal 23 was 0, the time of delay that delay circuit 210 is produced was the shortest, can cause reference signal 20 the shortest the time with postponing; Gradually the numerical value of count signal 23 is increased, then delay circuit 210 also increases gradually time of delay of being produced, the time delay that makes reference signal 20 also with prolongation.
On the other hand, for meeting design requirement the time of delay that makes reference signal 20, in the adjustment process of time of delay, certainly will need to see through the mechanism of back coupling progressively to being revised time of delay at that time, till delay circuit 210 can produce correct time of delay.On the practice, can earlier count signal 23 be made as 0, borrow the effect of delay circuit 210, can cause the shortest time delay of reference signal 20.Then, with the reference signal 20 after postponing as in the feedback signal 25 feed-in phase detectors 220, and utilize the phase difference of 25 of phase detectors 220 reference signal detection 20 and feedback signals, so, can detect and do not reach design requirement (so time time of delay the shortest) time of delay of learning this moment as yet.Then, phase detectors 220 can in delayed control signal 22 feed-in counters 230, increase the numerical value of count signal 23 according to testing result, and with in these count signal 23 feed-in delay circuits 210, to increase the time of delay of reference signal 20.After increasing time of delay, the reference signal 20 after will postponing once again is as in the feedback signal 25 feed-in phase detectors 220, and utilizes above-mentioned control method, continues adjustment time of delay, till delay circuit 210 can produce correct time of delay.Hence one can see that, and the enforcement that repeats by above-mentioned adjustment work can make reference signal 20 reach correct time delay.
Then, will specify the 100MHz signal delay processing method in 1/4 cycle based on circuit framework shown in Figure 2; That is, desire with above-mentioned signal processing mode, make the 100MHz signal can produce the time delay of 2.5ns.Please refer to Fig. 3, postpone the delay locked loop calcspar of T/4 shown in it.At first, need utilize the reference signal 30 of 200MHz to implement delay correction work.Borrow the effect of inverted logic circuit 310, can with reference signal 30 anti-phase be reference signal 30a and feed-in phase detectors 220, see through the effect of buffer 320, can be feedback signal 35a and feed-in phase detectors 220 with feedback signal 35 bufferings.Then, phase detectors 220 can in delayed control signal 32 feed-in counters 230, to adjust the time of delay of reference signal 30, can produce correct time delay until delay circuit 210 according to the phase difference between reference signal 30a and feedback signal 35a.Therefore these control modes are no longer gone to live in the household of one's in-laws on getting married and are chatted in above describing in detail; Hereinafter, will do further explanation with sequential chart at the relativeness between each signal.
Please refer to Fig. 4, the sequential chart between reference signal and feedback signal among Fig. 3 shown in it please be simultaneously with reference to Fig. 3 and Fig. 4.Reference signal 30a is and feedback signal 35a feed-in simultaneously phase detectors 220, because feedback signal 35 is the results after reference signal 30 delayed circuit 210 effects, if inverted logic circuit 310 equates that with the reaction time of buffer 320 then the phase place of feedback signal 35a should fall behind than reference signal 30a.Then, phase detectors 220 utilize rising edge (risingedge) r0 of reference signal 30a to obtain the state of feedback signal 35a, and as shown in Figure 4, this moment, accessed signal should be logical one.By suitable design, when getting access to the signal of logical one, phase detectors 220 can make delayed control signal 32 be logical one, and, make the numerical value of count signal 33 increase, to prolong the time of delay of reference signal 30 with these delayed control signal 32 feed-in counters 230.Then owing to increase time of delay of reference signal 30, so the phase difference between feedback signal 35a and the reference signal 30a also increase, with regard to the phase change of the two, the rising edge r5 displacement to the right of visual feedback signal 35a at this moment.Then, phase detectors 220 utilize the rising edge r0 of reference signal 30a to obtain the state of feedback signal 35a once again, if this moment, accessed signal still was a logical one, just make delayed control signal 32 be logical one once again, the numerical value of count signal 33 is increased, to prolong the time of delay of reference signal 30 once again.So, the phase difference between feedback signal 35a and the reference signal 30a will more increase, and can be considered the rising edge r5 displacement to the right once again of feedback signal 35a.Therefore, by the effect of these controlling mechanisms, as long as reference signal 30.The detected signal of rising edge r0 be logical one, can further increase the time of delay of reference signal 30, make feedback signal 35 (lagging) reference signal 30 that more lags behind.
By above as can be known, increase the time of delay of reference signal gradually, and the rising edge of feedback signal is moved to right gradually.It should be noted that after feedback signal 35a ' forms its rising edge r5 ' is as long as lag behind rising edge r0 more slightly, the accessed signal of rising edge r0 this moment just is converted to logical zero by logical one immediately.By suitable design, when getting access to the signal of logical zero, phase detectors 220 can make delayed control signal 32 be logical zero, just begin to reduce the numerical value of count signal 33 this moment, make time of delay that delay circuit 210 produced toward readjustment, may can make rising edge r5 take the lead rising edge r0 again, and make delayed control signal 32 become logical one, and increase the numerical value of count signal 33.In other words, so go round and begin again, just can make rising edge r5 and rising edge r0 remain on an extremely short distance, as the relation of rising edge r5 ' in graphic, near 1/2 cycle with rising edge r0.
By above as can be known, wait the effect of delay locked loop whereby, can make 1/2 cycle time (being T/2) that is fixed on reference signal time of delay; That is when the frequency of reference signal 30 was 200MHz, be 2.5ns time of delay.Please pay special attention to, the original purpose of this circuit is in order to 100MHz signal delay T/4; Therefore on the practice, we utilize the reference signal 30 of 200MHz to implement delay correction work in advance, to obtain the time of delay of 2.5ns.After time of delay is fixing, 1/4 cycle time (being T/4) because of 2.5ns is equal to the 100MHz signal,, meet design requirement fully if with 100MHz signal feed-in delay circuit 210, can make 100MHz signal delay T/4 this moment.Moreover, with these delay locked loops, have a safe phase locking range SR, that is, as long as feedback signal 35a falls within the safe phase locking range SR, by the effect of phase detectors 220, all can finish phase-locked program, to obtain correct time of delay.
Next, will utilize delay locked loop to produce the time delay in 1 cycle, and be illustrated with example.Please refer to Fig. 5, it illustrates the delay locked loop calcspar that postpones one-period.Delay locked loop comprises delay circuit 210, phase detectors 220 and counter 230.Phase detectors 220 can be according to the phase difference of 35 of reference signal 30 and feedback signals with in the delayed control signal 52 feed-in counters 230, to adjust the numerical value of count signal 53, make delay circuit 210 produce according to this correct time of delay.Hereinafter, the sequential chart with cooperating reference signal 50 with feedback signal 55 is further described.
Please refer to Fig. 6, it illustrates the sequential chart between reference signal and feedback signal among Fig. 5, please be simultaneously with reference to Fig. 5 and Fig. 6.As shown in the figure, reference signal 50 is and feedback signal 55 phase detectors of feed-in simultaneously 220, because feedback signal 55 is the results after reference signal 50 delayed circuit 210 effects, so the phase place of feedback signal 55 should fall behind than reference signal 50.Same, phase detectors 220 utilize the rising edge r50 of reference signal 50 to obtain the state of feedback signal 55, to adjust time of delay.But as shown in Figure 6 because feedback signal 55 falls behind reference signals 50, so the time phase detectors 220 accessed signals should be logical zero; Above once describe in detail, when the signal that gets access to when phase detectors 220 is logical zero, count signal 33 is successively decreased, if count signal 33 promptly is parked in minimum point at the beginning, then delay circuit 210 will remain on present state at time of delay of being produced, can not change.In other words, get access to first signal from phase detectors 220, just do not have any change time of delay, duty is event, and nature can't make reference signal 50 reach the design requirement that postponed for 1 cycle.So postpone phase-locked funny Lu Eryan with these, have a wrong phase locking range FR, that is, as long as feedback signal 55 falls within the wrong phase locking range FR, promptly can't finish correct phase-locked program, make the circuit can't normal operation.
Clearly, the shortcoming of tradition delay locked loop is, if wish to get 1/4 cycle and the two kinds of different delays of 1 cycle, just must set up two groups of different delay locked loops, producing different time of delay respectively, and can't produce this two kinds of different delays with same delay locked loop.So, not only taken the circuit area of twice, more increased production cost and circuit complexity, industry applications is greatly reduced.
Summary of the invention
Technical problem to be solved by this invention provides a kind of phase detection device, and the phase-locked funny road of the delay that framework is gone out can be applicable to the delay in 1/4 cycle, 1/2 cycle and 1 cycle simultaneously, to reduce circuit complexity and production cost, improves industry applications.
To achieve these goals, the present invention proposes a kind of phase detection device, being summarized as follows of this device:
Phase detection device can produce a delayed control signal according to the phase difference between reference signal in the delay locked loop and feedback signal, and in the feed-in counter; Then, counter can be adjusted the numerical value of count signal according to delayed control signal, satisfies different time delay demands to make delay circuit.Phase detection device can comprise phase detectors, inverted logic circuit, deferred mount, locking devicen and or logical circuit, wherein, phase detectors can utilize reference signal to obtain state between feedback signal, and produce detection signal.Then, the inverted logic circuit can with detection signal anti-phase be feed-in deferred mount behind the anti-phase detection signal, anti-phase detection signal is postponed a little, and in the feed-in locking devicen.After locking devicen receives anti-phase detection signal, can produce a latch-up signal and feed-in or logical circuit according to this, or another input of logical circuit couples with detection signal then.Behind two signal feed-ins or the logical circuit, or logical circuit can be according to the state of detection signal and latch-up signal with in the delayed control signal feed-in counter, counter can be adjusted count signal, meets different time delay demands such as 1/4 cycle, 1/2 cycle and 1 cycle to make delay circuit.
For allowing above-mentioned purpose of the present invention, feature and the advantage can be brighter and understandable, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
The reference signal of Fig. 1 shown in being and the phase diagram between inhibit signal;
Fig. 2 is a delay locked loop calcspar in the prior art;
Fig. 3 is the delay locked loop calcspar that postpones T/4 in the prior art;
Fig. 4 is the sequential chart between reference signal and feedback signal among Fig. 3;
Fig. 5 postpones the delay locked loop calcspar of phase on one side in the prior art;
Fig. 6 is the sequential chart between reference signal and feedback signal among Fig. 5;
Fig. 7 is the correct sequential chart of reference signal and feedback signal when phase-locked of the delay locked loop of Fig. 5;
Fig. 8 is a preferred embodiment shown in the present, the delay locked loop calcspar that is provided;
Fig. 9 is the circuit diagram of phase detection device among Fig. 8;
Figure 10 is the sequential chart of each signal among Fig. 9;
Figure 11 is the circuit diagram after the phase detection device improvement among Fig. 9;
Figure 12 is the sequential chart of each signal among Figure 11.
Embodiment
For addressing the above problem, the practice proposed by the invention is the time of delay that in advance increases reference signal 50, and feedback signal 55 is moved to right to the phase-locked SR scope of safety, the phase difference that utilizes phase detectors 220 to detect between two input signals again is to finish correct phase-locked program; Correct phase-locked program please refer to Fig. 7.The correct sequential chart of reference signal and feedback signal when phase-locked shown in Figure 7.As shown in the figure,, must earlier feedback signal 55 be moved to right, the rising edge r55 of feedback signal 55 is fallen in the safe phase locking range SR for finishing correct phase-locked program; Treat that rising edge r55 falls into after the safe phase locking range SR, phase detectors 220 utilize the rising edge r50 of reference signal 50 to obtain the state of feedback signal 55 again, just can get access to logical one smoothly this moment, the numerical value of count signal 53 increased, to prolong the time of delay of reference signal 50.At this moment, because the running of phase-locked loop makes feedback signal 55 can continue displacement to the right, form until feedback signal 35 '.As noted before.After treating to determine time of delay, by the phase place between reference signal among Fig. 7 50 and feedback signal 55 ' as can be known, be the time delay in 1 cycle at this moment, meet design requirement fully.In sum, desire to make reference signal can reach the time delay in 1 cycle, the focusing on of design, must manage to make the rising edge r55 of feedback signal 55 to fall into safe phase locking range SR earlier after, can borrow phase detectors 220 to adjust the numerical value of count signal 53, make the circuit normal operation.Therefore, how to make the rising edge r55 of feedback signal 55 fall in the safe phase locking range SR key when just having become circuit design.
Please refer to Fig. 8, shown in it according to a preferred embodiment of the present invention, the delay locked loop calcspar that is provided.Delay locked loop includes phase detection device 820, and its function is identical with the conventional phase detector, is in order to the phase place of comparison reference signal 80 with feedback signal 85, and adjusts the time of delay of reference signal 80 according to this; Different is, phase detection device 820 is except that the delay that applies to 1/4 cycle and 1/2 cycle in graphic, also applicable to 1 delay of meeting the phase, so the delayed control signal 82 that produced of phase detection device 820 can satisfy the different time delay demand of delay circuit 210, its concrete practice will be in hereinafter being illustrated.
As shown in the figure, phase detection device 820 comprises phase detectors 220 and draw-gear 810, and the function of phase detectors 220 in above repeatedly explanation, repeats no more.Importantly, when time of delay in 1 cycle of needs, by the effect of delay locked loop of the present invention, detection signal 84 initial values of exporting from phase detectors 220 (initial value) should be logical zero (above existing detailed description the in detail please refer to Fig. 5 and Fig. 6 and explanation thereof).But the invention is characterized in, this moment, the logical zero of detection signal 84 can make output signal one delayed control signal 82 of draw-gear 810 be logical one, behind these delayed control signal 82 feed-in counters 230, can increase the time of delay of reference signal 80, make feedback signal 85 displacement to the right; That is, phase detectors 220 still can't correctly adjust when postponing with situation under, can utilize draw-gear 810 to increase time of delay, with the effect of temporary transient replacement phase detectors 220 in advance.After feedback signal 85 falls into safe phase locking range, phase detectors 220 get final product output logic 1, this moment is forbidden energy (disable) draw-gear 810 just, and recovers with detection signal 84 as delayed control signal 82 feed-in counters 230, to proceed the adjustment of time of delay.
Please refer to Fig. 9, the circuit diagram of phase detection device among Fig. 8 shown in it.Phase detection device 820 comprises phase detectors 220 and draw-gear 810, and wherein, draw-gear 810 comprises inverted logic circuit 840, breech lock (latch) device 830 and or logical circuit 850.As shown in the figure, inverted logic circuit 840 is to couple with phase detectors 220, in order to detection signal 84 anti-phase be anti-phase detection signal 84a.Then, with anti-phase detection signal 84a feed-in locking devicen 830, locking devicen 830 can be according to the state of anti-phase detection signal 84a with latch-up signal 86 feed-ins or logical circuit 850.Or after logical circuit 850 receives detection signal 84 and latch-up signal 86, as long as detection signal 84 and latch-up signal 86 one are logical one wherein, can make the delayed control signal 82 of output be logical one, when only detection signal 84 was logical zero with latch-up signal 86, delayed control signal 82 sides that exported were logical zero.In delayed control signal 82 feed-in counters 230, can adjust the numerical value of count signal 83, to adjust time of delay.Hereinafter, will do further explanation at the sequential chart of each signal.
Please refer to Figure 10, the sequential chart of each signal among Fig. 9 shown in it.Behind reference signal 80 and the feedback signal 85 feed-in phase detectors 220, phase detectors 220 promptly utilize the rising edge r80a of reference signal 80 to obtain the state of feedback signal 85, and should get access to logical zero this moment, so detection signal 84 also is a logical zero.Then, effect by inverted logic circuit 840, can with detection signal 84 anti-phase be in anti-phase detection signal 84a and the feed-in locking devicen 830, this moment is because anti-phase detection signal 84a is a logical one, so can make output signal one latch-up signal 86 of locking devicen 830 be logical one, and with latch-up signal 86 feed-ins or logical circuit 850.By as can be known graphic, detection signal 84 is all with latch-up signal 86 or the input signal of logical circuit 850, and this moment, detection signal 84 was a logical zero, and latch-up signal 86 is a logical one, so can make delayed control signal 82 in logical one and the feed-in counter 230, make lengthening time of delay.As indicated above, time of delay, lengthening can be considered the rising edge r85a displacement to the right of feedback signal 85, when treating that feedback signal 85 moves to right position to rising edge r85b, the falling edge (illustrating) that just surpasses reference signal 80 as dotted line in graphic, the accessed state of the rising edge r80b of reference signal 80 changes logical one into by original logical zero this moment, thus detection signal 84 also be converted to logical one.Then, borrow inverted logic circuit 840 with in the anti-phase detection signal 84a feed-in locking devicen 830, this moment is because anti-phase detection signal 84a protects logical zero, so can make latch-up signal 86 be logical zero locking devicen 830 forbidden energy.Behind detection signal 84 and latch-up signal 86 feed-ins or the logical circuit 850, delayed control signal 82 still is a logical one, continues time of delay to prolong so can make.It should be noted that henceforth the interim task of locking devicen 830 was finished already, and adjusted work ensuing time of delay, then be responsible for by phase detectors 220, irrelevant with locking devicen 830.Because this moment, feedback signal 85 entered safe phase locking range, along with the running of forcing the road, the rising edge r85b of feedback signal 85 can move to right gradually to the position of rising edge r85 ', and forming feedback signal 85 ', this moment, the rising edge r85 ' of feedback signal 85 ' was almost close fully with the rising edge r80b of reference signal 80.So by the phase relation of reference signal 80 with feedback signal 85 ', be 1 cycle Ci Shi time of delay as can be known, meets design requirement fully.
Please refer to Figure 11, the phase detection device circuit diagram of another embodiment of the present invention shown in it.As shown in the figure, deferred mount 120 is to be coupled to inverted logic circuit 840 and locking devicen 830, by the effect of deferred mount 120, can will postpone in the anti-phase detection signal 84a feed-in locking devicen 830 of labour; It should be noted that the purpose that anti-phase detection signal 84a is postponed, be to obtain the detection signal 84 of a stable logic 1.Then please refer to Figure 12, the sequential chart of each signal among Figure 11 shown in it.Because circuit is when actual operation, the rising edge of feedback signal 85 can cause detection signal 84 instabilities during near the falling edge of reference signal 80, therefore before detection signal 84 is unstable as yet, can not utilize tool as delayed control signal 82, to avoid circuit erroneous action; So by the effect of deferred mount 120, can not continue to allow anti-phase detection signal 84a remain on logical one before detection signal 84 is stable as yet, so that delayed control signal 82 is stabilized in the state of logical one, not examined signal 84 unsure states influence.It should be noted that, when design, need make the time of delay of deferred mount 120 greater than the 84 unsettled times of detection signal, in so the signal (being anti-phase detection signal 84a) of feed-in locking devicen 830 is anti-phase (when meaning is about to locking devicen 830 forbidden energy), detection signal 84 settles out already, this moment can be with detection signal 84 as control signal 82, to continue the adjustment work of time of delay, as noted before.
The disclosed phase detection device of the above embodiment of the present invention, when delay locked loop need produce the delay in 1/4 cycle or 1/2 cycle, because feedback signal promptly falls in the safe locker scope at the beginning, meaning is that the initial state of detection signal can make the stable running of circuit.Moreover, when the phase-locked funny road of delay need produce the delay in 1 cycle, after the present invention can make feedback signal enter safe phase locking range by draw-gear, utilize phase detectors to carry out the adjustment of time of delay again, so, can produce the time delay in 1 cycle.So phase detection device provided by the present invention, can make same delay circuit produce 1/4 cycle, 1/2 cycle or 1 cycle etc. when multiple with postponing, not only saved one times circuit area, more reduced production cost and circuit complexity, industry applications is greatly improved.
It should be noted that in the present embodiment be with the RS latch circuit as locking devicen 830 and be illustrated, so be familiar with this operator and realize and the similar function of locking devicen when utilizing him to plant circuit, only still do not break away from spirit of the present invention.
In sum; though the present invention discloses as above with a preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is awkward when looking accompanying the claim person of defining of institute.

Claims (6)

1, a kind of phase detection device in order to producing a delayed control signal, and satisfies the different time delay demand of delay circuit according to described delayed control signal, it is characterized in that: comprising:
One phase detectors are in order to detect phase difference between a reference signal and a feedback signal to export a detection signal; And
One draw-gear couples with described phase detectors, and exports this delayed control signal according to described detection signal, and to adjust the time of delay of this reference signal, this draw-gear comprises:
One inverted logic circuit is coupled to this phase detectors, in order to this detection signal is anti-phase, to export an anti-phase detection signal;
One locking devicen is coupled to this inverted logic circuit, and exports a latch-up signal according to this anti-phase detection signal; And
One or logical circuit, be coupled to these phase detectors and this locking devicen, and export this delayed control signal according to this detection signal and this latch-up signal.
2, phase detection device as claimed in claim 1 is characterized in that described locking devicen is the RS latch circuit.
3, phase detection device as claimed in claim 1 is characterized in that described draw-gear also comprises:
One deferred mount is coupled between this inverted logic circuit and the locking devicen, in order to postpone this anti-phase detection signal.
4, phase detection device as claimed in claim 3 is characterized in that described locking devicen is the RS latch circuit.
5, a kind of phase detection device in order to producing a delayed control signal, and satisfies the different time delay demand of delay circuit according to this delayed control signal, and this phase detection device comprises:
One phase detectors are in order to detect phase difference between a reference signal and one time labour signal to export a detection signal;
One inverted logic circuit is coupled to this phase detectors, in order to this detection signal is anti-phase, to export an anti-phase detection signal;
One deferred mount is coupled to this inverted logic circuit, in order to postpone this anti-phase detection signal;
One locking devicen is coupled to this deferred mount, and the witch exports a latch-up signal according to this anti-phase detection signal after postponing; And
One or logical circuit, be coupled to these phase detectors and this locking devicen, and export this delayed control signal, to adjust the time of delay of this reference signal according to this detection signal and this latch-up signal.
6, phase detection device as claimed in claim 5 is characterized in that described locking devicen is the RS latch circuit.
CNB01134475XA 2001-11-05 2001-11-05 Phase detector Expired - Lifetime CN1159848C (en)

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JP3939715B2 (en) * 2004-08-20 2007-07-04 日本テキサス・インスツルメンツ株式会社 Phase-locked loop circuit
US7034591B2 (en) * 2004-08-30 2006-04-25 Texas Instruments Incorporated False-lock-free delay locked loop circuit and method
CN113708758A (en) * 2020-05-20 2021-11-26 中兴通讯股份有限公司 Phase detection method, device and equipment thereof

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Granted publication date: 20040728