CN115951836B

CN115951836B - DFI command and data channel universal controller and read-write method thereof

Info

Publication number: CN115951836B
Application number: CN202310064597.5A
Authority: CN
Inventors: 李兵; 王晓阳; 何亚军; 钱阔
Original assignee: Shanghai Kuixin Integrated Circuit Design Co ltd
Current assignee: Shanghai Kuixin Integrated Circuit Design Co ltd
Priority date: 2023-01-12
Filing date: 2023-01-12
Publication date: 2023-09-05
Anticipated expiration: 2043-01-12
Also published as: CN115951836A

Abstract

The application relates to a universal controller for a DFI command and a data channel and a read-write method thereof. The controller includes: a register configuration and command and write data parsing module configured to designate relevant parameters of the DFI protocol according to the received externally configured register information to generate configuration information, determine a type of command according to the received external command, and convert data to be written according to the determined command type; the command channel control module is configured to complete control of command channel signals according to the configuration information so as to enable the DRAM to be in a specified state; the write data channel module is configured to complete control of write data channel signals according to the configuration information so as to write data into the DRAM; and a read data channel module configured to complete control of a read data channel signal according to the configuration information to read data from the DRAM.

Description

DFI command and data channel universal controller and read-write method thereof

Technical Field

The present application relates to the field of data storage, and more particularly, to a DFI command and data path generic controller architecture for memories using DFI interfaces.

Background

In the field of data storage, various new memories have been developed with the development of technology, and DFI interfaces have been used in new memories such as LPDDR4 and LPDDR 5.

DDR memory interfaces are currently generally divided into two parts, memory control logic (MC, memory Controller) and physical layer interfaces (PHY, physical Interface). In order to achieve a standard interconnection between the two, a standard communication interface between the MC and the PHY is required. DFI is such a specification. The DFI standard is proposed to define a universal interface between the MC and the PHY to increase the multiplexing rate of the independent modules (IP cores, etc.), thereby reducing the cost and project period.

Specifically, the DFI interface module is configured to send a signal input by the instruction sending module to the DDR physical layer PHY supporting the DFI standard according to the DFI standard protocol, and to fetch data from the read-write data channel module, output the data according to the DFI standard protocol, and simultaneously receive the data input from the physical layer PHY and send the data to the read-write data channel module.

But the configuration of using the DFI interface is also different for various types of DDRs. Also, even with the same type of DDR, the DFI interface used for performing different functions is configured differently. Therefore, a general solution is lacking to support arbitrary configuration of DFI interface parameters, i.e., a general DFI interface (all configurations supporting DFI interface parameters) cannot be implemented. Moreover, due to the lack of such versatility, the existing DFI interfaces have to use more hardware resources in order to implement various functions and various configurations, increasing the cost of the system and reducing the operating efficiency of the system.

Accordingly, there is a need to provide a solution for a universal DFI interface that enables a reduction in the consumption of resources with a smaller structure and with high performance.

Disclosure of Invention

The application provides a universal solution, relates to software and hardware improvement, supports arbitrary parameter configuration of a DFI protocol and is based on optimizing hardware resources.

According to a first aspect of the present application, there is provided a DFI command and data path generic controller comprising:

a register configuration and command and write data parsing module configured to designate relevant parameters of the DFI protocol according to the received externally configured register information to generate configuration information, determine a type of command according to the received external command, and convert data to be written according to the determined command type;

the command channel control module is configured to complete control of command channel signals according to the configuration information so as to enable the DRAM to be in a specified state;

the write data channel module is configured to complete control of write data channel signals according to the configuration information so as to write data into the DRAM; and

and the read data channel module is configured to complete control of read data channel signals according to the configuration information so as to read data from the DRAM.

According to a second aspect of the present application, there is provided a write operation method for a DFI command and data path general controller, comprising:

1) Configuring relevant parameters of the write operation to select a working scene;

2) Receiving an external command and data to be written;

3) Calculating the initial phase of the command according to the configured command interval;

4) Controlling the sending starting point of each command channel according to the calculated starting phase of the command, and outputting a command load;

5) Calculating wrat_integral_offset/wrat_phase_offset/wrcmd2data_integral_offset/wrcmd2data_phase_offset corresponding to the write command according to the configured command interval to adjust the interval from the write command to dfi_wrdata_en_pn and control the initial phase of dfi_wrdata_en_pn, adjust the interval from the write command to dfi_wrdata_wn and control the initial phase of dfi_wrdata_wn;

6) Obtaining a 0-delay DFI write data channel enabling signal wren 0 corresponding to the write command through synchronous broadening so as to finally generate wrdata_en_valid of the DFI write channel;

7) Performing interval control from the write command to write enable/write chip select/write data;

8) And executing the initial phase control of the write enable write chip select/write data.

According to a third aspect of the present application, there is provided a read operation method for a DFI command and data path general controller, comprising:

1) Configuring relevant parameters of the read operation to select a working scene;

2) Receiving an external command;

5) Calculating the rdlat_integral_offset/rdlat_phase_offset corresponding to the read command according to the configured command interval so as to adjust the interval from the read command to the dfi_rddata_en_pn and control the starting phase of the dfi_rddata_en_pn;

6) Obtaining a 0-delay DFI read data channel enabling signal rd_en0 corresponding to the read command through synchronous stretching so as to finally generate rddata_en_valid of the DFI read channel;

7) Performing interval control from the read command to read enable/read chip select;

8) Performing a start phase control of the read enable/read chip select;

9) Performing initial phase detection of read data; and

10 After aligning the read data.

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Drawings

In order to describe the manner in which the above-recited and other advantages and features of the application can be obtained, a more particular description of the application briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the application and are not therefore to be considered to be limiting of its scope, the application will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:

fig. 1 shows a schematic block diagram of a DFI command and data path generic controller according to one embodiment of the application.

Fig. 2 illustrates an example write operation flow based on the DFI command and data path generic controller of fig. 1.

Fig. 3 illustrates an example read operation flow based on the DFI command and data path generic controller of fig. 1.

FIG. 4 illustrates the initial Phase control principle of a 1T/2T command when LPDDR4 ratio is 1:2 in an embodiment of the application.

FIG. 5 illustrates the control principle of the start Phase of a 1T/2T command when LPDDR4 ratio is 1:4 in an embodiment of the application.

FIG. 6 illustrates the control principle of the LPDDR5 1T/2T command in an embodiment of the application.

Fig. 7 shows the calculation principle of wrat_integer_offset/wrat_phase_offset when rg_phy_wrat is 18 at ratio 4 in the embodiment of the present application.

Fig. 8 shows a schematic diagram of the control principle of wrata_en_valid of the DFI write channel in an embodiment of the application.

FIG. 9 shows a schematic diagram of the initial phase control principle of DFI write channel dfi_wrdata_en_pn at ratio 4 in an embodiment of the present application.

Detailed Description

To implement the solution of the generic DFI interface, the present application first designs a DFI command and data path generic controller, and in fig. 1, a schematic block diagram of the DFI command and data path generic controller according to one embodiment of the present application is shown.

As shown, the DFI command and data path generic controller 1000 basically includes a register configuration and command and write data parsing module 1100, a command path control module 1200, a write data path module 1300, and a read data path module 1400. The modules may be implemented in hardware, software, or a combination thereof and may communicate with each other over data communication lines therebetween.

The register configuration and command and write data parsing module 1100 is configured to specify relevant parameters of the DFI protocol according to the received externally configured register information to generate configuration information, determine a type of command according to the received external command, and convert data to be written according to the determined command type. Specifically, the work tasks mainly include: parameters such as device type (device type, e.g., lpddr4/lpddr 5), ratio of dfi_clk and TCK, BL16/BL32, bank group/8B/16B mode, interval between respective commands, etc. are selected according to the register information. The above parameters will directly affect the timing of the DFI interface. The register configuration and command and write data parsing module will determine whether the command is of the 1T or 2T type and convert the received write data to a particular format based on the determined command type. After the above-described work is completed, the register configuration and command and write data parsing module 1100 generates a corresponding output as configuration information.

The command channel control module 1200 is configured to complete control of command channel signals according to configuration information to bring the DRAM into a specified state (including read/write/refresh operations, etc.). The command channel signals include dfi_cs_pn (rank for selecting each channel), dfi_address_pn (command payload for each channel). The method is mainly characterized by supporting different initial phases, supporting 1T/2T commands and being optional in rank. Further, the command channel control module 1200 is also configured to calculate the start phase of the DFI command and drive dfi_cs_pn and dfi_address_pn according to the input command payload, command valid indication (pulse signal), 1T/2T type.

The write data channel module 1300 includes a preprocessing module 1310 and a write enable write data write chip select control module 1320. The preprocessing module 1310 includes a command synchronous stretching and delay processing module 1312, a carry determination and buffering module 1314, a start phase calculation and buffering module 1316, and a pointer calculation module 1318.

First, the write data channel module 1300 is configured to complete control of the write data channel signal according to the configuration information to write data to the DRAM as a whole. The write data channel signals include dfi_wrdata_cs_pn (specifying the chip to which write data channel n corresponds), dfi_wrdata_en_pn (specifying whether write data channel n is enabled), dfi_wrdata_wn (specifying the data on write data channel n). The method is mainly characterized by supporting different initial phase, chip optional, supporting interval of writing command to dfi_wrdata_en_pn and supporting interval of writing command to dfi_wrdata_wn. Moreover, the write data channel module 1300 is further configured to calculate the interval of the write command to dfi_wrdata_en_pn and the start phase of dfi_wrdata_en_pn, the interval of the write command to dfi_wrdata_wn and the start phase of dfi_wrdata_wn, and drive the related signals according to the input chip information and the write data load.

And subdivided into its components, the operation of each of its components is as follows:

the command synchronous stretching and delay processing module 1312 is configured to stretch the write command pulse according to the configuration information, and store the stretched write command pulse into the shift register to generate valid indication signals for controlling dfi_wrdata_en_pn and dfi_wrdata_wn;

the carry determination and buffer module 1314 is configured to dynamically calculate whether a carry occurs in the interval corresponding to each write command according to the configuration information, and store carry information into the carry information shift register for adjusting the interval from the write command to dfi_wrdata_en_pn and the interval from the write command to dfi_wrdata_wn;

a start phase calculation and buffer module 1316 configured to calculate a start phase of dfi_wrdata_en_pn/dfi_wrdata_wn and store start phase information into a phase information shift register to support the above-described interval configurable function;

the pointer calculation module 1318 is configured to control the carry information shift register and the phase information shift register to output data so as to support the interval configurable function, thereby assisting in controlling dfi_wrdata_en_pn/dfi_wrdata_wn;

the write enable write data write chip select control module 1320 is configured to select to directly output the command stretching signal or delay a specific beat to output the command stretching signal according to configuration information and finally control dfi_wrdata_en/dfi_wrdata_wn, and control dfi_wrdata_cs_pn according to configuration information and dfi_wrdata_en_pn.

The read data channel module 1400 includes: a preprocessing module 1410, a read enable read chip select control module 1412, and a read data control module 1414.

Overall, the read data channel module 1400 is configured to perform control of the read data channel signal according to the configuration information to read data from the DRAM. The read data channel signals include dfi_rddata_cs_pn (specifying the chip to which read data channel n corresponds), dfi_rddata_en_pn (specifying whether read data channel n is enabled), dfi_rddata_valid_wn (a data valid indication for read data channel n), dfi_rddata_wn (data returned on read data channel n). The method is mainly characterized by supporting different initial phase, chip optional, supporting interval coordination from a read command to dfi_rddata_en_pn and supporting interval coordination from the read command to dfi_rddata_wn.

The preprocessing module 1410 of the read data channel module 1400 is substantially identical in structure to the preprocessing module 1310 of the write data channel module 1300, except that it performs control of read data. In other words, both may share the same set of hardware structures, or be respectively composed of two sets of the same hardware structures. Since the various components and functions thereof in the pre-processing module 1310 have been specifically described above, the same will not be described again here, but only the different parts thereof will be described.

Specifically, the read-enabled chip select control module 1412 selects to directly use the corresponding spread signal or delay a specific DFI clock for the corresponding spread signal according to the configuration interval information and the carry information to obtain rddata_en_valid (dfi_rddata_en_pn's path indication signal when the start phase is 0), respectively.

And the read data control module 1414 calculates the initial phase of the read data by looking up the table of the input dfi_rddata_valid_wn, and aligns the data returned by the PHY according to the initial phase of the read data and outputs the aligned data.

The remainder is substantially identical to the write data module 1300, so that both the pre-processing module 1310 and the pre-processing module 1410 may be implemented by performing the read and write operations described above, respectively, on the same pre-processing module. But for clarity the two are shown separated in fig. 1 to make the structure clearer.

In addition to the above modules, the DFI command and data path generic controller 1000 further includes a DFI interface 1500 for transmitting signals to the DDR physical layer PHY supporting the DFI standard according to the DFI standard protocol, and for fetching data from the read/write data path module, outputting data according to the DFI standard protocol, and receiving data inputted from the physical layer PHY and transmitting to the read/write data path module.

Having a basic understanding of the basic structure of the DFI command and data path generic controller 1000 and the main functions of its components, an example write operation flow and an example read operation flow based on the DFI command and data path generic controller, respectively, are described below in conjunction with fig. 2 and 3.

First, as shown in FIG. 2, an example write operation flow 200 of the DFI command and data channel generic controller is shown.

First, in step 202, write operation related parameters are configured to select a working scenario. Write operations require configuration of relevant parameters to support a particular scenario. As previously described, the reception parameters may include receiving externally configured register information to specify relevant parameters of the DFI protocol. Parameters such as device type (device type, e.g., lpddr4/lpddr 5), ratio of dfi_clk and TCK, BL16/BL32, bank group/8B/16B mode, interval between respective commands, etc. are selected according to the register information. The specific implementation will be described in detail in operation 1 below. For example, a write operation requires configuration of relevant parameters to specify 2 metrics of the DFI write channel to adapt to parameters corresponding to a selected device, the configuration process being described in operation 6 below.

After the operational scenario is selected, at step 204, an external command and data to be written are received. The type of command received will also be described in detail in operation 2 below.

In step 206, a start phase of the command is calculated according to the configured command interval, and used to control the transmission start point of each command channel, and the specific implementation procedure will be described in detail in operation 3 below.

Thereafter, in step 208, the transmission start points of the respective command channels are controlled according to the command start phase calculated in the above step, and the command payload is outputted (the memory grain of the memory is put into a specific state), as described in operation 4 (3 scenarios are supported, as shown in fig. 4 to 6). The purpose of the control Rank is to select a specific row of particles, and the starting point of the sending of each command channel needs to be consistent with the command load, and the specific implementation process is as described in operation 5 below. Thus, all commands required for the write operation have been sent to the granule, allowing the granule to enter the write operation state.

In step 210, wrat_integral_offset/wrat_phase_offset/wrcmd2data_integral_offset/wrcmd2data_phase_offset corresponding to the write command is calculated according to the configured command interval, and is used for adjusting the interval from the write command to dfi_wrdata_en_pn and controlling the initial phase of dfi_wrdata_en_pn, adjusting the interval from the write command to dfi_wrdata_wn and controlling the initial phase of dfi_wrdata_wn, and the specific implementation process is as described in operation 7 below.

Thereafter, in step 212, the DFI write data channel enable signal wr_en0 corresponding to the write command is obtained through synchronous stretching (the delay from the write command to dfi_wrata_en_pn is configured to be 0), and is used to finally generate the wrata_en_valid of the DFI write channel, which is specifically implemented as described in operation 8 below.

Thereafter, at step 214, interval control of the write command to write enable/write chip select/write data is performed. Specifically, the n-delay DFI write data channel enable signal wrdata_en_valid and the n-delay DFI write data channel data valid indication signal wrdata_valid corresponding to the write command are implemented by dynamically adjusting the pointer, and the specific implementation process is described in operations 9 and 10 below.

Finally, at step 216, a start phase control of write enable write chip select/write data is performed. Specifically, the dfi_wrdata_en_pn/dfi_wrdata_wn/dfi_wrdata_cs_pn is controlled according to wrlat_phase_offset/wrmmd2data_phase_offset/wrdata, and the specific implementation procedure is as described in operation 11 below.

As shown, the steps 206, 210 and 212 may be performed simultaneously (in parallel) to increase the efficiency of the execution.

Next, as shown in fig. 3, an example read operation flow 300 of the DFI command and data path generic controller is shown.

As shown, at step 302, first, a read operation also requires configuration of relevant parameters to select a working scenario. The read operation requires configuration of relevant parameters to support a specific scenario, which operates similarly to step 202 in the write operation, i.e. see in particular operation 1 below. The read operation requires configuration of relevant parameters to specify that 1 index of the DFI read channel be used to adapt parameters corresponding to the selected device, the implementation of which is described in detail below in operation 12.

After the operational scenario is selected, at step 304, an external command is received. The type of command received will also be described in detail in operation 2 below.

Thereafter, at step 306, a start phase of the command is calculated according to the configured command interval, for controlling a transmission start point of each command channel, and the implementation is as described in operation 3 below.

Thereafter, at step 308, the transmission start points of the respective command channels are controlled according to the command start phase calculated in the above step, and the command payload is outputted (the memory grain of the memory is brought into a specific state), as described in operation 4 (3 scenarios are supported, as shown in fig. 4 to 6). The purpose of the control Rank is to select a specific row of particles, and the starting point of the sending of each command channel needs to be consistent with the command load, and the specific implementation process is as described in operation 5 below. So far, all the commands required for the read operation have been sent to the pellet, allowing the pellet to enter the read operation state.

Also occurring concurrently (in parallel) with steps 302-308 are steps 310-320. The method comprises the following steps:

in step 310, the rdlat_integer_offset/rdlat_phase_offset corresponding to the read command is calculated according to the configured command interval, and is used for adjusting the interval from the read command to dfi_rddata_en_pn and controlling the start phase of dfi_rddata_en_pn, which is specifically implemented as described in operation 13 below.

Thereafter, in step 312, a DFI read data channel enable signal rd_en0 of 0 delay (delay from the read command to dfi_rddata_en_pn is configured to be 0) corresponding to the read command is obtained through synchronous stretching, and the rddata_en_valid of the DFI read channel is finally generated, which is specifically implemented as described in operation 8 below.

Thereafter, at step 314, interval control by executing a read command to read enable/read chip select is performed. Specifically, the DFI read data lane enable signal rddata_en_valid for the n delays corresponding to the read command is implemented by dynamically adjusting the pointer, as described in operations 15 and 16 below.

Thereafter, at step 316, a start phase control of read enable/read chip select is performed. Specifically, dfi_wrdata_en_pn/dfi_wrdata_cs_pn is controlled according to rdlat_phase_offset, and the specific implementation is described in operation 17 below.

Thereafter, at step 318, a start phase detection of the read data, i.e., a start phase of the read data is calculated, as described in step 18 below.

Finally, in step 320, the read data is output after alignment. Specifically, performing the initial phase detection of read data outputs the output returned by the PHY to dfi_rddata_wn, with the specific implementation described above in step 19.

Also, as shown, the steps 306, 310 and 312 are performed simultaneously (in parallel) to increase the efficiency of the execution.

The operations involved in the steps of the above-described write operation and read operation are specifically described below with reference to the drawings.

Operation 1: the register configuration and command and write data parsing module configures operation related parameters:

configuring an interval from an ACTIVE command to a WRITE/READ/MASK WEITE command through a register rg_trcd; the register rg_trp configures the interval from PRECHARGE command to ACTIVE command; the register rg_tccd configures the intervals of WRITE command to WRITE command, READ command to READ command, MASK WRITE command to MASK WRITE command; the register rg_twr2pre configures the WRITE command to PRECHARGE command interval; the register rg_trd2pre configures the interval of READ command to PRECHARGE command.

Operation 2: the following signals represent externally incoming commands (dfi clock-based pulse signals):

cmd_act1 represents an ACTIVE command; cmd_pre1 represents a PRECHARGE command; cmd_wr1 represents a WRITE command that is not last in the consecutive WRITE commands; cmd_rd1 represents a non-last READ command of the consecutive READ commands; cmd_mwr1 represents a non-last MASK WRITE command in the consecutive MASK WRITE commands. Since the WRITE/READ/MASK WRITE command needs to calculate the start phase of the next PRECHARGE command (instead of the WRITE/READ/MASK WRITE command) when it is followed by the PRECHARGE command, the READ/WRITE command followed by 1 PRECHARGE command is distinguished, wherein:

cmd_wr1_folw_pre1 represents the last WRITE command in the consecutive WRITE commands (followed by 1 PRECHARGE command); similarly, cmd_rd1_folw_pre1 represents the last READ command in the consecutive READ commands; cmd_mwr1 represents the last MASK WRITE command in the consecutive MASK WRITE command.

Operation 3: the starting phase calculation principle of the command channel module is as follows:

LPDDR4 supports Phase delay. The delay information is respectively rg_trcd0, rg_tccd0, rg_twr2pre 0, rg_trd2pre 0 and rg_trp0 when Ratio is 1:2; the delay information for Ratio 1:4 is respectively rg_trcd [1:0], rg_tccd [1:0], rg_twr2pre [1:0], rg_trd2pre [1:0], rg_trp [1:0].

Since LPDDR5 uses only dfi_address_p0, phase delay is not supported. Therefore, the phase delay is set to 0 when the LPDDR5 is detected. In LPDDR4, the starting phase of the next command is calculated according to the command issued by MC to DFI interface. Since the principle of the various command combination operations is the same, only the parameters are different, so only the principle of the usual WRITE operation will be described. The method comprises the following steps:

when a cmd_act1 command (followed by a WRITE command) is detected, the rg_trcd [0]/rg_trcd [1:0] is added according to the ratio (1:2 and 1:4), respectively, because the phase delay value of the ACT command to the WRITE command is the active phase delay of rg_trcd.

When cmd_wr1 (and subsequent WRITE commands) is detected, the rg_tccd [0]/rg_tccd [1:0] is added according to the ratio, respectively, since the phase delay value of the adjacent WRITE commands is the active phase delay of rg_tccd.

When cmd_wr1_flow_pre1/cmd_mwr1_flow_pre1 (followed by PRECHARGE command) is detected, since the phase delay value from WRITE command to PRECHARGE command is the valid phase delay of rg_twr2pre, rg_twr2pre [0]/rg_twr2pre [1:0] is added according to the ratio, respectively.

When the cmd_pre1 command (followed by an ACTIVE command) is detected, since the phase delay value of PRECHARGE command to ACTIVE command is the ACTIVE phase delay of rg_trp, rg_trp [0]/rg_trp [1:0] is added according to the ratio, respectively.

Operation 4: controlling the sending starting point of each command channel according to the command starting phase:

after calculating the starting phase of the command, the control of the starting phase of dfi_address_pn (command load) in the command channel module can be further realized. 3 types (LPDDR 4 and ratio 1:2/LPDDR4 and ratio 1:4/LPDDR 5) are supported according to the configuration of the registers, as shown in detail in FIGS. 4-6 below.

FIG. 4 is a diagram illustrating the initial Phase control principle of a 1T/2T command when LPDDR4 ratio is 1:2 in an embodiment of the application.

As shown, phase_delay [1:0] is the command start phase (only phase_delay [0] is active when ratio is 1:2).

The state of cmd_valid (command pulse signal) and phase_delay is extended by 2 dfi_clk by 2 beats, respectively. Dfi_address_pn [5:0] is generated by mux to CA (command payload) according to the current phase delay value (cmd_valid/cmd_valid_d1/cmd_valid_d2 respectively corresponding to phase_dly/phase_dly_d1/phase_dly_d2 in sequence. The method comprises the following steps:

when cmd_valid is high, detecting that a 1T command phase delay is 0, and synchronously outputting a corresponding command to dfi_address_pn (a moment in the figure);

when the cmd_valid/cmd_valid_d1 is high and the 1T command phase delay/phase_dly_d1 is 1, respectively and synchronously outputting the corresponding command to dfi_address_pn (d and e in the figure);

When the cmd_valid/cmd_valid_d1 is high and the 2T command phase delay/phase_dly_d1 is 0, respectively and synchronously outputting the corresponding command to dfi_address_pn (h and l moments in the figure);

when the 2T command phase delay/phase_dly_d1/phase_dly_d2 is 1 corresponding to the high cmd_valid/cmd_valid_d1/cmd_valid_d2, the corresponding commands are synchronously output to dfi_address_pn (n, o, p time in the figure) respectively.

FIG. 5 is a diagram showing the control principle of the initial phase of a 1T/2T command when LPDDR4 ratio is 1:4 in an embodiment of the application.

As shown in the above figure, phase_delay [1:0] is the command start phase.

By beating cmd_valid and phase_delay 1 beat respectively, its state is extended by 1 dfi_clk. And generating dfi_address_pn [5:0] by mux on ca_value according to the current phase delay value (cmd_valid/cmd_valid_d1 respectively and sequentially corresponding to phase_dly/phase_dly_d1). The method comprises the following steps:

when the cmd_valid is high and a 2T command phase delay is detected to be 0, synchronously outputting a corresponding command to dfi_address_pn (h moment in the figure);

When the cmd_valid/cmd_valid_d1 is high and the 2T command phase delay/phase_dly_d1 is 1, respectively and synchronously outputting the corresponding command to dfi_address_pn (n and o time in the figure);

when the cmd_valid/cmd_valid_d1 is high and the 2T command phase delay/phase_dly_d1 is 2, respectively and synchronously outputting the corresponding command to dfi_address_pn (p and v time in the figure);

when the cmd_valid/cmd_valid_d1 is high and the 2T command phase delay/phase_dly_d1 is 3, the corresponding commands are synchronously output to dfi_address_pn (u and w in the figure).

Fig. 6 is a diagram illustrating the control principle of the LPDDR5 1T/2T command in an embodiment of the present application.

As shown in the above graph, LPDDR5 uses only dfi_address_p0[13:0], and does not support phase delay. For a 1T command, the output will be synchronized. For the 2T command, the first half of the 2T command will be output synchronously and the second half will be output at the next dfi_clk. The method comprises the following steps:

detecting a 1T command when cmd_valid is high, and synchronously outputting a corresponding command to dfi_address_p0 (a moment in the figure);

when cmd_valid/cmd_valid_d1 is high, a 2T command is correspondingly detected, and the corresponding commands are synchronously output to dfi_address_pn (d and e in the figure).

Operation 5: control of command channel rank

The control of the command channel Rank (actuation of dfi_cs_pn) will correctly output the information of the register configuration based on the calculated starting phase. See in particular table 1 below:

TABLE 1

Table 1 is a schematic diagram showing the mapping relationship of LPDDR4/LPDDR5 1T/2T commands and RANK in an embodiment of the application.

The control mechanism of CS (rank) of LPDDR4 is the same as that of CA, and is not described in detail (rg_dfi_cs_p0 represents a rank load corresponding to the first half of 1T of a 1T command or/and 2T command; rg_dfi_cs_p1 represents a rank load corresponding to the second half of 1T of a 1T command or/and 2T command; rg_dfi_cs_p2 represents a rank load corresponding to the first half of 1T of 2T command; and rg_dfi_cs_p3 represents a rank load corresponding to the second half of 1T of 2T command). Where, only dfi_cs_p0/dfi_cs_p1 is used when ratio is 1:2.

LPDDR5 uses only dfi_cs_p0 and does not support phase delay. The control mechanism of CS is the same as CA, outputting rg_dfi_cs_p0 to dfi_cs_p0 for 1T command and holding 1 dfi_clk; the rg_dfi_cs_p0 is output to dfi_cs_p0 for the 2T command and holds 2 dfi_clk.

The specific operating principle of the write data channel module 1300 of fig. 1 is as follows:

operation 6: configuration of register configuration and command and write data parsing module 1100:

The interval rg_phy_wrat of the write command signal to dfi_wrdata_en_pn (including the integer part wrat_integer based on DFI clock and the fractional part based on phy clock), the interval rg_phy_wrcmd2data of the write command signal to dfi_wrdata (including the integer part cmd2wrdata_integer based on DFI clock and the fractional part based on phy clock) are specified by register configuration to specify 2 indexes that must be specified for the DFI write channel.

Operation 7: the carry determination and buffer module 1314 calculates the offset wrlat_integer_offset of the integer portion of the interval of the write command to dfi_wrdata_en_pn (compares the integer portion of the sum value of rg_phy_wrlat, rg_phy_wrlat and the start phase of the current command to determine whether carry occurs) based on the input write command and the interval of the write command to dfi_wrdata_en_pn. The start phase calculation and buffering module calculates the fractional part of the sum value of fractional part wrlat phase offset (rg phase wrlat and the start phase of the current command).

Similarly, the carry determination and buffer module 1314 calculates the offset wrcmd2data_integer_offset of the integer portion of the interval from the write command to dfi_wrdata_wn (compares the integer portion of the sum of rg_phy_wrcmd2data, rg_phy_wrcmd2data and the start phase of the current command) in synchronization with the interval from the write command to dfi_wrdata_wn to determine whether a carry has occurred. The start phase calculation module 1316 calculates a fractional part of the sum value of the fractional part wrcmd2data_phase_offset (rg_phy_wrcmd2data and the start phase of the current command).

Operation 8: the command synchronous stretching and delay processing module 1312 performs synchronous stretching and delay processing on the input write command signal according to the configured burst length and ratio information.

Operation 9: the pointer calculation module 1318 is configured to support multiple register configuration modes, and calculate a corresponding pointer according to the register configuration value.

Operation 10: the write enable write data write chip select control module 1320 selects to directly use the corresponding spread signal or delay a specific DFI clock for the corresponding spread signal according to the configuration interval information and the carry information to obtain wrdata_en_valid/wrdata_valid (the associated indication signals of dfi_wrdata_en_pn and dfi_wrdata_wn when the start phase is 0), respectively.

Operation 11: thereafter, dfi_wrdata_en_pn/dfi_wrdata_wn is controlled according to wrat_phase_offset (the fractional part of the interval from the write command to dfi_wrdata_en_pn), wrcmd2data_phase_offset (the fractional part of the interval from the write command to dfi_wrdata_wn), and wrdata (the data to be written by the dfi write data interface).

rg_dfi_wrdata_cs_pn configures chips corresponding to each write channel, and outputs the chips to the dfi_wrdata_cs_pn to realize control of the dfi_wrdata_cs_pn. The method comprises the following steps: dfi_wrdata_cs_pn and dfi_wrdata_en_pn are updated synchronously; the dfi_wrdata_cs_pn is extended by beating 1 beat to dfi_wrdata_en_pn, so that the dfi_wrdata_cs_pn is maintained for 1 dfi_clk more than dfi_wrdata_en_pn, thereby satisfying spec.

The specific principle of operation of the read data channel module 1400 of fig. 1 is as follows:

operation 12: the interval rg_phy_rdlat (including the DFI clock-based integer portion rdlat_integer and the phy clock-based fractional portion) that specifies the read command signal to dfi_rddata_en is configured by a register to specify 1 index that must be specified for the DFI read channel.

Operation 13: the carry determination module 1314 calculates an offset rdlat_integer_offset of an integer portion of the interval of the read command to dfi_rddata_en_pn (compares the integer portions of the sum value of rg_phy_rdlat, rg_phy_rdlat and the start phase of the current command to determine whether carry occurs) in accordance with the input read command and the interval of the read command to dfi_rddata_en_pn. The start phase calculation module 1316 calculates the fractional part of the sum value of the fractional part rdlat_phase_offset (rg_phy_rdlat and the start phase of the current command).

Operation 14: the command synchronous stretching and delay processing module 1312 performs synchronous stretching and delay processing on the input read command signal.

Operation 15: the pointer calculation module 1318 is configured to support multiple register configuration modes, and calculate a corresponding pointer according to the register configuration value.

Operation 16: the read enable chip select control module 1412 selects to directly use the corresponding spread signal or delay the corresponding spread signal by a specific DFI clock to obtain rddata_en_valid (the associated indication signal of dfi_rddata_en_pn when the start phase is 0) according to the configuration interval information and carry information (the integer part of the interval from the read command to dfi_rddata_en_pn/the offset of the integer part of the interval from the read command to dfi_rddata_en_pn).

Operation 17: thereafter, dfi_rddata_en_pn is controlled according to rdlat_phase_offset (the fractional part of the interval from the read command to dfi_rddata_en_pn). The dfi_rddata_cs_pn is correspondingly controlled by extending the dfi_rddata_en_pn by 1 DFI clock, i.e., the register configuration information is output to the dfi_rddata_cs_pn.

rg_dfi_rddata_cs_pn configures chips corresponding to each read channel, and outputs the chips to the dfi_rddata_cs_pn to realize control of the dfi_rddata_cs_pn. The method comprises the following steps: the dfi_rddata_cs_pn and the dfi_rddata_en_pn are synchronously updated; the wifi_rddata_cs_pn is expanded by beating 1 beat to the wifi_rddata_en_pn, so that the wifi_rddata_cs_pn maintains 1 dfi_clk more than the wifi_rddata_en_pn, and the spec is further satisfied.

Operation 18: the read data control module calculates the initial phase of the read data by looking up a table of the input dfi_rddata_valid_wn.

Operation 19: and aligning the data returned by the PHY according to the read data initial phase and outputting the aligned data.

After the above detailed operation is described, several parameters involved in the operation are described in detail below.

The specific implementation mechanism of dfi_wrdata_en_pn is as follows:

since the calculation wrlat_integral_offset/wrlat_phase_offset and the calculation wrcmd2data_integral_off/wrcmd2data_phase_offset and the calculation rdlat_integral_offset/rdlat_phase_offset are the same in principle, only the procedure of calculating wrlat_integral_offset/wrlat_phase_offset will be described.

When the carry determination and buffer module 1314 detects cmd_act1_d0/cmd_wr1_d0/cmd_mwr1_d0, it sums rg_phy_wrat and cnt_phase_delay to obtain phy_wrat corresponding to the subsequent write command. It is determined whether a carry occurs in the integer portion of the interval of the write command to dfi_wrdata_en_pn by comparing the integer portions of phy_wrlat and rg_phy_wrlat, and dfi_wrdata_en_pn is adjusted in time. Carry information is stored in a carry information shift register to support the interval of write commands to dfi_wrdata_en_pn.

The start phase calculation and buffering module 1316 stores the start phase information aligned with the write command into the phase information shift register to support the start phase coordination of dfi_wrdata_en_pn by dynamically adjusting the sampling time (i.e., by dynamically adjusting whether to acquire the information of the previous 1 beat and offset the problem of the command interval by 1 beat). Taking ratio of 4 and rg_phy_wrlat of 18 as an example, the detailed procedure is shown in fig. 7.

Fig. 7 is a diagram showing the calculation principle of wrat_integer_offset/wrat_phase_offset when rg_phy_wrat is 18 at ratio 4 in the embodiment of the present application. Wherein wrlat integer offset is used to adjust the interval of write commands to dfi wrdata en pn in time, wrlat phase offset is used to control the starting phase of dfi wrdata en pn.

Referring to FIG. 7, when cmd_act1_d0 and cmd_wr1_d0 are performed, the phy_wrsat corresponding to the subsequent write command is calculated according to rg_phy_wrsat and cnt_phase_delay (the initial phase accumulated value of the command). Whether a carry occurs in the integer portion of the interval of the write command to dfi_wrdata_en_pn (phy_wrat_integer_offset_1 is wrat_integer_offset) is determined by comparing the integer portions of phy_wrat and rg_phy_wrat, and dfi_wrdata_en_pn is adjusted in time.

wrdataen n is dfi wrdata en pn with the start phase 0; wrlat_integer of the first o_cmd_wr1 is 4; wrlat_integer for the 2 nd o_cmd_wr1 is 5; wrlat_integer for the 4 th o_cmd_wr1 is 4. When the fractional part accumulation generates a carry, we need to pull wr_data_en_n down by 1 dfi clock (delay_value in the figure is x).

The dfi_wrdata_en_pn is controlled by the later modules by synchronously storing carry information, interval offset into fifo. The method comprises the following steps: storing 2' b1x into fifo when it is detected that the integer part of the interval from the write command to dfi_wrdata_en_pn carries; conversely, the dynamic register phy_wrlat_integer_offset_1_d0.

wrlat_phase_offset_h_fifo [31:0], wrlat_phase_offset_l_fifo [31:0] are used to dynamically shift the fractional portion of the interval (i.e., the start phase) that registers the write command to dfi_wrdata_en_pn. The values corresponding to the 1 st to 8 th o_cmd_wr1 are 3, 0, 1, 2, 3, 0; the values corresponding to the 1 st to 3 th and 8 th o_cmd_wr1 and the synchronously calculated value (the decimal part of phy_wrlat_d0) remain identical; the values corresponding to the 4 th-7 th o_cmd_wr1 lead the synchronously calculated value by 1 clock.

The integer portion of the interval of the write command to dfi_wrdata_en_pn carries over by 1 dfi clock pulling wrdata_en_n low, and the integer portion carries back from carry over to no carry over by 1 dfi clock. Therefore, the starting phase of dfi_wrdata_en_pn needs to be adjusted in time according to the carry situation.

The dfi_wrdata_en_pn is recovered by synchronizing the adjusted starting phase to fifo for later modules. Specifically, the integer portion of the interval from the write command to dfi_wrdata_en_pn is detected to be in the following state: from carry-back to carry-not-enter-again-carry-not

(select_cur_phy_wrlat is high) dynamically stores the starting phase information (the fractional part of phy_wrlat) that is 1 dfi clock relatively advanced into fifo; conversely, the synchronously calculated value (the fractional part of phy_wrlat_d0) is dynamically registered.

wrat_phase_offset_h_fifo [31:0], wrat_phase_offset_l_fifo [31:0], and the like remain synchronized with cmd_wr1_d0; it needs to beat 1 to synchronize with o_cmd_wr1 (the command pulse input to the command synchronous stretching and delay processing module 1312). The o_cmd_act1 locks the integral part of the interval from the first write command to dfi_wrdata_en_pn at the moment, and realizes synchronous reading of the cache.

The design principle of the command synchronous stretching and delay processing module 1312 is as follows:

the DFI write data channel enable signal wr_en0 (wrdata_en_valid for generating the DFI write channel) is obtained by synchronous stretching with a 0 delay (the delay of the write command to dfi_wrdata_en_pn is configured to be 0) corresponding to the write command (pulse signal). That is, the pulse signal is stretched into 8 DFI clocks (BL 32 and ratio are 1:2), 4 DFI clocks (BL 32 and ratio are 1:4, BL16 and ratio are 1:2), and 2 DFI clocks (BL 16 and ratio are 1:4) according to the configured register information.

FIG. 8 is a schematic diagram illustrating the control principle of the wrata_en_valid of the dfi write channel in an embodiment of the present application.

wrdata_en_valid is the channel associated indication signal of dfi_wrdata_en_pn when the start phase is 0, and is used together with the start phase information to realize control of dfi_wrdata_en_pn.

As shown in fig. 8, the 0-delayed wr_en0 information is dynamically stored by writing an array fifo of 32bits in real time (fifo < = { fifo [30:0], wr_en0 }). fifo [ n ] is the wr_en0 delay n+1 dfi_clk (i.e., the delay of the write command to dfi_wrdata_en_pn is n+1).

When the fractional part of tccd or other similar parameter is not 0, irregular intervals will occur for cmd_wr1, and control of wrdata_en_valid above cannot be achieved through static n. The intermediate value is dynamically adjusted by the pointer calculation module, and the irregular interval is supported by dynamically cutting the pointer. The method comprises the following steps:

1. When wrdat_integer_offset [1] above is detected to be high, wrdata_en_valid is pulled low eliminating the extra high introduced by the intermediate transient.

2. fifo [ wrat_integer+wrat_integer_offset [0] -5'd1] is the wren 0 delay n/n+1 dfi_clk (n > 0).

3. Wrata_en_valid is obtained by mux (mixing) wren 0 and fifo [ wrat_integer+wrat_integer_offset [0] -5'd1] when wrat_integer_offset [1] is low, depending on whether the configured delay value is 0.

The initial phase support of dfi_wrdata_en_pn can be configured, and the implementation principle is shown in fig. 9. Fig. 9 is a schematic diagram showing the start phase control principle of DFI write channel dfi_wrdata_en_pn at ratio 4 in an embodiment of the present application.

As shown in fig. 9, dfi_wren_delay (from the phase information shift register) is used to specify the start phase (dfi_wren_delay [0] is only valid when phase 2).

By beating the above wrata_en_valid 1 beat, the state of wrata_en_valid is extended by 1 dfi_clk. Dfi_wrdata_en_pn is generated from the current dfi_wren_delay by mux for wrdata_en_valid and wrdata_en_valid_d0.

The control principle of the start Phase of the dfi_wrdata_en_pn of the dfi write channel at the ratio 2 is consistent with that of Phase4, and the description is omitted.

The schematic structure of the DFI command and data path generic controller of the present application, the read-write flow steps performed thereby, and the specific operations in the steps thereof have been described. As will be clearly understood from the foregoing, the present application has at least the following advantages:

in general, the scheme of the application realizes arbitrary configuration of the support command interval by calculating the command interval in real time; the key information is dynamically accessed, so that less resources are consumed, and meanwhile, any configuration of relevant parameters of the DFI specification is supported.

In particular, the method comprises the steps of,

1) 4-6, control of the initial phase of the command channel is achieved by calculating the initial phase of the command in real time and buffering key information in 2 beats and looking up the table in flow, a solution supporting random configuration of relevant parameters of the initial phase of the command channel of the dfi interface is provided, and resources are consumed less.

2) As shown in fig. 7, the integer part offset and the fractional part of the interval of the write command to dfi_wrdata_en_pn are calculated in real time; calculating an integer part offset and a fractional part of the interval from the write command to dfi_wrdata_wn in real time; calculating an integer part offset and a decimal part of the interval from the read command to dfi_rddata_en_pn in real time; further, as shown in fig. 8, the relevant channel associated indication signals with the initial phase of 0 are synchronously generated, and as shown in fig. 9, control over dfi_wrdata_en_pn, dfi_wrdata_wn, dfi_rddata_en_pn, dfi_wrdata_cs_pn and dfi_rddata_cs_pn is finally realized. The method can provide a solution supporting random configuration of relevant parameters of the interval of the wifi interface read/write channel, consumes less resources, has strong scheme universality and can be analogized to control of other channels of the wifi interface.

3) As shown in fig. 7, key information is stored by performing shift buffering on carry information, interval offset information and initial phase information based on dynamic acquisition for eliminating intermediate error transients, and synchronous output of the integral offset and the decimal part of the relevant interval of the read-write channel when supporting arbitrary configuration of a relevant register is realized by the pointer calculation module and based on a pointer dynamic adjustment mechanism as shown in fig. 8, and finally control of the relevant associated control signal is realized. That is, the solution for realizing any delay of the specific target signal after the key information is shifted and cached and synchronously output in the specific scene is provided, the consumed resources are less, the universality of the solution is strong, and the conventional general fifo which consumes much more resources is not needed to be used.

Although many english abbreviations and english terms are used in the description of the above embodiments, it should be understood that the english abbreviations and english terms are well known in the art of data storage design and are also commonly used in data storage design, and therefore, there is no place for those skilled in the art to understand or understand these terms when reading the above description of the present application.

While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be understood by those of ordinary skill in the relevant art(s) that various changes in form and details may be made therein without departing from the spirit and scope of the present application as defined by the following claims. Thus, the breadth and scope of the present application as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A DFI command and data path generic controller, comprising:

2. The DFI command and data path generic controller according to claim 1, wherein the specifying relevant parameters of the DFI protocol according to the received externally configured register information comprises: and selecting device type, ratio of DFI_CLK and TCK, BL16/BL32, bank group/8B/16B mode and interval parameters among the commands according to the register information.

3. The DFI command and data path generic controller of claim 1, wherein the command path control module is further configured to calculate a starting phase of the DFI command and drive dfi_cs_pn and dfi_address_pn according to the input command payload, command valid indication, 1T/2T type;

where dfi_cs_pn is used to select the rank of each channel, and dfi_address_pn indicates the command payload of each channel.

4. The DFI command and data path generic controller of claim 1, the write path module comprising:

a preprocessing module, wherein the preprocessing module comprises:

the command synchronous stretching and delay processing module is configured to stretch a write command pulse according to the configuration information, and store the stretched write command pulse into the shift register to be used for generating valid indication signals for controlling dfi_wrdata_en_pn and dfi_wrdata_wn;

The carry judging and caching module is configured to dynamically calculate whether carry occurs at intervals corresponding to each write command according to the configuration information, and store carry information into the carry information shift register to be used for adjusting intervals from the write command to dfi_wrdata_en_pn and intervals from the write command to dfi_wrdata_wn;

the initial phase calculation and buffer module is configured to calculate initial phase of dfi_wrdata_en_pn/dfi_wrdata_wn and store initial phase information into a phase information shift register to support an interval configurable function;

the pointer calculation module is configured to control the carry information shift register and the phase information shift register to output data so as to support an interval configurable function, and further assist in controlling dfi_wrdata_en_pn/dfi_wrdata_wn; and

a write enable write data write chip select control module configured to select to directly output a command broadening signal or delay a specific beat to output the command broadening signal according to the configuration information and finally control dfi_wrdata_en_pn/dfi_wrdata_wn, and control dfi_wrdata_cs_pn according to the configuration information and dfi_wrdata_en_pn;

wherein dfi_wrdata_en_pn specifies whether write data channel n is enabled, dfi_wrdata_wn specifies data on write data channel n, and dfi_wrdata_cs_pn specifies the chip to which write data channel n corresponds.

5. The DFI command and data path generic controller according to claim 4, wherein the read data path module includes a preprocessing module, a read enable read chip select control module, and a read data control module;

the preprocessing module of the read data channel module is identical to the preprocessing module of the write data channel module in structure, and only performs read data control;

the read-enabled chip selection control module is configured to select to directly use a corresponding broadening signal or delay a specific DFI clock for the corresponding broadening signal according to configuration interval information and carry information so as to obtain rddata_en_valid respectively;

the read data control module is configured to calculate the initial phase of read data by looking up a table of the input dfi_rddata_valid_wn, and align and output data returned by the PHY according to the initial phase of the read data;

where rddata_en_valid is the channel indication signal of dfi_rddata_en_pn when the start phase is 0, dfi_rddata_valid_wn is a data valid indication of read data channel n, and dfi_rddata_en_pn is a data valid indication specifying whether read data channel n is enabled.

6. A method of write operation for a DFI command and data path generic controller, comprising:

2) Receiving an external command and data to be written;

8) Executing the initial phase control of the write enable/write chip select/write data;

wherein dfi_wrdata_en_pn is a value specifying whether write data channel n is enabled; dfi_wrdata_wn specifies the data on write data channel n; wrlat_integer_offset is the offset of the integer portion of the interval of the write command to dfi_wrdata_en_pn; wrlat_phase_offset is the fractional part of the interval of the write command to dfi_wrdata_en_pn; wrcmd2data_integer_offset is the offset of the integer part of the interval of the write command to dfi_wrdata_wn; wrcmd2data_phase_offset is the fractional part of the interval of the write command to dfi_wrdata_wn; wrdata_en_valid is the channel indication signal of dfi_wrdata_en_pn when the start phase is 0.

7. The write operation method according to claim 6, wherein step 3), step 5) and step 6) of the write operation method are performed in parallel.

8. A method of read operation for a DFI command and data path generic controller, comprising:

2) Receiving an external command;

8) Performing a start phase control of the read enable/read chip select;

9) Performing initial phase detection of read data; and

10 After aligning the read data.

9. The method of read operation of claim 8, wherein steps 3), 5) and 6) of the method of read operation are performed in parallel;

where dfi_rddata_en_pn is a value specifying whether read data channel n is enabled; rdlat_integer_offset is the offset of the integer portion of the interval of the read command to dfi_rddata_en_pn; rdlat_phase_offset is the fractional part of the interval from the read command to dfi_rddata_en_pn; rddata_en_valid is the channel indication signal of dfi_rddata_en_pn when the start phase is 0.