CN115932414A - Three-in-one sensor of in-ear earphone - Google Patents

Three-in-one sensor of in-ear earphone Download PDF

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CN115932414A
CN115932414A CN202211616911.8A CN202211616911A CN115932414A CN 115932414 A CN115932414 A CN 115932414A CN 202211616911 A CN202211616911 A CN 202211616911A CN 115932414 A CN115932414 A CN 115932414A
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microprocessor
sensor
substrate
delay chain
bare chip
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黄孙峰
周其伟
吴敏
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Nanjing Pairui Semiconductor Co ltd
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Wuxi Pairui Semiconductor Co ltd
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Abstract

The invention discloses a three-in-one sensor of an in-ear earphone in the technical field of in-ear earphones, which comprises: a substrate; bare chip, bare chip sets up the top of base plate, bare chip includes differential delay chain, microprocessor and power and clock management unit, differential delay chain with microprocessor electric connection, microprocessor with power and clock management unit electric connection, the top edge of base plate is provided with pin frame, still includes the pin, the pin passes through pin frame sets up the top of base plate, this kind of in-ear earphone's trinity sensor through a high stable internal reference discharge circuit, will carry out the processing of making absolute relatively diffusion time, and then quantizes the discharge circuit that outside awaits measuring electric capacity and internal reference resistance and constitute, realizes the multichannel capacitance measurement of high speed, low-power consumption.

Description

一种入耳式耳机的三合一传感器A three-in-one sensor for in-ear headphones

技术领域technical field

本发明涉及入耳式耳机技术领域,具体为一种入耳式耳机的三合一传感器。The invention relates to the technical field of in-ear earphones, in particular to a three-in-one sensor for in-ear earphones.

背景技术Background technique

入耳式耳机的交互方式,主要包括滑动控制和压感触控。The interaction methods of in-ear headphones mainly include sliding control and pressure-sensitive touch.

滑动控制主要基于使用者手指从极板A向板B平移过程中引起的电容值变化进行判断,或者是相反方向的移动,如图7a所示,电容式滑动控制的原理简单、实施方便、功耗极低,但极易受到外部环境因素的干扰,尤其是雨雾天气、汗水,或者是其它人体部位引起的误操作,从电路角度来看,电容测量需要通过模拟-数字转换器(ADC)进行采样和微处理器(Processor)进行处理,其主要功能模块如图7b所示。Sliding control is mainly based on the judgment of the change in capacitance value caused by the translation of the user's finger from plate A to plate B, or the movement in the opposite direction. As shown in Figure 7a, the principle of capacitive sliding control is simple, easy to implement, and functional. The power consumption is extremely low, but it is very susceptible to interference from external environmental factors, especially misoperation caused by rain, fog, sweat, or other human body parts. From the perspective of the circuit, capacitance measurement needs to be performed through an analog-to-digital converter (ADC). Sampling and processing by a microprocessor (Processor), and its main functional modules are shown in Figure 7b.

压感触控主要采用压阻应变片原理,通过柔性材料或MEMS技术实现前端敏感元件C,一般为惠斯通电桥,再通过后端调理电路D完成采样和数字化处理,如图8a所示,压阻应变片式压感触控的原理非常成熟,在称重领域有数十年的应用历史。但其缺点同样十分明显:加工精度,包括尺寸精度和均匀性非常依赖于设备,导致一致性差异较大;安装工艺,尤其是焊接胶安装时胶水溢出导致应变片失效;受柔性材料的特性影响,温度范围相对较窄,零度以下性能下降较为严重;受MEMS工艺特性的影响,产品的抗跌落较差,无法使用超声波洗板;至少需要一颗敏感前端、一颗后端调理芯片,方案的PCB尺寸较大;方案的线性度回归系数受材料、结构、安装等影响相对严重,一般低于97%;该方案的系统功耗严重受制于模拟-数字转换器的设计,典型值为毫安(mA)等级,压阻应变片,或典型惠斯通电桥全桥结构如图8b所示,基于惠斯通电桥的压感触控系统功能模块如图8c所示。Pressure-sensitive touch mainly adopts the principle of piezoresistive strain gauges. The front-end sensitive element C is realized by flexible materials or MEMS technology, usually a Wheatstone bridge, and then the sampling and digital processing are completed through the back-end conditioning circuit D, as shown in Figure 8a. The principle of strain gauge pressure sensitive touch is very mature and has been applied in the field of weighing for decades. But its shortcomings are also very obvious: processing accuracy, including dimensional accuracy and uniformity, is very dependent on equipment, resulting in large differences in consistency; installation process, especially glue overflow during installation with welding glue leads to failure of strain gauges; affected by the characteristics of flexible materials , the temperature range is relatively narrow, and the performance drops below zero. Affected by the characteristics of the MEMS process, the product’s drop resistance is poor, and ultrasonic cleaning cannot be used; at least one sensitive front-end and one back-end conditioning chip are required. The PCB size is large; the linearity regression coefficient of the solution is relatively seriously affected by materials, structure, installation, etc., and is generally lower than 97%; the system power consumption of the solution is severely restricted by the design of the analog-to-digital converter, and the typical value is mA (mA) level, piezoresistive strain gauges, or a typical Wheatstone bridge full bridge structure is shown in Figure 8b, and the functional modules of the piezo-sensitive touch system based on the Wheatstone bridge are shown in Figure 8c.

电容式佩戴检测的原理与电容式滑动控制雷同。但只需一颗电容极板,即可感知耳机是否处于佩戴状态。The principle of capacitive wearing detection is the same as that of capacitive sliding control. But only one capacitive plate is needed to sense whether the earphone is in the wearing state.

综上所述,为了在入耳式耳机中实现电容式佩戴检测、电容式滑动控制以及压感触控三种人机交互功能,这些功能对于入耳式耳机的功耗控制以及用户体验非常关键,现有主流方案至少需要以下3-4颗器件(芯片):多通道电容测量芯片:用于电容式佩戴检测、电容式滑动控制;压阻应变的敏感前端:用于感知用户操作时的压力输入行为;压阻应变的后端调理:用于对压力输入进行采样和处理;外部或内部(电容测量芯片或压阻应变后端调理芯片内置)微处理器:用于信号处理以上三种功能所需的芯片组如图9所示,现有的入耳式耳机的三合一传感器存在着电容测量速度较慢,功耗较高的问题To sum up, in order to realize the three human-computer interaction functions of capacitive wearing detection, capacitive sliding control and pressure-sensitive touch in the earphone, these functions are very important for the power consumption control and user experience of the earphone. The mainstream solution requires at least the following 3-4 devices (chips): multi-channel capacitive measurement chip: used for capacitive wearing detection, capacitive sliding control; sensitive front end of piezoresistive strain: used to sense the pressure input behavior of the user during operation; Back-end conditioning of piezoresistive strain: used to sample and process pressure input; external or internal (built-in capacitance measurement chip or piezoresistive strain back-end conditioning chip) microprocessor: used for signal processing required by the above three functions The chip set is shown in Figure 9. The three-in-one sensor of the existing in-ear earphones has the problems of slow capacitance measurement speed and high power consumption.

发明内容Contents of the invention

本发明的目的在于提供一种入耳式耳机的三合一传感器,以解决上述背景技术中提出的现有的入耳式耳机的三合一传感器存在着电容测量速度较慢,功耗较高的问题。The object of the present invention is to provide a three-in-one sensor for in-ear earphones, to solve the problems of relatively slow capacitance measurement speed and high power consumption in the existing three-in-one sensor for in-ear earphones proposed in the above-mentioned background technology .

为实现上述目的,本发明提供如下技术方案:一种入耳式耳机的三合一传感器,包括:In order to achieve the above object, the present invention provides the following technical solutions: a three-in-one sensor for in-ear earphones, comprising:

基板;Substrate;

裸片,所述裸片设置在所述基板的顶部,所述裸片包括差分延迟链、微处理器和电源与时钟管理单元,所述差分延迟链与所述微处理器电性连接,所述微处理器与所述电源与时钟管理单元电性连接。a die, the die is arranged on the top of the substrate, the die includes a differential delay chain, a microprocessor, and a power and clock management unit, the differential delay chain is electrically connected to the microprocessor, the The microprocessor is electrically connected with the power supply and clock management unit.

优选的,所述基板的顶部边缘处设置有引脚框架。Preferably, a lead frame is provided at the top edge of the substrate.

优选的,还包括引脚,所述引脚通过所述引脚框架设置在所述基板的顶部。Preferably, pins are also included, and the pins are arranged on the top of the substrate through the lead frame.

优选的,所述裸片的顶部边缘处均匀设置有连接键,所述连接键上的顶部设置有导线,所述导线远离所述裸片的一端与所述引脚相连接。Preferably, connection keys are uniformly arranged on the top edge of the bare chip, and wires are arranged on the top of the connection keys, and the ends of the wires away from the die are connected to the pins.

优选的,所述裸片还包括内部放电电路、存储区和接口电路;Preferably, the bare chip also includes an internal discharge circuit, a storage area and an interface circuit;

所述内部放电电路与所述差分延迟链电性连接;The internal discharge circuit is electrically connected to the differential delay chain;

所述存储区与所述微处理器电性连接;The storage area is electrically connected to the microprocessor;

所述接口电路与所述微处理器电性连接。The interface circuit is electrically connected with the microprocessor.

优选的,还包括封装塑体,所述封装塑体设置在所述基板的顶部,所述封装塑体覆盖在所述裸片与所述引脚的外侧。Preferably, an encapsulation plastic body is also included, the encapsulation plastic body is arranged on the top of the substrate, and the encapsulation plastic body covers the outside of the die and the pins.

与现有技术相比,本发明的有益效果是:该种入耳式耳机的三合一传感器,通过一个高稳定的内部参考放电电路,将相对扩散时间进行绝对化处理,进而对外部待测电容与内部参考电阻组成的放电电路进行量化,实现高速、低功耗的多通道电容测量。Compared with the prior art, the beneficial effect of the present invention is: the three-in-one sensor of the earphone, through a highly stable internal reference discharge circuit, absolutizes the relative diffusion time, and then the external capacitance to be measured The discharge circuit composed of the internal reference resistor is quantified to realize high-speed, low-power multi-channel capacitance measurement.

附图说明Description of drawings

图1为本发明结构示意图;Fig. 1 is a structural representation of the present invention;

图2为本发明侧视示意图;Fig. 2 is a schematic side view of the present invention;

图3为本发明绝对量化处理系统框图;Fig. 3 is a block diagram of the absolute quantization processing system of the present invention;

图4为本发明差分延迟链电路相对量化离子扩散时间的流程图;Fig. 4 is the flowchart of relative quantization ion diffusion time of differential delay chain circuit of the present invention;

图5为本发明佩戴、滑动、压感触控三合一示意框图;Fig. 5 is a three-in-one schematic block diagram of wearing, sliding and pressure-sensitive touch according to the present invention;

图6为本发明差分延迟链单链示意图;6 is a schematic diagram of a single chain of a differential delay chain in the present invention;

图7为本发明电容式滑动控制和电容测量电路的主要功能模块示意图;7 is a schematic diagram of the main functional modules of the capacitive sliding control and capacitance measuring circuit of the present invention;

图8为本发明压阻应变片式压感触控、惠斯通全桥压阻应变片和压感触控系统功能示意框图;Fig. 8 is a functional block diagram of piezoresistive strain gauge type pressure-sensitive touch, Wheatstone full-bridge piezoresistive strain gauge and pressure-sensitive touch system of the present invention;

图9为本发明电容佩戴、滑动控制以及压感触控三种功能的芯片组示意框图。FIG. 9 is a schematic block diagram of a chipset with three functions of capacitive wearing, sliding control and pressure-sensitive touch according to the present invention.

图中:100基板、200裸片、210连接键、220导线、300引脚、400封装塑体。In the figure: 100 substrates, 200 bare chips, 210 connection keys, 220 wires, 300 pins, and 400 packaging plastic bodies.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

本发明提供一种入耳式耳机的三合一传感器,涉及电容佩戴、滑动控制以及压感触控三种功能的三合一的单芯片方案,以应力、应变作用在硅衬底上对N型以及P型沟槽离子扩散速度的影响,通过差分延迟链进行相对高精度的测量(数百皮秒等级),进而在后端处理器中完成应力、应变——相对扩散时间的线性化处理,得出用户输入的应力数值;此外,通过一个高稳定的内部参考放电电路,将相对扩散时间进行绝对化处理,进而对外部待测电容与内部参考电阻组成的放电电路进行量化,实现高速、低功耗的多通道电容测量,相比当前的主流方案,本申请涉及的单芯片方案至少具备以下优势:The invention provides a three-in-one sensor for in-ear earphones, which involves a three-in-one single-chip solution with three functions of capacitive wearing, sliding control, and pressure-sensitive touch. The impact of the ion diffusion velocity in the P-type trench is relatively high-precision measurement (hundreds of picoseconds) through the differential delay chain, and then the stress, strain-relative diffusion time linearization process is completed in the back-end processor, and the In addition, through a highly stable internal reference discharge circuit, the relative diffusion time is absolutized, and then the discharge circuit composed of the external capacitor to be measured and the internal reference resistance is quantified to achieve high-speed, low-power Compared with the current mainstream solutions, the single-chip solution involved in this application has at least the following advantages:

单芯片:PCB尺寸缩小60-90%;Single chip: PCB size reduced by 60-90%;

低功耗:整体功耗从毫安(mA)缩小至数十微安(μA),减少90%以上;Low power consumption: the overall power consumption is reduced from milliamps (mA) to tens of microamps (μA), reducing more than 90%;

高可靠:通过标准CMOS工艺生产,无需柔性材料压阻应变计所需的涂层工艺,具备更高的可靠性和稳定性;High reliability: produced by standard CMOS process, without the coating process required for flexible material piezoresistive strain gauges, with higher reliability and stability;

高性能:温度特性稳定,温度范围更宽(-40至85℃)。此外,线性度回归系数最高可达99.91%;High performance: stable temperature characteristics and wider temperature range (-40 to 85°C). In addition, the linearity regression coefficient can reach up to 99.91%;

成本更加可控;Costs are more controllable;

请参阅图1,包括:基板100、裸片200、引脚300和封装塑体400;Please refer to FIG. 1 , including: a substrate 100 , a bare chip 200 , pins 300 and a package plastic body 400 ;

基板100的顶部边缘处设置有引脚框架,裸片200设置在基板100的顶部,裸片200包括差分延迟链、微处理器和电源与时钟管理单元,差分延迟链与微处理器电性连接,微处理器与电源与时钟管理单元电性连接,裸片200的顶部边缘处均匀设置有连接键210,连接键210上的顶部设置有导线220,导线220远离裸片200的一端与引脚300相连接,裸片200还包括内部放电电路、存储区和接口电路,内部放电电路与差分延迟链电性连接,存储区与微处理器电性连接,接口电路与微处理器电性连接,引脚300通过引脚框架设置在基板100的顶部,封装塑体400设置在基板100的顶部,封装塑体400覆盖在裸片200与引脚300的外侧;A lead frame is arranged at the top edge of the substrate 100, and a die 200 is arranged on the top of the substrate 100. The die 200 includes a differential delay chain, a microprocessor, and a power and clock management unit, and the differential delay chain is electrically connected to the microprocessor. , the microprocessor is electrically connected to the power supply and the clock management unit, the top edge of the bare chip 200 is evenly provided with connection keys 210, the top of the connection key 210 is provided with a wire 220, and the end of the wire 220 away from the bare chip 200 and the pin 300, the bare chip 200 also includes an internal discharge circuit, a storage area and an interface circuit, the internal discharge circuit is electrically connected to the differential delay chain, the storage area is electrically connected to the microprocessor, and the interface circuit is electrically connected to the microprocessor. The pin 300 is arranged on the top of the substrate 100 through the lead frame, the packaging plastic body 400 is arranged on the top of the substrate 100, and the packaging plastic body 400 covers the outside of the die 200 and the pin 300;

本申请中的差分延迟链阵列如图6所示,用于对硅衬底N型及P型沟槽离子扩散速度进行相对量化;The differential delay chain array in this application is shown in Figure 6, which is used for relative quantification of the ion diffusion speed of the N-type and P-type grooves of the silicon substrate;

用户输入的应力,经过耳机柄部的压感触控区域传递至芯片封装体,无论采用基板还是引线框架,应力均会集中作用于内部居中的裸片上,进而引起硅衬底的应变,图1为采用基板进行封装的示意图,图2为采用金属引线框架进行封装的示意图;The stress input by the user is transmitted to the chip package through the pressure-sensitive touch area of the handle of the earphone. Regardless of whether the substrate or the lead frame is used, the stress will be concentrated on the inner centered die, which will cause the strain of the silicon substrate, as shown in Figure 1. A schematic diagram of packaging with a substrate, and Figure 2 is a schematic diagram of packaging with a metal lead frame;

硅衬底的应变,引起离子扩散速度的变化,通过内置微处理器给出启动与停止信号,基于内部时钟分频来控制启动与停止信号之间的间隔,同时对信号通过的差分延迟链单元个数进行累计,对比不同应力、应变作用下的累计个数,即可对应力——离子扩散时间进行相对量化;The strain of the silicon substrate causes the change of ion diffusion speed. The start and stop signals are given by the built-in microprocessor, and the interval between the start and stop signals is controlled based on the frequency division of the internal clock. At the same time, the signal passes through the differential delay chain unit The number is accumulated, and the relative quantification of the stress-ion diffusion time can be carried out by comparing the accumulated number under different stress and strain;

具体工作流程如图4所示,The specific workflow is shown in Figure 4.

假定通过时钟分频后预设的时间为T,单位为皮秒,不受外部应力、应变作用下的累计延迟链单元个数为N,单位为个;Assume that the preset time after clock frequency division is T, and the unit is picoseconds, and the number of cumulative delay chain units not affected by external stress and strain is N, and the unit is one;

外部应力、应变作用下的累计延迟链单元个数为N’,单位为个;The number of cumulative delay chain units under the action of external stress and strain is N', and the unit is one;

通过对外部应力F与ΔT之间的关系函数进行线性化处理,可以通过ΔT得出外部应力的数值,其中,ΔT如下:By linearizing the relationship function between the external stress F and ΔT, the value of the external stress can be obtained through ΔT, where ΔT is as follows:

Figure BDA0004000478720000051
Figure BDA0004000478720000051

假定外部应力F1、F2对用测出的离子扩散时间差为ΔT1、ΔT2如下:Assuming that the external stress F1, F2 is ΔT1, ΔT2 for the measured ion diffusion time difference as follows:

F1→ΔT1 F 1 →ΔT 1

F2→ΔT2 F 2 →ΔT 2

通过两点校准可以得出外部应力F与ΔT之间的函数关系如下:Through two-point calibration, the functional relationship between the external stress F and ΔT can be obtained as follows:

Figure BDA0004000478720000061
Figure BDA0004000478720000061

Figure BDA0004000478720000062
Figure BDA0004000478720000062

其中k为一阶函数的斜率,无量纲,where k is the slope of the first-order function, dimensionless,

上述过程对应力、应变引起的硅衬底N沟槽及P沟槽的离子扩散时间进行了相对量化,如能对相对量化时间进行绝对化处理,即可对外部待测电容进行测量,其系统框图如图3所示;The above process has carried out relative quantification on the ion diffusion time of the N-channel and P-channel of the silicon substrate caused by stress and strain. If the relative quantification time can be processed absolutely, the external capacitance to be measured can be measured. The system The block diagram is shown in Figure 3;

假定内部参考放电电路为Rref和Cref,绝对放电时间常数为:Assuming the internal reference discharge circuit is Rref and Cref, the absolute discharge time constant is:

Ta=RrefxCref T a = R ref x C ref

测得的离子扩散相对时间可以绝对化处理为如下:The measured relative time of ion diffusion can be absoluteized as follows:

T=kTa=kx(Rref×Cref)T=kT a =kx(R ref ×C ref )

图3所示的片上系统,既能够测得传递至封装体上的应力、应变,也能够测得外部待测电容的容值,因而,通过这一核心方案——差分延迟链技术配合内部放电电路,可用于入耳式耳机的电容式佩戴检测、电容式滑动控制以及压感触控,如图5所示,对于空间尺寸、系统功耗资源越发紧缺的入耳式耳机而言,本申请涉及的基于差分延迟链的应力、电容融合传感器片上系统,以2mmx3mmx0.9mm的最大尺寸满足耳机的佩戴、滑动控制检测和压感触控功能,同时功耗仅为竞争方案的10%-20%。The system-on-chip shown in Figure 3 can not only measure the stress and strain transmitted to the package, but also measure the capacitance of the external capacitor to be measured. Therefore, through this core solution - differential delay chain technology with internal discharge The circuit can be used for capacitive wearing detection, capacitive sliding control and pressure-sensitive touch of in-ear earphones. The stress and capacitive fusion sensor system-on-a-chip of the differential delay chain, with a maximum size of 2mmx3mmx0.9mm, meets the functions of earphone wearing, sliding control detection and pressure-sensitive touch, while the power consumption is only 10%-20% of competing solutions.

虽然在上文中已经参考实施例对本发明进行了描述,然而在不脱离本发明的范围的情况下,可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是,只要不存在结构冲突,本发明所披露的实施例中的各项特征均可通过任意方式相互结合起来使用,在本说明书中未对这些组合的情况进行穷举性的描述仅仅是出于省略篇幅和节约资源的考虑。因此,本发明并不局限于文中公开的特定实施例,而是包括落入权利要求的范围内的所有技术方案。While the invention has been described above with reference to the embodiments, various modifications may be made thereto and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, as long as there is no structural conflict, the various features in the embodiments disclosed in the present invention can be used in combination with each other in any way, and the description of these combinations is not exhaustive in this specification only to show In consideration of omitting space and saving resources. Therefore, the present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (6)

1. The utility model provides a trinity sensor of in-ear earphone which characterized in that: the method comprises the following steps:
a substrate (100);
a die (200), the die (200) disposed on top of the substrate (100), the die (200) including a differential delay chain, a microprocessor, and a power and clock management unit, the differential delay chain electrically connected with the microprocessor, the microprocessor electrically connected with the power and clock management unit.
2. The three-in-one sensor for an in-ear headphone as recited in claim 1, wherein: a leadframe is disposed at a top edge of the substrate (100).
3. The three-in-one sensor for an in-ear headphone as defined in claim 2, wherein: also included are leads (300), the leads (300) being disposed on top of the substrate (100) through the lead frame.
4. The three-in-one sensor for an in-ear headphone as defined in claim 3, wherein: the top edge of the bare chip (200) is uniformly provided with connecting keys (210), the top of the connecting keys (210) is provided with a conducting wire (220), and one end of the conducting wire (220) far away from the bare chip (200) is connected with the pins (300).
5. The three-in-one sensor for an in-ear headphone as recited in claim 4, wherein: the die (200) further includes internal discharge circuitry, a memory region, and interface circuitry;
the internal discharge circuit is electrically connected with the differential delay chain;
the storage area is electrically connected with the microprocessor;
the interface circuit is electrically connected with the microprocessor.
6. The three-in-one sensor for an in-ear headphone as recited in claim 5, wherein: the packaging plastic body (400) is arranged on the top of the substrate (100), and the packaging plastic body (400) covers the bare chip (200) and the outer side of the pin (300).
CN202211616911.8A 2022-12-15 2022-12-15 Three-in-one sensor of in-ear earphone Pending CN115932414A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200073334A1 (en) * 2018-08-31 2020-03-05 Nxp B.V. Capaticance-to-digital converter
CN212848365U (en) * 2020-08-17 2021-03-30 南京鑫晟立博科技有限公司 DC converter and electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200073334A1 (en) * 2018-08-31 2020-03-05 Nxp B.V. Capaticance-to-digital converter
CN212848365U (en) * 2020-08-17 2021-03-30 南京鑫晟立博科技有限公司 DC converter and electronic device

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