CN115685664A - Hard mask and preparation method thereof - Google Patents
Hard mask and preparation method thereof Download PDFInfo
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- CN115685664A CN115685664A CN202110869289.0A CN202110869289A CN115685664A CN 115685664 A CN115685664 A CN 115685664A CN 202110869289 A CN202110869289 A CN 202110869289A CN 115685664 A CN115685664 A CN 115685664A
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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Abstract
The invention discloses a hard mask and a preparation method thereof, wherein the hard mask comprises a substrate and a graph setting layer, a first insulating layer is formed on the surface of the substrate, first graph line holes penetrating through the substrate and the first insulating layer are formed on the substrate and the first insulating layer, the graph setting layer is formed on the surface, far away from the substrate, of the first insulating layer, second graph line holes penetrating through are formed in the graph setting layer, the second graph line holes are communicated with the first graph line holes, a line width limiting layer is formed on the side wall of each second graph line hole, and the line width limiting layer in each second graph line hole limits the line width of a target graph. The line width limiting layer can reduce the line width of the line hole of the second pattern, and can reduce the line width of a photoetching pattern when a photoetching machine is adopted for photoetching, so that the requirement of chip design is met, the dependence on a more advanced photoetching machine is eliminated, and a large amount of equipment cost is saved. The invention also provides a preparation method of the hard mask, and the hard mask prepared by the preparation method has the beneficial effects.
Description
Technical Field
The invention belongs to the technical field of chip preparation, and particularly relates to a hard mask and a preparation method thereof.
Background
The Hard Mask (Hard Mask) is an inorganic thin film material produced by CVD (Chemical Vapor Deposition). The main components of the catalyst are TiN, siN and SiO 2 And so on. The hard mask is mainly applied to the chip preparation photoetching process, firstly, a photoresist image is transferred to the hard mask, then, the final pattern is etched and transferred to the substrate through the hard mask, and compared with a mode of directly transferring the photoresist, the hard mask plate can be repeatedly used for many times and has no pollution residue.
In the prior art, in the preparation process of the hard mask, the hard mask with the graph with the preset line width is directly etched by a DUV KrF photoetching machine, and then is etched by an etching machine and is formed at one step to obtain the graph with the preset line width, so that the line width of the graph is caused
The manufacture of the hard mask structure with the preset line width formed at one time by photoetching is limited by photoetching conditions and is too high in cost, so that the hard mask structure with the preset line width formed at one time by photoetching is difficult to popularize, for example, the light source of a DUV KrF photoetching machine in the photoetching conditions is 193nm, products with the line width of more than 193nm can be produced, and for products with the line width of less than 193nm, a more advanced DUV ArF photoetching machine or EUV photoetching machine is needed, but the cost of the more advanced DUV ArF or EUV photoetching machine is more than 1 hundred million dollars, the cost is too high, the cost of the photoetching machine cannot be borne for most enterprises, and the products with the smaller line width are seriously limited by photoetching technology.
However, due to the requirement of chip design, the line width of more and more chips is designed to be smaller than 190nm, the type of the lithography machine determines the minimum line width of the hard mask, and how to produce the hard mask with smaller line width based on the existing DUV KrF lithography machine is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention aims to solve the defects in the prior art and provides a hard mask and a preparation method thereof, which specifically comprise the following steps:
the invention provides a hard mask, comprising:
the circuit board comprises a substrate, wherein a first insulating layer is formed on the surface of the substrate, and a first pattern line hole penetrating through the substrate and the first insulating layer is formed in the substrate and the first insulating layer;
the pattern setting layer is formed on the surface, far away from the substrate, of the first insulating layer, and second pattern wire holes penetrating through the pattern setting layer are formed in the pattern setting layer;
the second pattern line hole is communicated with the first pattern line hole, a line width limiting layer is formed on the side wall of the second pattern line hole, and the line width limiting layer in the second pattern line hole limits the line width of a target pattern.
Further, a parameter control layer is formed on a sidewall of the first pattern line hole.
Further, the pattern setting layer is a silicon layer, and the line width limiting layer is a silicon dioxide layer.
Further, the substrate is a silicon substrate, and the parameter control layer is a silicon dioxide layer.
Further, the line width limiting layer and the parameter control layer are generated simultaneously.
Further, the line width of the second pattern line hole is smaller than or equal to the line width of the first pattern line hole.
Furthermore, a non-metal bump is formed on the surface, far away from the first insulating layer, of the pattern setting layer.
Further, the non-metallic substance bump is any one of silicon nitride or silicon dioxide.
Further, the thicknesses of the first insulating layer, the pattern setting layer and the substrate are sequentially increased.
Further, the thickness of the first insulating layer is 100nm to 1000nm; the thickness of the pattern setting layer is 3-10 um; the thickness of the substrate is 100 um-700 um.
The invention also provides a preparation method of the hard mask, which comprises the following steps:
providing a substrate, forming a first insulating layer on one surface of the substrate, and forming a pattern setting layer on the surface, far away from the substrate, of the first insulating layer;
forming a second pattern line hole penetrating through the pattern setting layer on the pattern setting layer;
forming a first pattern line hole penetrating through the substrate and the first insulating layer on the substrate and the first insulating layer; the first pattern line hole and the second pattern line hole are communicated with each other;
and forming a line width limiting layer on the side wall of the second pattern line hole to limit the line width of the target pattern.
Further, forming a first pattern line hole through the substrate and the first insulating layer on the substrate and the first insulating layer, includes:
etching the substrate to form a first part of a first pattern line hole;
and continuously etching the first insulating layer on the basis of the first part to form a second part of the first pattern line hole.
Further, the etching the substrate to form a first portion of the first pattern line hole includes:
the substrate is formed with a first portion of a first pattern line hole by dry etching.
Further, the step of continuously etching the first insulating layer on the basis of the first portion to form a second portion of the first pattern line hole includes:
and continuously etching the first insulating layer by acid cleaning on the basis of the first part to form a second part of the first pattern line hole.
Further, the forming a second pattern line hole penetrating through the pattern setting layer in the pattern setting layer includes:
and carrying out dry etching on the pattern setting layer to form a second pattern line hole.
Further, the forming of a first pattern line hole penetrating the substrate and the first insulating layer on the substrate and the first insulating layer includes:
exposing the surface of the substrate, which is far away from the first insulating layer, through deep ultraviolet to form a first pattern to be etched;
and sequentially etching the substrate and the first insulating layer through the first pattern to form a first pattern line hole.
Further, the forming a second pattern line hole penetrating through the pattern setting layer in the pattern setting layer includes:
carrying out deep ultraviolet exposure on the surface of the pattern setting layer, which is far away from the first insulating layer, so as to form a second pattern to be etched;
and etching the pattern setting layer through the second pattern to form a second pattern line hole.
Furthermore, the second pattern and the first pattern are symmetrically arranged, and the line width of the second pattern is smaller than or equal to the line width of the first pattern.
Further, the substrate is made of silicon, the first insulating layer is made of silicon dioxide, and the silicon dioxide is formed by directly oxidizing the silicon surface.
Furthermore, the material of the pattern setting layer is silicon.
Further, the forming of the line width limiting layer on the sidewall of the second pattern line hole includes:
and growing silicon on the silicon material side wall of the second pattern line hole by dry oxidation and/or wet oxidation to form the line width limiting layer.
Further, the forming of the line width limiting layer on the silicon material sidewall of the second pattern line hole by growing silicon through dry oxidation and/or wet oxidation includes:
the thickness of the formed line width limiting layer is controlled by controlling the oxidation parameters of the dry oxidation and/or the wet oxidation, and further the line width reduction degree of the second pattern line hole is controlled.
Further, the line width of the second pattern line hole is smaller than or equal to the line width of the first pattern line hole.
Further, a parameter control layer is formed on the side wall of the first pattern line hole on the substrate by silicon oxidation.
Furthermore, a non-metal bump is formed on the surface, far away from the first insulating layer, of the pattern setting layer.
Further, the non-metallic bump is any one of silicon nitride or silicon dioxide.
Compared with the prior art, the beneficial effects are as follows:
the hard mask provided by the invention is used for replacing photoresist in the chip preparation photoetching process, can be used for multiple times, and has no pollution residue;
secondly, the hard mask is designed into a structure of a substrate and a graph setting layer, a first insulating layer is formed on the surface of the substrate, a first graph line hole penetrating through the substrate and the first insulating layer is formed in the substrate, a second graph line hole penetrating through the graph setting layer is formed in the graph setting layer, the second graph line hole is communicated with the first graph line hole, and a photoetching channel in a chip preparation photoetching process is formed.
And finally, a line width limiting layer is formed on the side wall of the second pattern line hole, so that the line width of the second pattern line hole can be reduced, and the line width of a photoetching pattern can be reduced when a photoetching machine is adopted for photoetching, thereby meeting the requirement of chip design. Particularly, the DUV KrF photoetching machine with a 193nm light source can only produce products with line widths above 193nm, and the hard mask provided by the invention can produce products with line widths far smaller than 193nm, so that a more advanced DUV ArF photoetching machine or an EUV photoetching machine is not needed to be adopted, dependence on the DUV ArF photoetching machine or the EUV photoetching machine is eliminated, and a large amount of equipment cost is saved.
The invention also provides a preparation method of the hard mask, and the hard mask prepared by the preparation method has the beneficial effects.
Drawings
FIG. 1 is a schematic diagram of a hard mask according to an embodiment of the present invention;
fig. 2a to 2h are schematic flow structure diagrams of a method for manufacturing a hard mask according to an embodiment of the present invention.
Description of reference numerals: the circuit board comprises a substrate 10, a first insulating layer 11, a first pattern line hole 12, a pattern setting layer 20, a second pattern line hole 21, a line width limiting layer 30, a parameter control layer 40 and a nonmetal bump 22.
Detailed Description
The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to without contradiction.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a hard mask according to an embodiment of the present invention.
The invention provides a hard mask, comprising: a substrate 10 and a pattern arrangement layer 20.
The substrate 10 is an insulating substrate, and may include a base substrate in the field of semiconductor chips and/or superconductor chips, such as a sapphire substrate, a silicon carbide substrate, and the like, and in this embodiment, silicon is used as a substrate material.
A first insulating layer 11 is formed on the surface of the substrate 10, and the first insulating layer 11 and the substrate 10 may be formed physically or chemically. In this embodiment, the first insulating layer 11 is formed by a chemical method, and the silicon oxide layer formed by oxidizing the silicon substrate 10 is formed as the first insulating layer 11 by natural oxidation, dry oxidation, wet oxidation, or a combination of dry oxidation and wet oxidation. In other embodiments, a first insulating layer 11 with insulating properties may be directly added to the substrate 10 by physical means, such as attaching a layer of silicon carbide (where attaching is only an arrangement form, and is not limited to the attaching form, and in addition, silicon carbide is not limited to be used as the first insulating layer 11, and in other embodiments, silicon dioxide may be used to be directly attached, and any material with insulating properties may be used as the material of the first insulating layer 11).
A first pattern line hole 12 penetrating through the substrate 10 and the first insulating layer 11 is formed in the substrate 10 and the first insulating layer 11, in this embodiment, a parameter control layer 40 is formed on a side wall of the first pattern line hole 12, the parameter control layer 40 is made of silicon dioxide, and the parameter control layer 40 is generated by oxidizing a side wall of the first pattern line hole 12 in the substrate 10, which is made of silicon. In other embodiments, the parameter control layer 40 may not be provided, and the function of the parameter control layer 40 is to protect the substrate 10 from external factors, such as oxidation, corrosion, human damage, etc.
The material of the pattern setting layer 20 is silicon, and in other embodiments, a non-metal substance with insulating property may be used instead, and the non-metal substance is not easily oxidized in air. The pattern arrangement layer 20 is formed on the surface of the first insulating layer 11 far away from the substrate 10, and a second pattern wire hole 21 penetrating through the pattern arrangement layer 20 is formed on the pattern arrangement layer 20.
The second pattern line hole 21 is communicated with the first pattern line hole 12, specifically, the pattern shapes of the first pattern line hole 12 and the second pattern line hole 21 are the same, the first pattern line hole 12 and the second pattern line hole 21 are communicated in a superposed mode in position and are integrated, and when the photoetching machine is used in a later period, light of the photoetching machine can simultaneously pass through the first pattern line hole 12 and the second pattern line hole 21 to reach a substrate for chip manufacturing which needs photoetching.
A line width limiting layer 30 is formed on a sidewall of the second pattern line hole 21, the line width limiting layer 30 in the second pattern line hole 21 limits a line width of a target pattern, in this embodiment, the line width limiting layer 30 is made of silicon dioxide, the line width limiting layer 30 is a silicon dioxide layer formed by oxidizing the sidewall of the second pattern line hole 21 on the pattern setting layer 20 made of silicon, in this embodiment, the line width limiting layer 30 is formed by oxidizing the pattern setting layer 20 in a dry oxidation manner, a wet oxidation manner, or a combination manner of the dry oxidation and the wet oxidation manner.
The sidewalls of the second pattern line holes 21 are oxidized by a silicon dry oxidation method, and silicon dioxide having a thickness of 1.0X can be generated per consumption of 0.44X thickness of silicon according to a silicon oxidation theory. After oxidation, a certain thickness of silicon dioxide grows on the sidewall of the second pattern line hole 21, and the line width of the second pattern line hole 21 decreases. By using the method, the line width of the hole can be accurately controlled by controlling the thickness of the silicon dioxide, so that the aperture of the second graphic line hole 21 with smaller line width can be obtained, and the SOI hard mask with the line width of 20-200 nm can be obtained by using the method, so that the dependence on a high-grade photoetching machine is eliminated.
In actual practice, to accelerate efficiency, wet oxidation or a combination of dry and wet oxidation is used to oxidize silicon.
In this embodiment, the line width limiting layer 30 and the parameter control layer 40 are both generated simultaneously by the above method using silicon oxidation, so as to improve the production efficiency, and in the operation process, it is ensured that the line width of the second pattern line hole 21 is smaller than the line width of the first pattern line hole 12, so that the line width of the first pattern line hole 12 can accommodate a large amount of light sources of a lithography machine, and then the light sources are introduced into the first pattern line hole 12 with a small line width, thereby improving the lithography effect in the later chip manufacturing process. In other embodiments, the size relationship between the line width of the second pattern line hole 21 and the line width of the first pattern line hole 12 is not particularly limited.
In the later chip manufacturing process, the photoetching machine can be used for photoetching a photoetching pattern with the photoetching line width smaller than that of the photoetching machine by the hard mask provided by the embodiment in the photoetching process, so that in the actual production process, the photoetching pattern with the small line width can be photoetched without adopting a more advanced photoetching machine, and a large amount of cost can be saved.
A nonmetal bump 22 is formed on the surface of the pattern setting layer 20 away from the first insulating layer 11, where the nonmetal bump 22 is any one of silicon nitride or silicon dioxide, in this embodiment, silicon nitride is used as the nonmetal bump 22, and in a chip preparation process, the nonmetal bump 22 is used as a supporting point, when a film is plated, a hard mask is not attached to a substrate (not a substrate in a hard mask provided by the present invention, but a substrate of a chip in a chip preparation process, such as a sapphire substrate or a silicon substrate) and a certain distance is kept, where the distance is a height of the nonmetal bump 22. In other embodiments, silicon nitride or silicon dioxide is not limited, and non-metallic substances that are not easily oxidized may be used.
In the present embodiment, the thickness of the first insulating layer 11 is 100nm to 1000nm; the thickness of the pattern setting layer 20 is 3um to 10um; the thickness of the substrate 10 is 100 um-700 um, which is convenient for the process production.
As shown in fig. 2a to 2h, fig. 2a to 2h are schematic flow structure diagrams of a method for manufacturing a hard mask according to an embodiment of the present invention.
The invention also provides a preparation method of the hard mask, which comprises the following steps:
as shown in fig. 2a, a substrate 10 is provided, the substrate 10 is an insulating substrate, and may include a base substrate in the field of semiconductor chips and/or superconductor chips, such as a sapphire substrate, a silicon carbide substrate, etc., and in this embodiment, silicon is used as a substrate material.
A first insulating layer 11 is formed on one surface of the substrate 10, and a pattern setting layer 20 is formed on a surface of the first insulating layer 11 away from the substrate 10, in this embodiment, the material of the pattern setting layer 20 is silicon, and in other embodiments, a non-metal substance with insulating property may be used instead, and the non-metal substance is not easily oxidized in air.
A first insulating layer 11 is formed on the surface of the substrate 10, and the first insulating layer 11 and the substrate 10 may be formed physically or chemically. In this embodiment, the first insulating layer 11 is formed by a chemical method, and the silicon oxide layer formed by oxidizing the silicon substrate 10 is formed as the first insulating layer 11 by natural oxidation, dry oxidation, wet oxidation, or a combination of dry oxidation and wet oxidation. In other embodiments, a first insulating layer 11 with insulating properties may be added directly on the substrate 10 by physical means, such as attaching a layer of silicon carbide (where the attaching is only one arrangement form, and is not limited to the attaching form, and in addition, silicon carbide is not limited to be used as the first insulating layer 11, and in other embodiments, silicon dioxide may be used to be directly attached, and any material with insulating properties may be used as the material of the first insulating layer 11).
Forming a first pattern to be etched on the surface of the substrate 10 far away from the first insulating layer 11 through deep ultraviolet exposure, and performing deep ultraviolet exposure on the surface of the pattern setting layer 20 far away from the first insulating layer 11 to form a second pattern to be etched, wherein the second pattern and the first pattern are symmetrically arranged on opposite surfaces, and the line width of the second pattern is smaller than or equal to the line width of the first pattern (not shown in the first pattern and the second pattern).
As shown in fig. 2b, after the first pattern and the second pattern are formed, the second pattern is dry-etched with respect to the pattern-setting layer 20 to form a second pattern hole 21, and when the first insulating layer 11 is touched during etching, the etching is stopped, and the second pattern hole 21 is completely etched.
As shown in fig. 2c, after the etching of the second pattern line hole 21 is completed, the substrate 10 is dry etched to form a first portion of the first pattern line hole 12, and when the substrate is etched and touches the first insulating layer 11, the etching is stopped, and the etching of the first portion of the first pattern line hole 12 is completed.
As shown in fig. 2d, on the basis of the first portion of the first pattern line hole 12, the first insulating layer 11 is further continuously subjected to acid cleaning and etching to form a second portion of the first pattern line hole 12, the first portion and the second portion form a complete first pattern line hole 12, the first pattern line hole 12 and the second pattern line hole 21 are communicated with each other, in order to distinguish a boundary between the first pattern line hole 12 and the second pattern line hole 21, a dotted line is used for marking in fig. 2d as a boundary for distinguishing between the first pattern line hole 12 and the second pattern line hole 21, and an actual product does not have the dotted line, as shown in fig. 2 e.
When the first part of the first pattern line hole 12 is formed, the first insulating layer 11 serves as a barrier layer, etching is stopped immediately when the etching meets the first insulating layer 11, the pattern setting layer 20 can be well protected from being damaged, and similarly, when the second pattern line hole 21 is etched, the first insulating layer 11 serves as a barrier layer, the substrate 10 can be protected from being damaged, and after the etching of the first part of the first pattern line hole 12 and the second pattern line hole 21 are etched, the first insulating layer 11 made of silicon dioxide material is etched off to form the second part of the first pattern line hole 12, the substrate 10 and the pattern setting layer 20 cannot be damaged, so that etching precision can be improved, and yield can be improved.
As shown in fig. 2f, the line width limiting layer 30 is formed on the sidewall of the second pattern line hole 21 to limit the line width of the second pattern line hole 21, in this embodiment, the line width limiting layer 30 of silicon dioxide is formed by growing silicon on the sidewall of the second pattern line hole 21 on the pattern setting layer 20 of silicon material by dry oxidation and/or wet oxidation, and the thickness of the formed line width limiting layer 30 is controlled by controlling the oxidation parameters of the dry oxidation and/or wet oxidation, so as to control the line width reduction degree of the second pattern line hole 21.
The sidewalls of the second pattern line holes 21 were oxidized by a silicon dry oxidation method, and according to the silicon oxidation theory, silicon dioxide having a thickness of 1.0X was generated for every consumption of 0.44X thickness of silicon. After oxidation, silicon dioxide of a certain thickness grows in the second pattern line hole 21, and the line width of the second pattern line hole 21 decreases. By using the method, the thickness of the silicon dioxide can be controlled, so that the line width of the hole can be accurately controlled, and the aperture of the second pattern line hole 21 with smaller line width can be obtained.
As shown in fig. 2g, a parameter control layer 40 is formed on the sidewall of the first pattern line hole 12 on the substrate 10 made of silicon by silicon oxidation, the material of the parameter control layer 40 is silicon dioxide, in other embodiments, the parameter control layer 40 may not be provided, and the function of the parameter control layer 40 is to protect the substrate 10 from being interfered by external factors, such as oxidation, corrosion, artificial damage, and the like.
As shown in fig. 2h, a non-metallic bump 22 is formed on the surface of the pattern setting layer 20 away from the first insulating layer 11, where the non-metallic bump 22 is any one of silicon nitride and silicon dioxide, in this embodiment, silicon nitride is used as the non-metallic bump 22, and in a chip preparation process, the non-metallic bump 22 is used as a supporting point for a film deposition, and when the film deposition is performed, a certain distance is kept between a hard mask and a substrate (not a substrate in a hard mask provided by the present invention, but a substrate in a chip preparation process, such as a sapphire substrate or a silicon substrate, etc.), where the distance is the height of the non-metallic bump 22. In other embodiments, non-metal materials that do not readily oxidize may be used, without limitation, silicon nitride or silicon dioxide.
In other embodiments, the step of forming the non-metal bump 22 on the surface of the pattern arrangement layer 20 away from the first insulation layer 11 may be performed before the deep ultraviolet exposure is performed on the substrate 10 and the pattern arrangement layer 20, and the subsequent steps are the same as those in the above embodiments.
The hard mask provided by the invention is used for replacing photoresist in the chip preparation photoetching process, can be used for multiple times, and has no pollution residue;
secondly, the hard mask is designed into a structure of a substrate and a graph setting layer, a first insulating layer is formed on the surface of the substrate, a first graph line hole penetrating through the substrate and the first insulating layer is formed in the substrate, a second graph line hole penetrating through the graph setting layer is formed in the graph setting layer, the second graph line hole is communicated with the first graph line hole, and a photoetching channel in a chip preparation photoetching process is formed.
And finally, a line width limiting layer is formed on the side wall of the second pattern line hole, so that the line width of the second pattern line hole can be reduced, and the line width of a photoetching pattern can be reduced when a photoetching machine is adopted for photoetching, thereby meeting the requirement of chip design. Particularly, the DUV KrF photoetching machine with a 193nm light source can only produce products with line widths above 193nm, and the hard mask provided by the invention can produce products with line widths far smaller than 193nm, so that a more advanced DUV ArF photoetching machine or an EUV photoetching machine is not needed to be adopted, dependence on the DUV ArF photoetching machine or the EUV photoetching machine is eliminated, and a large amount of equipment cost is saved.
The invention also provides a preparation method of the hard mask, and the hard mask prepared by the preparation method has the beneficial effects.
The present invention has been described in detail with reference to the embodiments shown in the drawings, and it is therefore intended that the present invention not be limited to the exact forms and details shown and described, but that various changes and modifications can be made without departing from the spirit and scope of the invention.
Claims (26)
1. A hard mask, comprising:
a substrate (10), wherein a first insulating layer (11) is formed on the surface of the substrate (10), and a first pattern line hole (12) penetrating through the substrate (10) and the first insulating layer (11) is formed on the substrate (10) and the first insulating layer (11);
the pattern setting layer (20) is formed on the surface, far away from the substrate (10), of the first insulating layer (11), and a second pattern line hole (21) penetrating through the pattern setting layer (20) is formed in the pattern setting layer (20);
the second pattern line hole (21) is communicated with the first pattern line hole (12), a line width limiting layer (30) is formed on the side wall of the second pattern line hole (21), and the line width limiting layer (30) in the second pattern line hole (21) limits the line width of a target pattern.
2. The hard mask according to claim 1, wherein a parameter control layer (40) is formed on a sidewall of the first pattern line hole (12).
3. The hardmask of claim 2, wherein the pattern setting layer (20) is a silicon layer and the line width limiting layer (30) is a silicon dioxide layer.
4. The hard mask according to claim 3, wherein the substrate (10) is a silicon substrate and the parameter control layer (40) is a silicon dioxide layer.
5. The hard mask according to claim 4, wherein the line width limiting layer (30) and the parameter control layer (40) are generated simultaneously.
6. The hard mask according to claim 2, wherein the line width of the second pattern line hole (21) is smaller than or equal to the line width of the first pattern line hole (12).
7. The hardmask of claim 1, wherein the pattern providing layer (20) has a non-metallic bump (22) formed on a surface thereof remote from the first insulating layer (11).
8. The hard mask according to claim 7, wherein the bump (22) of non-metallic substance is any one of silicon nitride or silicon dioxide.
9. Hard mask according to claim 1, characterized in that the thickness of the first insulating layer (11), the pattern providing layer (20) and the substrate (10) increases in sequence.
10. The hardmask of claim 1, wherein the first insulating layer (11) has a thickness of 100nm to 1000nm; the thickness of the pattern setting layer (20) is 3-10 um; the thickness of the substrate (10) is 100 um-700 um.
11. A method for preparing a hard mask is characterized by comprising the following steps:
providing a substrate (10), forming a first insulating layer (11) on one surface of the substrate (10), and forming a pattern setting layer (20) on the surface, far away from the substrate (10), of the first insulating layer (11);
forming a second pattern line hole (21) penetrating through the pattern setting layer (20) on the pattern setting layer (20);
then forming a first pattern line hole (12) penetrating through the substrate (10) and the first insulating layer (11) on the substrate (10) and the first insulating layer (11); the first pattern line hole (12) and the second pattern line hole (21) are communicated with each other;
a line width limiting layer (30) is formed on a sidewall of the second pattern line hole (21) to limit a target pattern line width.
12. The method of manufacturing a hardmask according to claim 11, wherein forming a first pattern line hole (12) through the substrate (10) and the first insulating layer (11) on the substrate (10) and the first insulating layer (11) comprises:
etching the substrate (10) to form a first portion of a first pattern line hole (12);
and continuously etching the first insulating layer (11) on the basis of the first part to form a second part of the first pattern line hole (12).
13. The method of claim 12, wherein said etching said substrate (10) to form a first portion of a first pattern line hole (12) comprises:
the substrate (10) is dry etched to form a first portion of a first pattern line hole (12).
14. The method for preparing a hard mask according to claim 12, wherein said etching of said first insulating layer (11) to form a second portion of a first pattern line hole (12) is continued on the basis of said first portion, comprising:
and on the basis of the first part, continuously forming a second part of the first pattern line hole (12) on the first insulating layer (11) through acid pickling and etching.
15. The method for manufacturing a hard mask according to claim 11, wherein said forming a second pattern line hole (21) penetrating through said pattern setting layer (20) in said pattern setting layer (20) comprises:
and carrying out dry etching on the pattern setting layer (20) to form a second pattern line hole (21).
16. The method for manufacturing a hard mask according to claim 11, wherein said forming a first pattern line hole (12) through said substrate (10) and said first insulating layer (11) on said substrate (10) and said first insulating layer (11) comprises:
exposing the surface, far away from the first insulating layer (11), of the substrate (10) through deep ultraviolet to form a first pattern needing etching;
and sequentially etching the substrate (10) and the first insulating layer (11) through the first pattern to form a first pattern line hole (12).
17. The method for manufacturing a hard mask according to claim 16, wherein said forming a second pattern line hole (21) penetrating through said pattern setting layer (20) in said pattern setting layer (20) comprises:
carrying out deep ultraviolet exposure on the surface, far away from the first insulating layer (11), of the pattern setting layer (20) to form a second pattern to be etched;
and etching the pattern setting layer (20) through the second pattern to form a second pattern line hole (21).
18. The method as claimed in claim 17, wherein the second pattern is disposed symmetrically to the first pattern, and the line width of the second pattern is smaller than or equal to the line width of the first pattern.
19. The method according to claim 11, wherein the substrate (10) is silicon, the first insulating layer (11) is silicon dioxide, and the silicon dioxide is formed by oxidizing a silicon surface directly.
20. The method of claim 19, wherein the pattern setting layer (20) is made of silicon.
21. The method of fabricating a hard mask according to claim 20, wherein the forming of the line-width limiting layer (30) on the sidewall of the second pattern line hole (21) comprises:
the line-width limiting layer (30) is formed by growing silicon on the silicon material sidewall of the second pattern line hole (21) by dry oxidation and/or wet oxidation.
22. The method of fabricating a hardmask according to claim 21, wherein the forming the line-width limiting layer (30) by growing silicon on the silicon material sidewalls of the second pattern line holes (21) by dry oxidation and/or wet oxidation comprises:
the thickness of the formed line width limiting layer (30) is controlled by controlling the oxidation parameters of the dry oxidation and/or the wet oxidation, and further the line width reduction degree of the second pattern line hole (21) is controlled.
23. The method for manufacturing a hard mask according to claim 11, wherein the line width of said second pattern line hole (21) is smaller than or equal to the line width of said first pattern line hole (12).
24. The method of fabricating a hard mask according to claim 19, wherein the parameter control layer (40) is formed by silicon oxidation of sidewalls of the first pattern line holes (12) on the substrate (10).
25. The method of any one of claims 11 to 24, wherein a non-metal bump (22) is formed on a surface of the pattern-providing layer (20) remote from the first insulating layer (11).
26. The method for manufacturing a hard mask according to claim 25, wherein said bump (22) of a nonmetallic substance is any one of silicon nitride or silicon dioxide.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110869289.0A CN115685664A (en) | 2021-07-30 | 2021-07-30 | Hard mask and preparation method thereof |
| PCT/CN2022/107418 WO2023005845A1 (en) | 2021-07-30 | 2022-07-22 | Hard mask and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110869289.0A CN115685664A (en) | 2021-07-30 | 2021-07-30 | Hard mask and preparation method thereof |
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| CN115685664A true CN115685664A (en) | 2023-02-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110869289.0A Pending CN115685664A (en) | 2021-07-30 | 2021-07-30 | Hard mask and preparation method thereof |
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| WO (1) | WO2023005845A1 (en) |
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| KR20030050952A (en) * | 2001-12-20 | 2003-06-25 | 주식회사 하이닉스반도체 | Method of fabricating exposure mask for semiconductor manufacture |
| JP2004273689A (en) * | 2003-03-07 | 2004-09-30 | Sony Corp | Exposure mask, method for manufacturing the same and method for manufacturing semiconductor device |
| JP2005108938A (en) * | 2003-09-29 | 2005-04-21 | Sony Corp | Stencil mask and its manufacturing method, aligner and exposure method, and method for manufacturing electronic device |
| JP5332776B2 (en) * | 2009-03-18 | 2013-11-06 | 凸版印刷株式会社 | Method for manufacturing transfer mask |
| CN105159027B (en) * | 2015-07-31 | 2019-09-10 | 瑞声声学科技(深圳)有限公司 | Photomask structure and preparation method thereof suitable for MEMS microphone |
| CN215416266U (en) * | 2021-07-30 | 2022-01-04 | 合肥本源量子计算科技有限责任公司 | Hard mask |
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Address after: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, Hefei high tech Zone, Hefei City, Anhui Province Applicant after: Benyuan Quantum Computing Technology (Hefei) Co.,Ltd. Address before: 230088 6th floor, E2 building, phase II, innovation industrial park, 2800 innovation Avenue, Hefei high tech Zone, Hefei City, Anhui Province Applicant before: ORIGIN QUANTUM COMPUTING COMPANY, LIMITED, HEFEI |