CN115580225A - A heat dissipation structure for a concentrated photovoltaic cell substrate - Google Patents

Abstract

The present invention relates to the technical field of photovoltaic cell substrates, in particular to a heat dissipation structure for a concentrated photovoltaic cell substrate, including a chip, a bare substrate, a heat sink, and a second insulating layer. The bare substrate includes an etching layer and a bottom layer. One side of the etching layer is connected to the chip, the other side of the etching layer is fixedly connected to the bottom layer, the etching layer is provided with a fifth etching block, one side of the fifth etching block is connected to the chip, and the bottom layer is provided with a heat sink. The other side of the fifth etching block extends into the inside of the heat dissipation port, the lower part of the bottom layer is fixedly connected to the second insulating layer, the second insulating layer covers the fifth etching block, and the lower part of the bottom layer is connected to the second insulating layer. Radiator welding; the invention can insulate the chip and the radiator through the second insulating layer, avoiding the risk of electric shock caused by the radiator being charged, at the same time, reducing the heat dissipation path, improving the heat dissipation efficiency, and only one time between the bare substrate and the radiator The connection can be completed by welding, which simplifies the processing steps and improves the production efficiency.

Description

A heat dissipation structure for a concentrated photovoltaic cell substrate

technical field

The invention relates to the technical field of photovoltaic cell substrates, in particular to a heat dissipation structure for a concentrated photovoltaic cell substrate.

Background technique

Photovoltaic cells refer to devices that directly convert the sun's light energy into electrical energy. The full name is solar photovoltaic cells. Photovoltaic cells generally use polycrystalline silicon and monocrystalline silicon cells. Due to the limited supply capacity, the price of polysilicon in the international market has been rising all the way. Therefore, a new type of high-power concentrator battery has emerged. This battery has the advantages of high conversion rate, small battery footprint and less consumables. The typical example is gallium arsenide solar cells. GaAs solar cells have different crystallization methods. The chip is a conductive structure with negative electrodes on both sides and positive electrodes below the chip. Can generate high heat, so it needs to be used in conjunction with a heat sink.

Chinese patent CN115036383A discloses a gallium arsenide battery heat dissipation structure, including a gallium arsenide chip, a positive electrode of a power supply, a negative electrode of a power supply, and a heat sink. The gallium arsenide chip base surface, the gallium arsenide chip is connected to the copper foil circuit board through the positive electrode wire, the copper foil circuit board is connected to the positive electrode of the power supply, the copper foil circuit board is bonded to the base copper plate through the epoxy resin insulating and heat-conducting coating, and the base copper plate is another One side is connected to the heat sink through the ceramic copper-plated insulating heat-conducting coating. The ceramic copper-plated insulating heat-conducting layer is an insulator coated with copper on both sides of the ceramic. Both sides are soldered with tin, one side is welded to the basic copper plate, and the other side is welded to the radiator. Gallium arsenide The heat dissipation path of the chip is: gallium arsenide chip-basic copper plate-ceramic copper-plated insulating heat-conducting coating-radiator. Insulation properties between radiators.

To sum up, in the prior art, in order to maintain the insulation performance between the gallium arsenide chip and the heat sink, a ceramic copper-plated insulating heat-conducting coating is welded between the basic copper plate and the heat sink, and the ceramic double-sided copper-clad material is used. During processing, it is necessary to solder one side of the ceramic copper-plated insulating heat-conducting coating to the base copper plate, and then solder the other side of the ceramic copper-plated insulating heat-conducting coating to the radiator. This requires two steps of soldering to realize the basic copper plate and the base copper plate. The insulation between radiators requires a long processing cycle; at the same time, the ceramic copper-plated insulating and heat-conducting coating has a certain thickness, which will affect the heat conduction efficiency. Therefore, it is urgent to provide a heat dissipation structure for the substrate of the concentrated photovoltaic cell. The invention provides a photovoltaic cell substrate heat dissipation structure which can simplify the processing steps while maintaining the insulation performance.

Contents of the invention

In order to solve the above technical problems, the present invention provides a heat dissipation structure for a concentrated photovoltaic cell substrate.

To achieve the above object, the technical scheme of the present invention is as follows:

A concentrating photovoltaic cell substrate heat dissipation structure, including a chip, a bare substrate and a heat sink, the bare substrate includes an etching layer and a bottom layer, one side of the etching layer is connected to the chip, and the other side of the etching layer is connected to the chip. The bottom layer is fixed, the etching layer is provided with a fifth etching block, one side of the fifth etching block is connected to the chip, the bottom layer is provided with a heat dissipation port, and the other side of the fifth etching block extends Into the inside of the heat dissipation port, a second insulating layer is provided on the lower part of the bottom layer, the second insulating layer covers the fifth etching block, and the lower part of the bottom layer is welded to the heat sink.

Further, the second insulating layer is made of insulating ink, and the thickness of the second insulating layer is 0.5um.

Furthermore, the lower part of the etching layer is coated with insulating ink.

Furthermore, the lower part of the chip is set as the positive pole, the two ends of the chip are set as the negative pole, the fifth etching block is connected to the positive pole of the chip, and the etching layer is also connected to the negative pole of the chip.

Furthermore, it also includes a positive terminal seat and a negative terminal seat, the etching layer includes a first etching layer and a second etching layer, the first etching layer is connected to the negative terminal seat, and the second etching layer conduction with the positive terminal block.

Furthermore, the first etching layer includes a second etching block and a third etching block, and both the second etching block and the third etching block are connected to the negative terminal seat; the second etching layer A sixth etching block and a seventh etching block are included, both of the sixth etching block and the seventh etching block are connected to the positive terminal seat.

Furthermore, the negative electrode of the chip is connected to the first etching layer through several pins.

Furthermore, a bypass diode is further included, and the bypass diode is respectively connected in parallel with the positive terminal seat and the negative terminal seat through the etching layer.

Further, the first etching layer is also provided with a first etching block, and the second etching layer is also provided with a fourth etching block, and both the first etching block and the fourth etching block are connected with the bypass The diode conducts.

Furthermore, a first insulating layer is provided on the upper part of the etching layer, and the first etching block, the second etching block, the third etching block, the fourth etching block, and the fifth etching block , both the sixth etching block and the seventh etching block protrude from the first insulating layer.

Compared with prior art, the beneficial effect of the present invention is:

(1) One side of the etching layer of the present invention is connected to the chip, and the other side of the etching layer is fixedly connected to the bottom layer. The etching layer is provided with a fifth etching block. The other side of the fifth etching block can extend into the inside of the heat dissipation port. The lower side of the bottom layer is welded with the second insulating layer. The second insulating layer covers the fifth etching block. The lower side of the bottom layer is also welded with a radiator. The insulation layer abuts; the chip and the radiator can be insulated through the second insulation layer to avoid the risk of electric shock caused by the radiator being charged. At the same time, compared with the connection method using ceramic copper-plated insulating layer in the prior art, the present invention can reduce the heat dissipation path and improve the heat dissipation efficiency, and the connection between the bare substrate and the heat sink can be completed by only one welding, which simplifies the processing steps ,Increase productivity.

(2) The second insulating layer is made of insulating ink, and the thickness of the second insulating layer is only 0.5um. The heat of the positive electrode of the chip passes through the chip, the fifth etching block, the second insulating layer, and then to the radiator. The small second insulating layer is used for insulation, which can not only ensure the insulation effect, but also have a good heat conduction effect.

(3) The first etching block arranged on the top of the first etching layer can conduct with one end of the bypass diode, and the fourth etching block arranged on the top of the second etching layer can conduct with the other end of the bypass diode, so that the bypass diode and The positive terminal block and the negative terminal block are connected in parallel, and the parallel connection of bypass diodes can prevent photovoltaic cells from being under strong light. Partially blocked cells become loads due to lack of light, thereby consuming the heat of other cells exposed to light, resulting in severe heat and death. damaged.

Description of drawings

Fig. 1 is the overall structural representation of the present invention;

Fig. 2 is an exploded view of the present invention in the front view direction;

Fig. 3 is the structural representation of etching layer of the present invention;

4 is a schematic diagram of the positional relationship between the bottom layer and the second insulating layer of the present invention;

Fig. 5 is a schematic diagram of the structure of the embodiment of the present invention after being installed with the radiator.

Explanation of reference signs:

1. chip; 11. pin; 2. bare substrate; 21. first insulating layer; 22. etching layer; 221. first etching layer; 2211. first etching block; 2212. second etching block; 2213. second Three etching blocks; 222, second etching layer; 2221, fourth etching block; 2222, fifth etching block; 2223, sixth etching block; 2224, seventh etching block; 23, bottom layer; 231, heat conduction port; 3, The second insulating layer; 4. Bypass diode; 5. Negative pole terminal seat; 6. Positive pole terminal seat; 7. Radiator; 8. Welding layer.

detailed description

The technical scheme of the present invention will be clearly described below in conjunction with the accompanying drawings. Obviously, the described embodiments are not all embodiments of the present invention. Embodiments all belong to the protection scope of the present invention. It should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal" etc. are based on the orientation or position shown in the drawings The positional relationship is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

As shown in Figure 1, the present invention provides a heat dissipation structure for a concentrated photovoltaic cell substrate, including a chip 1, a bare substrate 2, a negative terminal seat 5, a positive terminal seat 6, and a bypass diode 4, and the front and side walls of the bare substrate 2 Weld the chip 1 at the center position, the center position of the rear side wall of the chip 1 is set as the positive pole, the positions of the upper and lower ends of the chip 1 are the negative pole; the lower position of the front side wall of the bare substrate 2 is fixedly connected with the bypass diode 4 and the positive terminal seat 6 , the bypass diode 4 and the positive terminal seat 6 are located at both ends of the lower part of the front side wall of the bare substrate 2, the bypass diode 4 and the positive terminal seat 6 are located on the same horizontal line of the front side wall of the bare substrate 2, and the front side of the bare substrate 2 The upper part of the side wall is also fixedly connected with the negative terminal base 5, which is located directly above the bypass diode 4, the opening of the negative terminal base 5 faces upward, and the positive terminal base 6 and the negative terminal base 5 are located on the front side of the bare substrate 2 At both ends of the diagonal line of the side wall, the opening of the positive terminal seat 6 faces directly below; the positive terminal seat 6 and the negative terminal seat 5 are provided to enable the positive and negative electrodes of the chip 1 to communicate with other devices, which can play a conductive role; Setting the bypass diode 4 can effectively prevent gallium arsenide batteries from being burned due to the hot spot effect, and can prevent solar cells from being blocked under strong light, causing some of the blocked cells to become loads due to lack of light, and consume other cells. The energy stored in the illuminated battery, the shaded battery will generate severe heat and be damaged.

As shown in FIG. 2 , the bare substrate 2 is made of copper, and the thickness of the bare substrate 2 is 0.8 mm. The bare substrate 2 is arranged in layers. The bare substrate 2 includes a first insulating layer 21 , an etching layer 22 and a bottom layer 23 from top to bottom. , the top is the first insulating layer 21, the setting of the first insulating layer 21 can protect the circuit, prevent the circuit from being damaged and can play the role of insulation; the middle layer is the etching layer 22, the etching layer 22 is made of copper, and the bottom layer The layer is the bottom layer 23, and the bottom layer 23 is also made of copper.

As shown in Figure 3, the etching layer 22 comprises a first etching layer 221, a second etching layer 222 and several etching blocks, the cross section of the first etching layer 221 along the vertical direction is F-type, and the vertical section of the first etching layer 221 is The first etching block 2211, the second etching block 2212 and the third etching block 2213 are welded on the front side and the side wall, and the first etching block 2211, the second etching block 2212 and the third etching block 2213 protrude from the first insulating layer 21. An etching block 2211, a second etching block 2212, and a third etching block 2213 are located on a vertical line, and the front and side walls of the first etching block 2211 are plated with nickel and gold to form a negative pad and conduct with the bypass diode 4. The side wall of the diode 4 close to the first insulating layer 21 is soldered with the first etching block 2211; the front side walls of the second etching block 2212 and the third etching block 2213 are also plated with nickel gold to form a negative pad and It is connected to the negative terminal base 5, and the side wall of the negative terminal base 5 near the first insulating layer 21 is soldered with the second etching block 2212 and the third etching block 2213; the front of the two horizontal parts of the first etching layer 221 The side walls are also plated with nickel and gold to form a negative electrode pad, and are connected to the negative electrodes at the upper and lower ends of the chip 1 through several pins 11, and the negative end of the chip 1 is soldered to the two horizontal parts of the first etching layer 221 through the pins 11 ; The side walls of the rear side of the first etching layer 221 are coated with insulating ink.

The left end of the horizontal part above the second etching layer 222 is horizontally welded with the fifth etching block 2222, the fifth etching block 2222 protrudes from the first insulating layer 21, and the thickness of the fifth etching block 2222 is thicker than that of the second etching layer 222, and the fifth etching block 2222 is thicker than that of the second etching layer 222. The front and side walls of the fifth etching block 2222 are plated with nickel and gold to form a positive electrode pad and conduct with the positive electrode of the chip 1, and the positive electrode of the chip 1 is soldered to the fifth etching block 2222 by tin; the front side of the horizontal part below the second etching layer 222 The left end of the wall is welded with a fourth etching block 2221, the fourth etching block 2221 protrudes from the first insulating layer 21, and the front and side walls of the fourth etching block 2221 are plated with nickel and gold to form an anode pad and connect with the bypass diode 4 close to the first One side wall of the insulating layer 21 is conductive, and the bypass diode 4 is soldered to the front side wall of the fourth etching block 2221 near the bottom of the first insulating layer 21; the front side wall of the vertical part of the second etching layer 222 is Weld the sixth etching block 2223 and the seventh etching block 2224 sequentially from bottom to top. The side and side walls are all plated with nickel and gold to form a positive electrode pad and conduct with the positive terminal seat 6, and the side wall of the positive terminal seat 6 near the first insulating layer 21 is connected with the sixth etching block 2223 and the seventh etching block 2224 tin respectively. Welding; the rear side wall of the second etching layer 222 is brushed with insulating ink, and the rear side wall of the fifth etching block protrudes from the insulating ink.

The negative pole of the chip 1 is conducted through the first etching layer 221 to the negative terminal base 5, the positive pole of the chip 1 is conducted through the second etching layer 222 to the positive terminal base 6, and the positive terminal base 6 and the negative terminal base 5 are connected in parallel to the bypass diode 4, which can To prevent the battery from being damaged by a large amount of heat due to the spot effect, the back and side walls of the first etching layer 221 and the second etching layer 222 are painted with insulating ink, which can prevent the bottom layer 23 from being charged.

As shown in Figure 4, the central position of the upper side wall of the bottom layer 23 is provided with a heat dissipation port, the heat dissipation port is vertically arranged, the heat dissipation port is a through hole, and the fifth etching block 2222 protrudes from the second etching layer 222 lower side wall. The part of the coated insulating ink can extend into the inside of the heat dissipation port, the length and width of the horizontal section of the heat dissipation port are the same as the length and width of the vertical section of the fifth etching block 2222, and the bottom side of the bottom layer 23 is fixed at the center of the side wall. The second insulating layer 3, the upper and side walls of the second insulating layer 3 are set to cover the cooling vent, and the side wall of the fifth etching block 2222 extends out of the cooling vent and is bonded to the second insulating layer 3, and the second insulating layer 3 is 0.5um The material of the insulating ink is provided with the second insulating layer 3, which can prevent the radiator 7 from being electrified and have an insulating effect. At the same time, the thickness of the second insulating layer 3 is very thin, and can also play a good heat dissipation effect.

As shown in FIG. 5 , the lower side wall of the bottom layer 23 is welded to the heat sink 7 through the welding layer 8 , and the heat sink 7 abuts against the side wall of the first insulating layer 21 away from the bottom layer 23 .

The conductive path of the concentrated photovoltaic cell substrate in this embodiment: the positive electrode of the chip 1-the second etching layer 222-the positive terminal seat 6; the negative electrode of the chip 1-pin 11-the first etching layer 221-the negative terminal seat 5.

The heat dissipation path of the concentrated photovoltaic cell in this embodiment: chip 1 - fifth etching block 2222 - second insulating layer 3 - radiator 7 .

The present invention can ensure the heat dissipation efficiency of the chip 1 while ensuring that the radiator 7 is not charged, and can also simplify the processing steps of the second insulating layer 3, and only need to solder the second insulating layer 3 to the lower part of the bare substrate 2, The heat sink 7 is welded with the bare substrate 2, and the heat sink 7 and the second insulating layer 3 are in an abutting relationship. In this way, the processing steps are simplified to one welding, and the second insulating layer 3 is made of 0.5um insulating ink material. The heat dissipation path of the chip 1 can also be shortened, so that the chip 1 can dissipate heat better and improve heat dissipation efficiency.

The above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without Any deviation from the scope of the technical solution of the present invention shall be covered by the scope of the claims of the present invention.

Claims (10)

1. The utility model provides a spotlight photovoltaic cell base plate heat radiation structure, includes chip, bare substrate and radiator, its characterized in that, bare substrate includes etching layer and bottom, etching layer one side with the chip switches on, etching layer opposite side with the bottom rigid coupling, the etching layer is equipped with fifth etching piece, fifth etching piece one side with the chip switches on, the bottom is equipped with the thermovent, fifth etching piece opposite side stretches into inside the thermovent, the bottom lower part sets up the second insulating layer, the second insulating layer covers the fifth etching piece, the bottom lower part with the radiator welding.

2. The concentrating photovoltaic cell substrate heat dissipation structure of claim 1, wherein the second insulating layer is made of insulating ink, and the thickness of the second insulating layer is 0.5um.

3. The concentrating photovoltaic cell substrate heat dissipation structure of claim 1, wherein the lower portion of the etching layer is coated with an insulating ink.

4. The substrate heat dissipation structure of claim 1, wherein an anode is disposed under the chip, cathodes are disposed at two ends of the chip, the fifth etching block is electrically connected to the anode of the chip, and the etching layer is also electrically connected to the cathode of the chip.

5. The pv cell substrate heat dissipation structure of claim 4, further comprising a positive terminal pad and a negative terminal pad, wherein the etching layer comprises a first etching layer and a second etching layer, the first etching layer is in electrical communication with the negative terminal pad, and the second etching layer is in electrical communication with the positive terminal pad.

6. The concentrating photovoltaic cell substrate heat dissipation structure of claim 5, wherein the first etching layer comprises a second etching block and a third etching block, and both the second etching block and the third etching block are in conduction with the negative electrode terminal base; the second etching layer comprises a sixth etching block and a seventh etching block, and the sixth etching block and the seventh etching block are both communicated with the positive terminal seat.

7. The substrate heat dissipation structure of claim 5, wherein the negative electrode of the chip is electrically connected to the first etching layer through a plurality of pins.

8. The substrate heat dissipation structure for the concentrated photovoltaic cell according to claim 6 or 7, further comprising a bypass diode, wherein the bypass diode is connected in parallel with the positive terminal block and the negative terminal block through the etching layer respectively.

9. The substrate heat dissipation structure for concentrating photovoltaic cells according to claim 8, wherein the first etching layer is further provided with a first etching block, the second etching layer is further provided with a fourth etching block, and the first etching block and the fourth etching block are both in conduction with the bypass diode.

10. The pv cell substrate heat dissipation structure of claim 9, wherein a first insulating layer is disposed on the upper portion of the etching layer, and the first etching block, the second etching block, the third etching block, the fourth etching block, the fifth etching block, the sixth etching block, and the seventh etching block are disposed to protrude from the first insulating layer.

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