CN115575411A - Wafer defect detection method, apparatus, device and computer readable storage medium - Google Patents
Wafer defect detection method, apparatus, device and computer readable storage medium Download PDFInfo
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Abstract
The application provides a defect detection method, a defect detection device, a defect detection equipment and a computer readable storage medium of a wafer. The defect detection method of the wafer comprises the following steps: acquiring structural feature information of the surface of the wafer; according to the structural feature information, carrying out region division on the surface of the wafer, and respectively determining structural identification information of different divided regions; respectively determining defect detection strategies matched with different areas according to the structure identification information of the different areas; the wafer is inspected based on a defect detection strategy. According to the embodiment of the application, the requirements of different areas on the wafer on the detection sensitivity can be adjusted.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for detecting defects of a wafer.
Background
At present, in the related art, when a wafer is inspected, the coverage of the inspection is usually considered, but the inspected wafer surface is not finely distinguished, so that the following problems are easily caused:
(1) For the detection methods with higher detection speed/detection efficiency, such as optical detection and other detection methods, because of the limitation of the physical limit of the detection system, the resolution cannot meet the requirement for smaller process nodes, and the detection omission is easily generated for small defects in the detection process. Therefore, when the detection method is adopted, the problems that the detection task requirement cannot be met and the false detection rate is high and the like may occur to the high-order process.
(2) For a detection method with a lower detection speed but a higher detection resolution, such as an electron beam detection method, since it usually uses the same "detection sensitivity" to detect all detection areas on a wafer, for example, scanning an image with the same pixel size, and then using a uniform algorithm and a detection threshold to complete defect detection, it is difficult to reconcile the requirements of different areas on the wafer for the detection sensitivity, which easily causes the problems that the detection speed is difficult to cover enough areas, and a statistically significant sampling area cannot be obtained.
Therefore, it is a technical problem to be solved by those skilled in the art how to reconcile the requirements of different areas on the wafer on the detection sensitivity.
Disclosure of Invention
The embodiment of the application provides a method, a device and equipment for detecting the defects of a wafer and a computer readable storage medium, which can meet the requirements of different areas on the wafer on the detection sensitivity.
In a first aspect, an embodiment of the present application provides a method for detecting a defect of a wafer, where the method includes:
acquiring structural feature information of the surface of the wafer;
according to the structural feature information, carrying out region division on the surface of the wafer, and respectively determining structural identification information of different divided regions;
respectively determining defect detection strategies matched with different areas according to the structure identification information of the different areas;
the wafer is inspected based on a defect inspection strategy.
Optionally, the acquiring the structural feature information of the surface of the wafer includes:
calculating a mask plate error enhancement factor of the surface of the wafer;
and acquiring structural characteristic information of the surface of the wafer based on the mask error enhancement factor.
Optionally, determining the defect detection strategies matched with the different regions according to the structure identification information of the different regions respectively includes:
respectively determining the detection sensitivity matched with different areas according to the structure identification information of the different areas;
and respectively determining defect detection strategies matched with different areas according to the detection sensitivity.
Optionally, the structural feature information includes at least one of the following information:
first information for characterizing whether a surface structure of a wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
Optionally, the method for detecting the defect of the wafer further includes:
determining a data format adopted when recording design information of a wafer;
and recording the structure identification information of different areas by adopting the same format as the data format.
Optionally, determining the detection sensitivities matched with the different regions according to the structure identification information of the different regions respectively includes:
calculating a corresponding weight value for each point on the wafer according to the structure identification information of different areas;
and respectively determining the detection sensitivity matched with different areas according to the weight values.
Optionally, determining the detection sensitivities matched with different regions according to the weight values respectively includes:
if the weight value is larger than a preset weight threshold, selecting a first target sensitivity larger than a preset sensitivity threshold as detection sensitivity;
and if the weight value is smaller than the preset weight threshold, selecting a second target sensitivity smaller than the preset sensitivity threshold as the detection sensitivity.
Optionally, determining a data format used when recording the design information of the wafer includes:
determining marking area identification, detecting equipment type, detecting light spot size, detecting algorithm parameters and/or automatic defect classification parameters.
Optionally, determining the defect detection strategies matched with the different regions according to the structure identification information of the different regions respectively includes:
determining importance information and uniqueness information of each pattern on the wafer in the circuit design;
and respectively determining the defect detection strategies matched with the different areas according to the structure identification information, the importance degree information and the uniqueness information of the different areas.
Optionally, the inspection equipment for performing the defect inspection method of the wafer includes optical inspection equipment and/or electron beam inspection equipment, and the inspection equipment is connected to the material by a dedicated or general-purpose transmission system.
Optionally, the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment and two electron beam inspection equipments, wherein the material connection between the optical inspection equipment and the two electron beam inspection equipments is realized through a dedicated material conveying channel.
Optionally, the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment and two electron beam inspection equipments, wherein one optical inspection equipment and two electron beam inspection equipments are connected by a common material transfer passage.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
wherein, material connection is realized among one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices through a special material conveying channel.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
the material connection is realized among one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices through a universal material conveying channel.
In a second aspect, an embodiment of the present application provides an apparatus for detecting defects of a wafer, the apparatus including:
an acquisition module for acquiring structural feature information of a surface of a wafer;
the dividing module is used for dividing the surface of the wafer into areas according to the structural feature information and respectively determining the structural identification information of the divided different areas;
the determining module is used for respectively determining the defect detection strategies matched with different areas according to the structure identification information of the different areas;
and the detection module is used for detecting the wafer based on the defect detection strategy.
Optionally, the obtaining module includes:
a calculation unit for calculating a mask error enhancement factor of a surface of the wafer;
and the acquisition unit is used for acquiring the structural characteristic information of the surface of the wafer based on the mask plate error enhancement factor.
Optionally, the determining module includes:
the sensitivity determining unit is used for respectively determining the detection sensitivity matched with different areas according to the structure identification information of the different areas;
and the strategy determining unit is used for respectively determining the defect detection strategies matched with the different areas according to the detection sensitivity.
Optionally, the structural feature information includes at least one of the following information:
first information for characterizing whether a surface structure of a wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
Optionally, the defect detecting apparatus for a wafer further includes:
a format determination module for determining a data format used when recording design information of a wafer;
and the recording module is used for recording the structure identification information of different areas by adopting the same format as the data format.
Optionally, the sensitivity determining unit includes:
the weight determining subunit is used for calculating a corresponding weight value for each point on the wafer according to the structure identification information of the different areas;
and the sensitivity determining subunit is used for respectively determining the detection sensitivities matched with the different areas according to the weight values.
Optionally, the sensitivity determining subunit is configured to:
if the weight value is larger than a preset weight threshold, selecting a first target sensitivity larger than a preset sensitivity threshold as detection sensitivity;
and if the weight value is smaller than the preset weight threshold, selecting a second target sensitivity smaller than the preset sensitivity threshold as the detection sensitivity.
Optionally, the format determining module is configured to:
determining marking area identification, detecting equipment type, detecting light spot size, detecting algorithm parameters and/or automatic defect classification parameters.
Optionally, the determining module is configured to:
determining importance information and uniqueness information of each pattern on the wafer in the circuit design;
and respectively determining the defect detection strategies matched with the different areas according to the structure identification information, the importance degree information and the uniqueness information of the different areas.
Optionally, the inspection equipment for performing the wafer defect inspection method includes optical inspection equipment and/or electron beam inspection equipment, and the inspection equipment is connected to the material by a dedicated or general-purpose transmission system.
Optionally, the inspection equipment for performing the defect inspection method of the wafer includes an optical inspection equipment and two electron beam inspection equipments, wherein the material connection between the optical inspection equipment and the two electron beam inspection equipments is realized through a dedicated material conveying channel.
Optionally, the inspection equipment for performing the wafer defect inspection method includes an optical inspection equipment and two electron beam inspection equipment, wherein one optical inspection equipment and two electron beam inspection equipment are connected by a general material conveying channel.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
wherein, material connection is realized among one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices through a special material conveying channel.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
the material connection is realized among one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices through a universal material conveying channel.
In a third aspect, an embodiment of the present application provides a defect detecting apparatus for a wafer, where the apparatus includes:
the defect detecting apparatus of a wafer includes: a processor and a memory storing computer program instructions;
the processor, when executing the computer program instructions, implements the method for defect detection of a wafer as described in the first aspect above.
In a fourth aspect, the present application provides a computer-readable storage medium, on which computer program instructions are stored, and when executed by a processor, the computer program instructions implement the defect detection method for a wafer according to the first aspect.
According to the defect detection method, device and equipment for the wafer and the computer-readable storage medium, the structural feature information of the surface of the wafer can be acquired; then, according to the structural feature information, carrying out region division on the surface of the wafer, and respectively determining structural identification information of different divided regions; respectively determining defect detection strategies matched with the different areas according to the structure identification information of the different areas; and finally, detecting the wafer based on the defect detection strategy, so that different defect detection strategies can be adopted for different areas of the surface of the wafer to detect, and the requirements of different areas on the wafer on the detection sensitivity can be adjusted.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following descriptions are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart diagram illustrating a method for detecting defects on a wafer according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an embodiment of a defect detection strategy based on a combination of optical detection and electron beam detection + dedicated material delivery channel for detection provided in an embodiment of the present application;
FIG. 3 is a schematic diagram of an embodiment of a defect detection strategy based on a combination of optical detection and electron beam detection + universal material transfer channel detection provided in an embodiment of the present application;
FIG. 4 is a schematic diagram of an embodiment of a defect detection strategy based on optical detection and multi-electron beam detection combined detection + single-electron beam detection device combined detection + dedicated material transport channel detection provided in an embodiment of the present application;
FIG. 5 is a schematic diagram of an embodiment of a defect detection strategy based on optical detection and multi-electron beam detection and single-electron beam detection combined detection and a universal material transfer channel for detection provided in an example of the present application;
FIG. 6 is a schematic structural diagram of a defect inspection apparatus for a wafer according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a wafer defect inspection apparatus according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of, and not restrictive on, the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
At present, in the related art, the coverage of the inspection is usually considered when the wafer is inspected, but the surface of the inspected wafer is not finely distinguished, so that the following problems are easily caused:
(1) For a detection method with high detection speed/detection efficiency, such as an optical detection method, a full wafer surface inspection (full coverage) is generally used. However, due to the limitation of the physical limit of the detection system, the resolution cannot meet the requirement of smaller process nodes, and missing detection is easily generated on small defects in the detection process, so that problems that the requirement of a detection task cannot be met and the false detection rate is high may occur on high-order processes when the detection method is adopted.
(2) For a detection method with a low detection speed and a high detection resolution, such as an electron beam detection method, sampling detection is generally used, wherein sampling detection refers to defining a detection area on the surface of a wafer and performing defect detection only in the detection area. When the method is adopted, all detection areas on the wafer are detected by the same detection sensitivity, for example, images are scanned by the same pixel size, and then defect detection is finished by using a uniform algorithm and a detection threshold value, so that the requirements of different areas on the wafer on the detection sensitivity are difficult to reconcile, and the problems that the detection speed is difficult to cover enough areas, a sampling area with statistical significance cannot be obtained and the like are easily caused.
For example, in practical applications, some regions on a wafer are sensitive to the existence of defects, and even the existence of small defects can affect the electrical performance of a chip, and for convenience of description, these regions are referred to as "important regions" below; however, some regions have little effect on the final performance of the chip due to the existence of defects, such as the Dummy Fill region, where the existence of defects does not affect the electrical performance of the chip, and such regions are referred to as "unimportant regions". In this way, if the same "detection sensitivity" is used for each region of the wafer, for example, the same pixel size and the same detection threshold are used for defect detection, the following problems occur: in the important area, in order to detect small defects, the detection sensitivity needs to be improved, and this also means that in the non-important area, insignificant small defects are reported, and the subsequent processing of these defects, including automatic defect classification, recording, storage, and the like, is meaningless, which is a waste of detection resources and a reduction in detection efficiency. Conversely, if the detection sensitivity is depressed, the insignificant defects in the non-important regions are reduced, but the detection of small defects in the important regions may be missed, which is a more serious problem, in other words, it is difficult for the detection method to reconcile the requirements of different regions on the wafer for the detection sensitivity.
In order to solve the problems of the prior art, embodiments of the present application provide a method, an apparatus, a device, and a computer-readable storage medium for detecting a defect of a wafer. The method for detecting defects of a wafer provided by the embodiment of the present application is first described below.
Fig. 1 is a schematic flow chart illustrating a method for detecting defects of a wafer according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
and S001, acquiring structural feature information of the surface of the wafer.
Wherein, the structural feature information may include at least one of the following information:
first information for characterizing whether a surface structure of a wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
In the embodiment of the present application, it is considered that although the shapes of the pattern structures distributed on the wafer surface are different, the density is different, and the structures are changed (there are many repeating structures, but the repeating cycle and the repeating number are not completely consistent), they are designed by the designer. Therefore, it is possible to know exactly all the structural features on the wafer surface, for example, which sites are prone to defects during the production process; which sites have structures that are sensitive or insensitive to which type of defect; which parts are Dummy Fill, defect detection can not be carried out; which sites are not sensitive to the final chip performance; which sites are due to the redundancy design, even defects will not affect the final performance. Based on this, before the wafer is inspected, the structural feature information of the surface of the wafer may be obtained, so as to determine the corresponding defect inspection strategy according to the structural feature information of the surface of the wafer.
In an alternative embodiment, the structural characteristic information of the surface of the wafer may be obtained by:
(1) Calculating a mask plate error enhancement factor of the surface of the wafer;
(2) And acquiring structural characteristic information of the surface of the wafer based on the mask error enhancement factor.
In the embodiment of the application, the mask error enhancement factor of the surface of the wafer can be obtained through quantification and calculation, and then the structural characteristic information of the surface of the wafer is obtained according to the mask error enhancement factor, for example, when the mask error enhancement factor is determined to be a preset first numerical value, the surface of the wafer corresponding to the mask error enhancement factor is considered to be an error-prone area (hot spots). Or, when the mask error enhancement factor is determined to be the preset second value, the surface of the wafer corresponding to the mask error enhancement factor is considered to be a dummy fill area, that is, an area which can not be subjected to defect detection.
The preset first numerical value and the preset second numerical value can be determined according to actual working experience.
It should be noted that the above-mentioned manner of acquiring the structural feature information of the surface of the wafer is only an exemplary illustration of the embodiments of the present application, and does not set any limit to the embodiments of the present application.
And S002, dividing the surface of the wafer into areas according to the structural feature information, and respectively determining structural identification information of the divided different areas.
In the embodiment of the application, after the structural feature information of the surface of the wafer is obtained, the surface of the wafer may be divided into regions according to the structural feature information, and the structural identification information of the divided different regions is determined respectively.
For example, following the example illustrated in S001, if it is determined that the structural feature information of a certain portion of the wafer surface is error-prone, the region corresponding to the certain portion may be divided into error-prone regions, and the structural identification information of the region may be determined to be hot spots regions or may be referred to as "error-prone regions".
For another example, if it is determined that the structural feature information of a certain portion of the wafer surface is not sensitive to the final chip performance, the region corresponding to the certain portion may be divided into regions that may not be subjected to defect detection, and the structural identification information of the region is determined to be a dummy fill region, or is marked as "a region that may not be subjected to defect detection".
It should be noted that the above-mentioned manner for determining the structure identification information of different areas is only an exemplary illustration of the embodiments of the present application, and does not set any limit to the embodiments of the present application.
In an alternative embodiment, after determining the structure identification information of the divided different regions, the data format used when recording the design information of the wafer may also be determined; and recording the structure identification information of different areas by adopting the same format as the data format. The structure identification information of different areas is recorded by adopting the same format as the data format, and the division of the detection area can be understood to be accurate to the same scale as each polygon on the wafer.
Optionally, the data format used when recording the design information of the wafer may include, but is not limited to: marking area identification, such as marking area ID, detection device type, detection spot size, detection algorithm parameters, automatic Defect Classification (ADC) parameters.
And S003, respectively determining defect detection strategies matched with different areas according to the structure identification information of the different areas.
The defect detection strategy may include information such as detection sensitivity.
In this embodiment, a weight may be calculated for each point on the wafer according to the structure identification information of the different regions, and then the defect detection strategies matched with the different regions are determined according to the weights, for example, the sensitivities of the different regions to be detected are automatically selected according to the weights, for example, a higher sensitivity is used in a place with a high weight, and a lower sensitivity is used in a place with a low weight.
Alternatively, in an embodiment, the comprehensive detection planning may be performed according to the structure identification information of the different regions, and by combining the importance level and uniqueness of each pattern on the wafer in the circuit design, so as to determine the defect detection strategies matching the different regions respectively.
In an alternative embodiment, S003 can be further implemented by:
(1) Respectively determining the detection sensitivity matched with different areas according to the structure identification information of the different areas;
(2) And respectively determining defect detection strategies matched with different areas according to the detection sensitivity.
And S004, detecting the wafer based on the defect detection strategy.
In the embodiment of the present application, after determining the defect detection strategies matching different regions, the wafer may be detected based on the defect detection strategies.
The inspection device, in which the wafer is inspected based on the defect inspection strategy, may be a stand-alone inspection device, such as an optical inspection device or an electron beam inspection device. Moreover, the material connection between the detection devices can be realized by a dedicated or general-purpose transmission system, such as an Over Head Transport (OHT).
As shown in fig. 2 to fig. 5, schematic diagrams of four embodiments of inspecting a wafer based on an inspection apparatus according to an embodiment of the present application are provided.
Fig. 2 is a schematic diagram of an implementation manner of performing detection by combining optical detection and electron beam detection and a dedicated material transfer channel based on a defect detection strategy provided in an embodiment of the present application. As shown in fig. 2, the inspection apparatus includes 1 optical inspection apparatus and two electron beam inspection apparatuses, wherein the 1 optical inspection apparatus and the two electron beam inspection apparatuses are connected to each other through a dedicated/dedicated material transfer channel.
Fig. 3 is a schematic diagram of an implementation of the defect detection strategy based on the embodiment of the present application, in which the detection is performed by combining optical detection and electron beam detection and a general material transfer channel. As shown in fig. 3, the inspection equipment includes 1 optical inspection equipment and two electron beam inspection equipment, wherein the material connection is realized between the 1 optical inspection equipment and the two electron beam inspection equipment through a general material conveying channel.
Fig. 4 is a schematic diagram of an embodiment of detection performed by optical detection and multi-electron beam detection combined detection + single-electron beam detection device combined detection + dedicated material delivery channel based on a defect detection strategy provided in an embodiment of the present application. As shown in fig. 4, the detecting device includes 1 optical detecting device, 1 multi-electron beam detecting device and 2 single-electron beam detecting devices, wherein the 1 optical detecting device, the 1 multi-electron beam detecting device and the 2 single-electron beam detecting devices are connected to each other through a dedicated/proprietary material conveying channel.
Fig. 5 is a schematic diagram of an embodiment of the present application that performs detection by optical detection and multi-e-beam detection + single-e-beam detection combined detection + a general material transfer channel, such as an OHT, based on a defect detection strategy. As shown in fig. 5, the detecting device includes 1 optical detecting device, 1 multi-electron beam detecting device and 2 single-electron beam detecting devices, wherein the 1 optical detecting device, the 1 multi-electron beam detecting device and the 2 single-electron beam detecting devices are connected through a general material conveying channel.
Optionally, in a practical application scenario, the detection device in the embodiment of the present application may be an integrated detection system with multiple detection paths, which includes multiple detection units with different capabilities, and may further include a controller. Wherein, the controller can know the capability of all detection units in the detection device and various possible detection paths; the controller may understand the structural marking information of the surface of the wafer.
In an alternative embodiment, the controller, after receiving the inspection task, may read the structure mark information of the surface of the wafer for analysis, and then combine to optimize the corresponding defect inspection scheme. Alternatively, the solution optimized by combination can take the maximum detection productivity as an objective function.
The controller may be a specific intelligent control device, or may be an algorithm capable of implementing a control function. When the controller is an algorithm capable of realizing a control function, the algorithm needs to optimize allocation of each detection task in the system, so that the detection productivity is optimal.
By adopting the defect detection method of the wafer, the structural feature information of the surface of the wafer can be obtained; then, according to the structural feature information, carrying out region division on the surface of the wafer, and respectively determining the structural identification information of different divided regions; respectively determining defect detection strategies matched with different areas according to the structure identification information of the different areas; and finally, detecting the wafer based on the defect detection strategy, so that different defect detection strategies can be adopted for different areas of the surface of the wafer to detect, and the requirements of different areas on the wafer on the detection sensitivity can be adjusted.
On the other hand, the detection strategy can be flexibly adjusted in the detection process, the detection execution is optimized, and the detection sensitivity is adjusted according to the situation, so that the overall detection productivity of the defect detection is optimized.
Fig. 6 shows a schematic structural diagram of a defect detection apparatus for a wafer according to an embodiment of the present application. As shown in fig. 6, the apparatus includes:
an obtaining module 601, configured to obtain structural feature information of a surface of a wafer;
a dividing module 602, configured to perform region division on the surface of the wafer according to the structural feature information, and determine structural identification information of different divided regions respectively;
a determining module 603, configured to determine, according to the structure identifier information of different regions, defect detection strategies that are matched with the different regions respectively;
an inspection module 604 for inspecting the wafer based on a defect detection strategy.
Optionally, the obtaining module 601 includes:
a calculation unit for calculating a mask error enhancement factor of a surface of the wafer;
and the acquisition unit is used for acquiring the structural characteristic information of the surface of the wafer based on the mask plate error enhancement factor.
Optionally, the determining module 603 includes:
the sensitivity determining unit is used for respectively determining the detection sensitivity matched with different areas according to the structure identification information of the different areas;
and the strategy determining unit is used for respectively determining the defect detection strategies matched with the different areas according to the detection sensitivity.
Optionally, the structural feature information includes at least one of the following information:
first information for characterizing whether a surface structure of a wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
Optionally, the apparatus for detecting a defect of a wafer further includes:
the format determining module is used for determining a data format adopted when the design information of the wafer is recorded;
and the recording module is used for recording the structure identification information of different areas by adopting the same format as the data format.
Optionally, the sensitivity determining unit includes:
the weight determining subunit is used for calculating a corresponding weight value for each point on the wafer according to the structure identification information of the different areas;
and the sensitivity determining subunit is used for respectively determining the detection sensitivities matched with the different areas according to the weight values.
Optionally, the sensitivity determining subunit is configured to:
if the weight value is larger than a preset weight threshold, selecting a first target sensitivity larger than a preset sensitivity threshold as detection sensitivity;
and if the weight value is smaller than the preset weight threshold, selecting a second target sensitivity smaller than the preset sensitivity threshold as the detection sensitivity.
Optionally, the format determining module is configured to:
determining marking area identification, detecting equipment type, detecting light spot size, detecting algorithm parameters and/or automatic defect classification parameters.
Optionally, the determining module is configured to:
determining importance information and uniqueness information of each pattern on the wafer in the circuit design;
and respectively determining defect detection strategies matched with different areas according to the structure identification information, the importance degree information and the uniqueness information of the different areas.
Optionally, the inspection equipment for performing the wafer defect inspection method includes optical inspection equipment and/or electron beam inspection equipment, and the inspection equipment is connected to the material by a dedicated or general-purpose transmission system.
Optionally, the inspection equipment for performing the wafer defect inspection method includes an optical inspection equipment and two electron beam inspection equipment, wherein one optical inspection equipment and two electron beam inspection equipment are connected by a dedicated material conveying channel.
Optionally, the inspection equipment for performing the wafer defect inspection method includes an optical inspection equipment and two electron beam inspection equipment, wherein one optical inspection equipment and two electron beam inspection equipment are connected by a general material conveying channel.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
the optical detection device, the multi-electron beam detection device and the two single-electron beam detection devices are connected through a special material conveying channel.
Optionally, if the electron beam inspection apparatus includes a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the defect inspection method of the wafer includes one optical inspection apparatus, one multi-electron beam inspection apparatus, and two single-electron beam inspection apparatuses;
the material connection is realized among one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices through a universal material conveying channel.
Each module/unit in the apparatus shown in fig. 6 has a function of implementing each step in fig. 1, and can achieve corresponding technical effects, and for brevity, no further description is provided here.
Fig. 7 shows a schematic structural diagram of a defect detection apparatus for a wafer according to an embodiment of the present application.
The defect inspection apparatus for a wafer may include a processor 701 and a memory 702 storing computer program instructions.
Specifically, the processor 701 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured to implement one or more Integrated circuits of the embodiments of the present Application.
In one embodiment, the Memory 702 may be a Read Only Memory (ROM). In one embodiment, the ROM may be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically Erasable PROM (EEPROM), electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.
The processor 701 reads and executes the computer program instructions stored in the memory 702 to implement the defect detection method of the wafer in any one of the above embodiments.
In one example, the wafer defect detection apparatus may further include a communication interface 703 and a bus 710. As shown in fig. 7, the processor 701, the memory 702, and the communication interface 703 are connected via a bus 710 to perform communication with each other.
The communication interface 703 is mainly used for implementing communication between modules, apparatuses, units and/or devices in this embodiment.
The bus 710 includes hardware, software, or both to couple the components of the wafer's defect detection equipment to each other. By way of example, and not limitation, a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hypertransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus or a combination of two or more of these. Bus 710 may include one or more buses, where appropriate. Although specific buses are described and shown in the embodiments of the application, any suitable buses or interconnects are contemplated by the application.
In addition, in combination with the defect detection method of the wafer in the above embodiments, the embodiments of the present application may provide a computer readable storage medium to implement. The computer readable storage medium having stored thereon computer program instructions; the computer program instructions, when executed by a processor, implement a method of defect detection of a wafer as in any of the above embodiments.
It is to be understood that the present application is not limited to the particular arrangements and instrumentalities described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions or change the order between the steps after comprehending the spirit of the present application.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.
It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed at the same time.
Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.
Claims (30)
1. A method for detecting defects of a wafer, comprising:
acquiring structural feature information of the surface of the wafer;
according to the structural feature information, carrying out region division on the surface of the wafer, and respectively determining structural identification information of different divided regions;
respectively determining defect detection strategies matched with the different areas according to the structure identification information of the different areas;
inspecting the wafer based on the defect detection strategy.
2. A method as claimed in claim 1, wherein the step of obtaining structural feature information of the surface of the wafer comprises:
calculating a mask error enhancement factor of the surface of the wafer;
and acquiring structural characteristic information of the surface of the wafer based on the mask error enhancement factor.
3. The wafer defect detection method of claim 1, wherein determining the defect detection strategies matching the different regions respectively according to the structure identification information of the different regions comprises:
respectively determining the detection sensitivity matched with the different areas according to the structure identification information of the different areas;
and respectively determining the defect detection strategies matched with the different areas according to the detection sensitivity.
4. A method for detecting defects in a wafer as recited in claim 1, wherein the structural feature information includes at least one of:
first information for characterizing whether a surface structure of the wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
5. A method for defect inspection of a wafer as recited in claim 1, further comprising:
determining a data format adopted when recording the design information of the wafer;
and recording the structure identification information of the different areas by adopting the same format as the data format.
6. The method of claim 3, wherein determining the detection sensitivities respectively matched to the different regions according to the structure identification information of the different regions comprises:
calculating a corresponding weight value for each point on the wafer according to the structure identification information of the different regions;
and respectively determining the detection sensitivity matched with the different areas according to the weight values.
7. The method of claim 6, wherein determining the detection sensitivities respectively matched to the different regions according to the weighting values comprises:
if the weight value is greater than a preset weight threshold, selecting a first target sensitivity greater than a preset sensitivity threshold as the detection sensitivity;
and if the weight value is smaller than a preset weight threshold, selecting a second target sensitivity smaller than a preset sensitivity threshold as the detection sensitivity.
8. The method of claim 5, wherein the determining the data format used for recording the design information of the wafer comprises:
determining marking area identification, detecting equipment type, detecting light spot size, detecting algorithm parameters and/or automatic defect classification parameters.
9. The method of claim 1, wherein determining the defect detection strategies matching the different regions according to the structure identification information of the different regions comprises:
determining importance information and uniqueness information of each pattern on the wafer in a circuit design;
and respectively determining the defect detection strategies matched with the different areas according to the structure identification information, the importance degree information and the uniqueness information of the different areas.
10. The wafer defect inspection method according to claim 1, wherein the inspection equipment for performing the wafer defect inspection method comprises optical inspection equipment and/or electron beam inspection equipment, and the inspection equipment is connected with material by a special or general transmission system.
11. The wafer defect inspection method according to claim 10, wherein the inspection equipment for performing the wafer defect inspection method comprises one said optical inspection equipment and two said electron beam inspection equipment, wherein a material connection is made between one said optical inspection equipment and two said electron beam inspection equipment through a dedicated material transfer passage.
12. The wafer defect inspection method of claim 10, wherein the inspection equipment for performing the wafer defect inspection method comprises one optical inspection equipment and two electron beam inspection equipment, wherein the one optical inspection equipment and the two electron beam inspection equipment are connected by a common material conveying passage.
13. The wafer defect inspection method of claim 10, wherein if the electron beam inspection apparatus comprises a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the wafer defect inspection method comprises one of the optical inspection apparatus, one of the multi-electron beam inspection apparatus and two of the single-electron beam inspection apparatus;
and one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices are connected through a special material conveying channel.
14. The wafer defect inspection method of claim 10, wherein if the electron beam inspection apparatus comprises a multi-electron beam inspection apparatus and a single-electron beam inspection apparatus, the inspection apparatus for performing the wafer defect inspection method comprises one of the optical inspection apparatus, one of the multi-electron beam inspection apparatus and two of the single-electron beam inspection apparatus;
and one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices are connected through a universal material conveying channel to realize material connection.
15. An apparatus for detecting defects of a wafer, the apparatus comprising:
an acquisition module for acquiring structural feature information of a surface of a wafer;
the dividing module is used for dividing the surface of the wafer into areas according to the structural feature information and respectively determining the structural identification information of the divided different areas;
the determining module is used for respectively determining the defect detection strategies matched with the different areas according to the structure identification information of the different areas;
a detection module to detect the wafer based on the defect detection strategy.
16. The apparatus of claim 15, wherein the acquiring module comprises:
a calculation unit for calculating a mask error enhancement factor of the surface of the wafer;
and the acquisition unit is used for acquiring the structural characteristic information of the surface of the wafer based on the mask error enhancement factor.
17. A wafer defect inspection apparatus as claimed in claim 15, wherein the determining module comprises:
the sensitivity determining unit is used for respectively determining the detection sensitivity matched with the different areas according to the structure identification information of the different areas;
and the strategy determining unit is used for respectively determining the defect detection strategies matched with the different areas according to the detection sensitivity.
18. A defect inspection apparatus for a wafer as claimed in claim 15, wherein said structural characteristic information includes at least one of:
first information for characterizing whether a surface structure of the wafer is susceptible to defects during a production process;
second information indicating a type of defect to which the surface structure of the wafer is sensitive and/or insensitive;
third information indicating whether the surface structure of the wafer is insensitive to the final chip performance.
19. A defect inspection apparatus for a wafer as defined in claim 15, wherein said apparatus further comprises:
the format determining module is used for determining a data format adopted when the design information of the wafer is recorded;
and the recording module is used for recording the structure identification information of the different areas by adopting the same format as the data format.
20. A defect inspection apparatus for a wafer as claimed in claim 17, wherein said sensitivity determining unit comprises:
a weight determining subunit, configured to calculate, according to the structure identification information of the different regions, a corresponding weight value for each point on the wafer;
and the sensitivity determining subunit is used for respectively determining the detection sensitivities matched with the different regions according to the weight values.
21. A defect inspection apparatus of a wafer as defined in claim 20, wherein the sensitivity determining subunit is configured to:
if the weight value is greater than a preset weight threshold, selecting a first target sensitivity greater than a preset sensitivity threshold as the detection sensitivity;
and if the weight value is smaller than a preset weight threshold, selecting a second target sensitivity smaller than a preset sensitivity threshold as the detection sensitivity.
22. A wafer defect inspection apparatus as claimed in claim 19, wherein said format determining module is configured to:
determining marking area identification, detecting equipment type, detecting light spot size, detecting algorithm parameters and/or automatic defect classification parameters.
23. A wafer defect inspection apparatus as claimed in claim 15, wherein said determining module is configured to:
determining importance information and uniqueness information of each pattern on the wafer in a line design;
and respectively determining the defect detection strategies matched with the different regions according to the structure identification information, the importance degree information and the uniqueness information of the different regions.
24. The wafer defect inspection apparatus of claim 15, wherein the inspection devices for performing the wafer defect inspection method comprise optical inspection devices and/or electron beam inspection devices, and the inspection devices are connected to each other by a dedicated or general-purpose transport system.
25. A wafer defect inspection apparatus as claimed in claim 24, wherein said inspection means for performing said wafer defect inspection method comprises one said optical inspection means and two said electron beam inspection means, wherein a material connection is made between one said optical inspection means and two said electron beam inspection means via a dedicated material transfer passage.
26. A defect inspection apparatus for a wafer as claimed in claim 24, wherein the inspection device for performing the defect inspection method for the wafer comprises one said optical inspection device and two said electron beam inspection devices, wherein a material connection is made between one said optical inspection device and two said electron beam inspection devices via a common material transfer path.
27. A defect inspection apparatus for a wafer as claimed in claim 24, wherein if said electron beam inspection device comprises a plurality of electron beam inspection devices and a single electron beam inspection device, an inspection device for performing a defect inspection method for said wafer comprises one said optical inspection device, one said plurality of electron beam inspection devices and two said single electron beam inspection devices;
and one optical detection device, one multi-electron beam detection device and two single-electron beam detection devices are connected through a special material conveying channel.
28. A defect inspection apparatus for a wafer as claimed in claim 24, wherein if said electron beam inspection device comprises a plurality of electron beam inspection devices and a single electron beam inspection device, an inspection device for performing a defect inspection method for said wafer comprises one said optical inspection device, one said plurality of electron beam inspection devices and two said single electron beam inspection devices;
and the optical detection equipment, the multi-electron beam detection equipment and the single-electron beam detection equipment are connected by a universal material conveying channel.
29. A defect inspection apparatus of a wafer, characterized in that the defect inspection apparatus of the wafer comprises: a processor and a memory storing computer program instructions;
the processor, when executing the computer program instructions, implements a method for defect detection of a wafer as recited in any of claims 1-14.
30. A computer-readable storage medium having computer program instructions stored thereon, which when executed by a processor, implement a method of defect detection of a wafer as recited in any one of claims 1-14.
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| CN202211188801.6A CN115575411A (en) | 2022-09-28 | 2022-09-28 | Wafer defect detection method, apparatus, device and computer readable storage medium |
| PCT/CN2023/086169 WO2024066279A1 (en) | 2022-09-28 | 2023-04-04 | Wafer defect detection method, device and apparatus, and computer-readable storage medium |
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| CN202211188801.6A CN115575411A (en) | 2022-09-28 | 2022-09-28 | Wafer defect detection method, apparatus, device and computer readable storage medium |
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| WO2024066279A9 (en) | 2024-05-23 |
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