CN1154631A - Image decoding device - Google Patents

Image decoding device Download PDF

Info

Publication number
CN1154631A
CN1154631A CN 96107280 CN96107280A CN1154631A CN 1154631 A CN1154631 A CN 1154631A CN 96107280 CN96107280 CN 96107280 CN 96107280 A CN96107280 A CN 96107280A CN 1154631 A CN1154631 A CN 1154631A
Authority
CN
China
Prior art keywords
data
mentioned
frame
memory
image data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 96107280
Other languages
Chinese (zh)
Inventor
栗原弘一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to CN 96107280 priority Critical patent/CN1154631A/en
Publication of CN1154631A publication Critical patent/CN1154631A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00Image coding
    • G06T9/004Predictors, e.g. intraframe, interframe coding

Abstract

The invention provides a image decoding device to reduce memory displacement. A decoding output of a B-picture is given to a memory. A memory control circuit divides a one (1) image plane to four (4) regions. Write is executed to the memory for the divided image data that are the decoding output with respect to eight (8) regions of first and second fields. The time at which each of the divided image data are retained in the memory is decided in accordance with the field to which the divided image data belongs and a position on an image plane. On the basis of this, subsequent to the readout of the divided image data, the other divided image data are written to a common storage region of the memory. Thus, a total memory capacity is reduced to enable interlacement conversion.

Description

Image decoding apparatus
The present invention relates to comprise the image decoding apparatus that the coded data of two-way prediction coded data is decoded.
Along with the establishment of the high-efficiency coding technology of image, the digitized processing of image is also popularized gradually in recent years.In order to improve the efficient of Digital Transmission and record etc., adopt little Bit Transmission Rate coding image data.In this high efficient coding, carry out orthogonal transforms such as DCT (discrete cosine transform) processing with m * n pixel block unit.Orthogonal transform is that the sampling value that will be imported is transformed into orthogonal components such as spatial frequency composition.Therefore can cut down the relevant composition in space.The composition of orthogonal transform is by quantizing to cut down the redundant information of block signal.
Particularly quantize output, further cut down data volume by variable length codes such as huffman coding are added to.Huffman coding is that the result that basis is calculated by the statistical coding amount that quantizes output encodes, and distributes to the high data of occurrence probability by lacking the position, with long the variable length code of distributing to the low data of occurrence probability, cuts down whole data volume.
And then in the device that carries out high efficient coding, the hybrid mode of studying with MPEG (mobile picture experts group) etc. becomes main flow.In this mode, in the frame that image in the frame is carried out the DCT processing, the compression, also adopt the correlation of utilizing interframe to cut down the interframe compression of the redundant information of time-axis direction.The interframe compression is to utilize general mobile image in the very similar such character of front and back frame, and the difference of frame by code differential value (prediction error), further lowers Bit Transmission Rate before and after asking., be effective particularly so reduce the moving compensation interframe prediction coding of prediction error because frame-to-frame differences is obtained in moving of prediction image.
Like this, in hybrid mode, except the pictorial data of regulation frame is carried out directly DCT handles and the intraframe coding of coding, adopt the pictorial data of regulation frame and only therewith the differential data of the reference picture data of the frame before and after the frame carry out that DCT handles and the prediction coding of coding.Coding method has as prediction: by the time with the place ahead to the reference picture data move compensation and obtain the place ahead prediction coding of prediction error; By the time with the rear to the reference picture data move compensation and obtain the rear prediction coding of prediction error and consider that code efficiency uses in the place ahead or the rear the average two-way prediction coding of either party or two directions.
Because only encode, so can be only with independent coded data coding with the frame internal information with the frame (hereinafter referred to as the I picture) that intraframe coding had been encoded.Thereby, in the MPEG specification,, can the I picture be inserted at fixed cycle (for example 12 frames) in order to prevent error diffusion etc.In the MPEG specification, the place ahead prediction coding by with this I picture can obtain inter-frame encoding frame (hereinafter referred to as the P picture).Moreover the P picture carries out the place ahead prediction coding by the P picture with the place ahead and also can obtain.And adapt to converted frames (hereinafter referred to as the B picture) by using in the place ahead or the rear either party or two-way I, P picture two-way prediction coding can obtain two-way prediction.
Fig. 9 is the key diagram in order to the compression method that this mode is described.The frame image that Fig. 9 (a) expression is imported, Fig. 9 (b) presentation code data, Fig. 9 (c) represents decoded data.Figure 10 is the key diagram of handling in order to the explanation blocking.
The frame image of frame number 0 is carried out intraframe coding.Use this frame image as with reference to image, the frame image of frame number 3 is carried out the place ahead prediction coding.The arrow of Fig. 9 (b) is represented the like this prediction direction of coding, and the frame image of frame number 6 also carries out the frame image of the frame number 3 in the place ahead the place ahead prediction coding as with reference to visual.The frame image of frame preface 1,2 also carries out two-way prediction coding as the reference image with the frame image of frame number 0,3.And the frame image of frame number 4,5 carries out two-way prediction coding as with reference to image with the frame image of frame number 3,6.
Shown in Fig. 9 (b), at first, the pictorial data of frame number 0 is carried out intraframe coding obtain the I picture.At this moment, the pictorial data of frame number 0 is carried out the branch frame with memory etc., simultaneously as shown in figure 10, per 8 pixels * 8 row piecemeals carry out DCT with block unit and handle.In addition, the ODD that represents with solid line among the figure represents the scan line of odd field, and the EVEN that dots represents the scan line of even field.After handling the dct transform coefficient obtain by DCT and quantizing, carry out variable length code, the acquisition coded data with the quantization parameter of regulation.
For the frame image of frame number 1,, till frame image coding, all remain in the memory subsequently frame number 3 owing to use the two-way prediction coding of the frame image of frame number 0,3.Equally, for the frame image of frame number 2, also behind the frame image coding of frame number 3, encode.For the frame image of frame number 3, carry out the frame image of frame number 0 is encoded as the used the place ahead prediction of reference image, obtain P picture (Fig. 9 (b)).That is, the data of frame number 0 are moved compensation, the reference picture data of moving compensation and the difference (prediction error) of existing frame (frame of frame number 3) pictorial data are carried out the DCT processing with dynamic vector.Identical when carrying out variable length code with intraframe coding after dct transform coefficient quantized.
Then use the frame number 0,3 of having encoded I picture, P picture, the frame image of frame number 1,2 is carried out two-way prediction coding successively.This just shown in Fig. 9 (b), obtains two B pictures.Identical therewith later on, shown in Fig. 9 (b), be 6,4,5 with frame number ... frame image encode successively and obtain P picture, B picture, B picture ...When coding, use the frame sequential different to encode like this with the frame sequential of reality input.When decoding, be necessary the decoding order of coded data is got back to original order, with frame number 0,1,2 ... order output decoder data.Figure 11 illustrates the block diagram of so existing image decoding apparatus.And Figure 12 is the key diagram that divides frame in order to explanation, the branch frame during Figure 12 (a) expression non-interlace, the branch frame during Figure 12 (b) expression interlacing scan.
Coded data is added to coding buffer storage circuit 1.This coded data is with the coded sequence shown in Fig. 9 (b) pictorial data or prediction error to be carried out carrying out variable length code again after DCT handles and quantize.The coded data that 1 maintenance of coding buffer storage circuit has been imported is carried out the decoding processing time and is made up with the time in output processing time, and outputs to length-changeable decoding circuit 2.Length-changeable decoding circuit 2 carries out length-changeable decoding with coded data and outputs to inverse quantization circuit 3 and buffering control circuit 7.With buffer control circuit 7 control coding buffer storage circuit 1.
Re-quantization is carried out in output with 3 pairs of length-changeable decoding circuit 2 of inverse quantization circuit, carries out inverse DCT with inverse DCT circuit 4 and handles, and the DCT that gets back to the coding side handles preceding data.Now, input is as the I picture of the coded data of frame number 0.At this moment, the output of inverse DCT circuit 4 is reduction images of frame number 0, and the output with inverse DCT circuit 4 is added to frame memory 6 like this.
The output of inverse DCT circuit 4 is pixel datas of block unit, and frame memory 6 keeps the pixel data of 1 frame.Frame memory 6 is as described below four zones of M1~M4.When carrying out the non-interlaced demonstration, shown in Figure 12 (a), frame memory 6 is exported with the output of the sequence arrangement inverse DCT circuit 4 of frame and with raster order.And when carrying out the interlacing demonstration, shown in Figure 12 (b), frame memory 6 divides the data of odd field and the data of even field to arrange the output of inverse DCT circuit 4, and each is exported with raster order.The output of frame memory 6 is exported (Fig. 9 (c)) by switch 16 as decoded data.For P, B picture codec, also supply with frame memory 12 from the reduction pictorial data of the frame number 0 of inverse DCT circuit 4.
Moreover, when after the DCT piece divides frame, carrying out piecemeal, show if carry out non-interlaced, arrange because need not change the pixel of line direction, also can have as change output memory in proper order to keep 8 row (1 word group row) partial data.But show in order to carry out interlacing, owing to be necessary to be divided into odd field and even field dateout, so more memory will be arranged.This is because in most of the cases adopt frame memory to carry out the branch frame as the memory in order to the change DISPLAY ORDER usually.
Then carry out the P picture codec of frame number 3.At this moment, the output of inverse DCT circuit 4 is prediction errors.On the other hand, dynamic vector sample circuit 8 extracts the dynamic vector that is included in the length-changeable decoding circuit 2 and is added to moving compensating circuit 10, and the reduction pictorial data that moving compensating circuit 10 is read the I picture from frame memory 12 utilizes dynamic vector to move compensation.The output of moving compensating circuit 10 adds to adder 5 by switch 15.Adder 5 will obtain the reduction pictorial data of frame number 3 through the reduction pictorial data of the frame number 0 of moving compensation and prediction error addition from inverse DCT circuit 4.These data are supplied with frame memory 11.
Subsequently with the B picture codec of frame number 1.At this moment the output of inverse DCT circuit 4 also is the prediction error.Dynamic vector between the image of dynamic vector sample circuit 8 taking-up frame number 3 from length-changeable decoding output and the image of frame number 1 adds to moving compensating circuit 9, moving compensating circuit 9 uses dynamic vector, is moved compensation and is outputed to adder 13 by the reduction pictorial data of 11 pairs of frame numbers 3 of frame memory.Adder 13 is corresponding with the prediction pattern in when coding, and output addition that will moving compensating circuit 9,10 is supplied with adders 5 by switch 15.Adder 5 is added to the prediction error with the output of switch 15, obtains the reduction pictorial data of the B picture of frame number 1.After this pictorial data adds to frame memory 6 and carries out the branch frame, by switch 16 outputs (Fig. 9 (c)).
Follow B picture codec with frame number 2.At this moment, also with the output of inverse DCT circuit 4 and the output addition of switch 15.Obtain the reduction pictorial data of the B picture of frame number 2.This pictorial data is after adding to frame memory 6 and carrying out the branch frame, by switch 16 outputs (Fig. 9 (c)).Then shown in Fig. 9 (c), the reduction pictorial data that is stored in the frame number 3 in the frame memory 11 is exported as decoded data by DISPLAY ORDER by switch 14 and 16.
Then, repeat same operation, the output pictorial data (decoded data) of the decoding order reduction of Fig. 9 (c).Have again, consider the lap of storage and operating time in system on one side, control decoding processing on one side and handle with output.
Writing and reading of frame memory 6 when exporting obtaining interlacing below with reference to Figure 13 describes.Figure 13 (a) represents writing and reading of frame memory 6, the dividing method of the pictorial data of Figure 13 (b) expression I picture.
As mentioned above, frame memory 6 has four zones of M1~M4.For the memory that uses 1 frame part the pictorial data interlacingization of 1 frame is also exported, be necessary to write simultaneously and read.Therefore 1 frame image data are divided into four, four zones of M1~M4 are set simultaneously, control writing and reading of each zone.
That is, shown in Figure 13 (b), first pictorial data is divided into separately data A1, A2 by getting off on the picture.Also second pictorial data also is divided into separately data B1, B2 up and down by picture.Make data A1, A2 be stored in separately regional M1, M2, make data B 1, B 2Be stored in separately regional M3, M4.
When will be frame by frame during the coded data decoding of structured coding, from the decoding output of adder 5 be from the first piece row corresponding with the picture upper end to capable with the corresponding piece in picture lower end, be that unit exports in turn by piece.That is, at the image decoding apparatus of Figure 11, at 1 time decoder data A1, B1 is at next 1 field time decoded data A2, B2.The transverse axis of Figure 13 (a) is with field unit representation decode time and output time, and the longitudinal axis is represented the memory address of the regional M1~M4 of frame memory 6.The capacity of each regional M1~M4 be frame memory 6 capacity 1/4.
In 1 initial image duration, the data A1, the B1 that export from adder 5 write each memory block M1, M3 successively.Oblique line K1, the K3 of Figure 13 (a) represent writing to regional M1, M2.The data volume of data A1, B1 is 1/4 of 1 frame, writes the whole zone of regional M1, M3 at 1 field interval.
At next 1 field interval, write separately memory block M2, M4 successively from data A2, the B2 of adder 5 output.Oblique line K2, the K4 of Figure 13 (a) represent writing to regional M2, M4.The data volume of data A2, B2 is 1/4 of 1 frame, writes the whole zone of regional M2, M4 in 1 image duration.
Also carry out reading from regional M1 at this field interval.The oblique line R1 of Figure 13 (a) represents to press the write sequence sense data from the reading of regional M1 from regional M1, reads the total data A1 that is stored among the regional M1 during half-court.The hatched example areas of Figure 13 (a) represents that data are that deposit is in the address of frame memory 6 regulations.Particularly use the oblique line R2 of Figure 13 (a) be illustrated in this field interval back half also read data A2 among the storage area M2.The data A1, the A2 that have read at this field interval export as first data.
At the first half of next field interval, during oblique line K3, read the data B that writes the M3 zone 1, half reads the data B2 (oblique line R4) that writes regional M4 during oblique line K4 in the back.So, data B 1, B 2Export as second field data.
Repeat same writing and reading later on, each decoding output transform of frame is become each the interlacing output and the output of field.
Therefore, the P picture uses the reference picture of the place ahead frame to decode, and the memory in order to 1 frame that keeps reference picture when decoding is necessary.The B picture uses the reference picture decoding of the place ahead and rear frame, is necessary in order to the memory of 2 frames that keep these reference pictures.And then, as mentioned above, dividing frame with the output of adder 5 because encoding process is carried out with the DCT block unit, the memory that can carry out 1 frame of interlacing demonstration or non-interlaced demonstration is necessary.At this moment, the decoded data of I, P picture is because as the reference picture of B picture, and is stored in the frame memory 11,12,, the double branch frame of doing of these frame memories can be used from the reading of these frame memories 11,12 by control and output.But,, be not stored in the frame memory 11,12, so, be necessary to be provided with frame memory 6 for a minute frame because the decoded data of B picture need not image for referencial use yet.
Like this, in above-mentioned existing image decoding apparatus, in order to comprise the image coded data decoding of B picture, a plurality of memories are necessary, thereby exist circuit scale big, the problem that cost is high.
The purpose of this invention is to provide a kind of energy and cut down the necessary memory of image coded data that comprises the B picture in order to decoding, and the image decoding apparatus that can reduce circuit scale, reduce cost.
Image decoding apparatus of the present invention is equipped with:
Decoding mechanism, its input comprises the coded data of the two-way prediction coded data of using the place ahead and rear reference picture, with the block unit of regulation the coded data of being imported is decoded and the output decoder data;
Storing mechanism, the regulation that it has row to store the capacity of the above-mentioned decoded data of 1 frame is cut apart the storage area of the capacity of one of number, by decoding processing to above-mentioned two-way prediction coded data, add to from the decoded data of the configuration frame of above-mentioned decoding mechanism output and be stored in above-mentioned memory block, by read the data of having stored by DISPLAY ORDER, obtain interlacing output;
Controlling organization, it becomes picture segmentation afore mentioned rules to cut apart the split image zone of 1/2 several numbers with the vertical direction position accordingly, to cutting apart each split image data that the corresponding respectively above-mentioned decoded data in each several split image zones is listed as with above-mentioned first and second above-mentioned each regulation, control writing and reading of above-mentioned storing mechanism, by considering input and output time control the writing and reading of above-mentioned each split image data to above-mentioned storing mechanism, will with the common storage area of the corresponding a plurality of above-mentioned split image storage in different above-mentioned split images zone to above-mentioned storing mechanism, obtain interlacing by above-mentioned storing mechanism and export.
With decoding mechanism two-way prediction coded data is decoded in the present invention.Controlling organization becomes regulation to cut apart several 1/2 split image zone picture segmentation, and each regulation of first and second is cut apart writing and reading of each several split image Data Control storing mechanisms.At this moment, controlling organization is by arriving common storage area with a plurality of split image storage, and the data of storing a frame can reduce the storage area number in order to the storing mechanism that obtains interlacing output.Controlling organization reads out in data each split image data from storing mechanism, obtains interlacing output.
Fig. 1 illustrates the block diagram of an embodiment of image decoding apparatus of the present invention.
Fig. 2 is the key diagram in order to explanation embodiment work.
Fig. 3 is the key diagram in order to explanation embodiment work.
Fig. 4 is the block diagram of other embodiment of expression the present invention.
Fig. 5 is the key diagram of work of the embodiment of key diagram 4.
Fig. 6 is the key diagram of key diagram 4 embodiment work.
Fig. 7 is the block diagram of other embodiment of expression the present invention.
Fig. 8 is the key diagram of the work of key diagram 7 embodiment.
Fig. 9 is the key diagram of explanation prediction coding.
Figure 10 is the key diagram in order to the explanation piecemeal.
Figure 11 is the block diagram of the existing image coding device of expression.
Figure 12 is the key diagram that divides frame in order to explanation.
Figure 13 is the key diagram in order to the interlacing conversion that existing example is described.
Below with reference to accompanying drawings embodiments of the invention are described.Fig. 1 is the block diagram of expression image decoding apparatus one embodiment of the present invention.Structural detail identical with Figure 11 in Fig. 1 is represented with prosign.
Coded data is supplied with coding buffer storage circuit 1.This coded data becomes by DCT processing, quantification treatment and variable length code processing, and it has the P picture of the reference picture of handling the I picture, use the place ahead or the rear frame that produce in the frame and uses the B picture of the reference picture of bidirectional frame.And coded data is also included within dynamic vector information used when processing P, B picture.And the DCT processing is to carry out with the block unit that obtains with piecemeal after the frameization.
The coded data that the maintenance of coding buffer storage circuit I is imported is carried out the combination and the output of decoding processing time and output time.The output of coding buffer storage circuit 1 adds to length-changeable decoding circuit 2.Length-changeable decoding circuit 2 is handled the variable length code that makes the coded data of being imported revert to the coding side by length-changeable decoding and is handled preceding data, outputs to buffer control circuit 7, inverse quantization circuit 3, reaches dynamic vector sample circuit 8.Buffer control circuit 7 is according to the output control coding buffer storage circuit 1 of length-changeable decoding circuit 2.
Dynamic vector sample circuit 8 for P, B picture, takes out the dynamic vector that is included in the length-changeable decoding output and outputs to moving compensating circuit 9,10.Inverse quantization circuit 3 carries out the re-quantization processing with the data of being imported and adds to inverse DCT circuit 4, and inverse DCT circuit 4 outputs to adder 5 after re-quantization output carrying out inverse DCT is handled.
The output of switch 15 also adds to adder 5.Switch 15 is added to adder 5 with 0 in the output of inverse DCT circuit 4 during according to the I picture, output with following moving compensating circuit 9,10 1 sides during according to the P picture is added to adder 5, and the output that will move compensating circuit 9,10 or following adder 13 during according to the B picture offers adder 5.Adder 5 when outputing to frame memory 11,12, also outputs to memory 21 by the output of inverse DCT circuit 4 and the output addition of switch 15 are made image restoration.
Frame memory 11,12 is stored 22 controls of device control circuit and writes and read, and keeps becoming the I of reference picture, the restored map image data of P picture.Frame memory 11,12 will output to moving compensating circuit 9,10 in the P of correspondence, the reference picture data that the decoding of B picture regularly keeps.Moving compensating circuit 9,10 will move the output of compensation back according to the dynamic vector from vector sample circuit 8 from the reference picture data of frame memory 11,12 respectively.The output of moving compensating circuit 9,10 is also supplied with adder 13 when supplying with switch 15.The output phase adduction that adder 13 corresponding predictive modes will move compensating circuit 9,10 outputs to switch 15.
Memory 21 is divided into a plurality of storage areas, and each zone has the regulation of storage 1 frame image data capacity (hereinafter referred to as the frame capacity) to cut apart the capacity of one of number (following picture segmentation number * 1/2).In addition, the example that constitutes memory 21 by five regional M1~M5 of 1/8 capacity shown in Figure 1 with frame capacity.That is, in this case, the capacity of memory 21 is 5/8 of frame capacity.Memory 21 is as described below, writes and reads with memorizer control circuit 22 control, and storage is the decoded data of the B picture of input successively, calls over and output to switch 16 by interlacing.
On the other hand, for I, P picture, use the restored map image data that is stored in frame memory 11,12.The control of frame memory 11,12 usefulness memorizer control circuits writes and reads, and the restored map image data of being stored is read and output to switch 14 by interlace sequence.Switch 14 is changed accordingly with the order of visual output frame, will output to switch 16 from the pictorial data of frame memory 11,12.Switch 16 is changed accordingly with the order of visual output frame, and a series of frame reduction pictorial data is exported as decoded data.
Memorizer control circuit 22 is cut apart the 1st and the 2nd along the above-below direction of each picture with the picture segmentation number of regulation, to each corresponding split image data of each zone of having cut apart, carry out writing to memory 21.For example, the picture segmentation number is 4, and the split image data corresponding with the 1st the 1st~the 4 four zone are respectively A1~A4, and the split image data corresponding with the 2nd the 1st~the 4 four zone are respectively B1~B4.At this moment, for example, memorizer control circuit 22 is with the regional M1 of split image data A1, A3, A4 write memory 21, and B1 writes regional M2 with the split image data, and B2 writes regional M3 with the split image data.And then memorizer control circuit 22 is one group with separation graph image data A2 and split image data A3 or A4 and writes regional M4 or M5, remaining split image data A3 or A4 are write regional M5 or M4.
Describe with reference to the work of the key diagram of Fig. 2 below the embodiment of formation like this.Fig. 2 (a) illustrates writing and reading of memory 21, and Fig. 2 (b) illustrates the dividing method of the pictorial data of 1 picture.And in Fig. 2, represent the data of odd field with oblique line, represent the data of even field with netting twine.
Decoding processing is with identical in the past.That is, coded data is input to coding buffer storage circuit 1.Coded data has I, P, B picture, for example uses the frame sequential input of Fig. 9 (b).Coding buffer storage circuit 1 is considered encoding process time and output time, keeps the coded data of having imported and outputs to length-changeable decoding circuit 2.
With length-changeable decoding circuit 2 coded data is carried out length-changeable decoding, carry out re-quantization, carry out inverse DCT with inverse DCT circuit 4 and handle, turn back to the data before coding side DCT handles and supply with adder 5 with inverse quantization circuit 3.These processing are carried out with block unit.
In the coded data of being imported is that switch 15 added to adder 5 with 0 when the I picture was carried out coded data.Therefore, adder 5 outputs to frame memory 12 with the output of inverse DCT circuit 4 like this.By frame memory 12, the decoded data of each piece carries out 1 frame savings, regularly reads by DISPLAY ORDER and exports by switch 14,16 in the output of regulation.
In the coded data of being imported is that the output of length-changeable decoding circuit 2 also added to dynamic vector sample circuit 8 when the P picture was carried out coded data.With dynamic vector sample circuit 8, take out the vector in the coded data that is included in the P picture, offer moving compensating circuit 10.
Frame memory 12 keeps the decoded data of I picture as with reference to image, moves the data that compensating circuit 10 is read frame memory 12, uses dynamic vector to move compensation.These data of having carried out the reference picture of moving compensation are added to adder 5 by switch 15.The output of inverse DCT circuit 4 is decoded prediction errors, adder 5 by will from the reference picture data of switch 15 therewith the addition of prediction error restore pictorial data.This pictorial data stores frame memory 11 into.
Import coded data subsequently based on the B picture.At this moment, the output of length-changeable decoding circuit 2 also offers dynamic vector sample circuit 8 when offering inverse quantization circuit 3 and inverse DCT circuit 4.By the prediction error of inverse DCT circuit 4 before adder 5 output DCT handle.On the other hand, dynamic vector sample circuit 8 takes out the dynamic vector corresponding with reference picture and outputs to each moving compensating circuit 9,10 from length-changeable decoding output.In addition, because the difference of prediction pattern is only extracted a certain dynamic vector sometimes.
Frame memory 12,11 keeps the restored map image data of I picture, P picture as the reference pictorial data, moving compensating circuit 9,10 is read these restored map image datas, moves compensation and outputs to switch 15 and adder 13 according to dynamic vector.That is, moving compensating circuit 9,10 is by dynamic vector revisal and the corresponding piecemeal position of decoded data by the specified block of inverse DCT circuit 4 outputs, carries out the moving reference picture data that compensate as the blocks of data of the piecemeal position that will proofread and correct and exports.The output phase adduction that adder 13 will be moved compensating circuit 9,10 outputs to switch 15.Switch 15 is selected the output of moving compensating circuit 10 when the prediction direction is the place ahead, select the output of moving compensating circuit 9 when being the rear, selects the output of adder 13 when being two directions, outputs to adder 5 as the reference picture data of moving compensation.
Like this, adder 5 will be restored the pictorial data of B picture and output to memory 21 with each block unit from the blocks of data of inverse DCT circuit 4 with from the reference picture data addition of the block unit of switch 15.
With the blocks of data of block unit output from adder 5.That is, capable from the capable piece of picture upper endpiece in turn with the data of block unit output B picture to the picture lower end by adder 5.Now, if the picture segmentation number is 4, by adder 5 at first at split image data A1, the B1 of 1/2 field interval output map 2 (b) of regulation, at next 1/2 field interval output split image data A2, B2, at next 1/2 field interval output split image data A3, B3 again, at next 1/2 field interval output split image data A4, B4 again.
On the other hand, memory 21 has five regional M1~M5.The capacity of each regional M1~M5 is 1/8 of a frame capacity.Thereby in predetermined timing, each regional M1~M5 can store each split image data A1~A4, any one data among B1~B4.
Fig. 2 (a) transverse axis is a unit interval, and the storage address corresponding with each zone of M1~M5 is illustrated in the longitudinal axis.Shown in this Fig. 2 (a), during adder 5 output split image data A1, B1, promptly at the T of Fig. 2 (a) 0The first half during this time, memorizer control circuit 22 produce M1, the M2 zone corresponding address with memory 21 in turn.Like this, as the oblique line K1 of Fig. 2 (a), shown in the K3, at T 0Preceding half 1/2 field interval during this time is to M1, and the M3 zone writes split image data A1, B1.
T below 0During this time later half is from adder 5 output split image data A2, B2.Memorizer control circuit 22 at this moment between appointed area M4, M3 corresponding address successively.Therefore, shown in oblique line K2, the K4 of Fig. 2 (a), regional M4, M3 are write split image data A2, B2.
The oblique line of Fig. 2 (a) partly represent split image data A1~A4 be stored in memory 21 during, netting twine represents that partly the split image data storing is during memory 21.Memorizer control circuit 22 is shown in the oblique line R1 of Fig. 2 (a), and the initial moment during following T1 is read the address to regional M1 appointment successively.Shown in Fig. 2 (a), during initial 1/4 during the T1 below, read split image data A1 thus, by switch 16 outputs from regional M1.With the address of reading of memorizer control circuit 22 appointed area M4, read split image data A2 and output during below during the T1 1/4.
Preceding half during this T1 also is from adder 5 output split image data A3, B3.Memorizer control circuit 22 also produces in the address with what oblique line K5 represented and writes the address regional M1 being produced reading of representing with above-mentioned oblique line R1.Make these read the address and write the address and for example cut apart generation by the time.That is, the address is read and write to preceding partly M1 zone successively specified of memorizer control circuit 22 during T1, Yi Bian read split image data A1, Yi Bian store split image data A3 into regional M1.In addition because read-out speed is 2 times of writing rate, so before upgrading regional M1, read split image data A1 with split image data A3.And the preceding partly also address of appointed area M5 successively during T1, B3 stores regional M5 into the split image data.
Equally, later half during T1 specified regional M1 and to be read the address and to write the address, at 1/4 field interval read split image data A3 (oblique line K6), on one side at 1/2 field interval write split image data A4 (oblique line R4) on one side.Also appointed area M4 write the address, write the split image data B that represents with oblique line K8 4Also last 1/4 field interval during T2 produces the address that writes to regional M1, and uses reading of split image data A4 that oblique line R4 represents.Like this, during T1, read split image data A1~A4 successively, form first image.
Preceding half during the T2 below read split image data B1 (oblique line R5) at 1/4 initial field interval from regional M2, and 1/4 field interval is below read split image data B2 (oblique line R6) from regional M3.Preceding half during this T2 is with T 0The same during this time, respectively will be from the split image data A1 of adder 5 outputs, B1 writes regional M1, M2.
Later half during T2 from adder 5 output split image data A2, B2.At T 0During this time with split image data A 2Be stored in regional M4, later half owing to not reading the split image data B4 that is stored in regional M4, so split image data A2 writes regional M5 during T2.That is, memorizer control circuit 22 later half during T2 specified regional M5 and to be read the address and to write the address, shown in oblique line R7, K10, on one side sense data R3, write split image data A2 on one side.Last 1/4 field interval during T2 is read split image data B4 from regional M4.Like this, during T2, read split image data B1~B4 in turn, form the 2nd image.
During the T3 below,, read split image data A1~A4 in the address of reading of per 1/4 appointed area M1, M5, M1, M1.Also preceding half during T3 produces regional M1, and M4 writes the address and writes split image data A3, B3, later half, produces regional M1, and M5 writes the address and writes split image data A4, B4.
During T4,, read split image data B1~B4 in turn from these zones in the address that writes that each 1/4 field interval all produces regional M2~M5.Repeat same operation later on.
Like this, use the memory 21 of frame capacity 5/8 capacity interlacing to export the B picture.
Like this, in the present embodiment, the split image data in a plurality of zones on the picture have been written in a storage area.Determine accordingly that with time of each split image writing data into memory 21 with from time that memory 21 is read and the field under the split image data and the position on the picture some split image data only is being stored in the memory 21 in the time of lacking.Present embodiment is because in a plurality of split image data of 1 area stores of memory 21, from Fig. 2 (a) and Fig. 3 (a) more as can be known, do not make and reduce during memory-aided, memory span is reduced.Split image data B3 is necessary to remain in the memory during identical with split image data B4, and at the split image data B that finishes to next frame that reads from the split image data B3 of regulation frame 4Write beginning during, exist to write split image data A 2And the enough and to spare time of only reading.
Reason in view of the above is with split image data B 3Be combined into one group with read the split image data A2 that begins to write when finishing from split image data B3, these group data and split image data B4 are alternately write regional M4, M5 every 1 frame.Then split image data A2 is write and the identical regional M5 of split image data A3 that reads end, split image data B4 is write regional M4 after these split image data A2 reads end.
For example as shown in the regional M1, utilize the different of read-out speed and writing rate, make to produce during same to write the address and read the address, on one side sense data write on one side, the utilance of memory 21 is further improved.
This just can not stop the output of decoded pictorial data, uses memory effectively, with the pictorial data of little memory span interlacing conversion 1 frame unit.The capacity of memory 21 each regional M1~M5 is 1/8th of a frame capacity, the capacity of memory 21 can be reduced to the capacity of 0.625 frame.For example, when adopting present embodiment in the PAL mode, for example using with decoder, the memory of 16M bit capacity constitutes all necessary memory.
Although exemplify out split image data A1, A3, A4 write regional M1, split image data B1, B2 write each regional M2, and M3 also can import other zone, and memory has 5 zones, obviously are assigned to any one zone and write all and be fine.
Further, write split image data A1~A4, the pattern of B1~B4 is not necessarily limited to the pattern of Fig. 2 (a).Fig. 3 (a)~(c) be in order to illustrate each other write the key diagram of pattern.Fig. 3 (a) illustrates the identical pattern with Fig. 2 (a), and Fig. 3 (b), (c) illustrate other pattern.
For the split image data A1~A4 to the same area, the storage time of B1~B4 is not overlapping, as long as the zone of each data of decision storage is just passable.For example, owing to be stored in reading shown in Fig. 3 (a) of split image data A1 among the regional M1 and be later half since first frame, thus can will proceed to from the output of adder 5 this constantly later split image data A3, B3, A4, B4 write regional M1.At this moment, obviously with split image data A3, that B3 writes fashionable efficient is higher than split image data A4, B4 are write this regional efficient.
When considering efficient, write shown in the following tabulation 1 of two continuous data combinations of the same area.
Table 1
Present data The data that may write Present data The data that may write
????A1 ????A3 ????B3 ????A3 ????A4 ????B4
????B1 ????(A2) ????(B2) ????B3 ????A2 ????(B2)
????A2 ????A4 ????B4 ????A4 ????A1 ????(B1)
????B2 ????(A2) ????B2 ????B4 ????A3 ????B3
And then because split image data B1, B2 storage time are long, split image data B1, B2 write the zone of regulation separately.Consider the pattern of Fig. 3 according to these conditions.For example, Fig. 3 (b) is the example that writes split image data B3 for regional M1 after split image data A1.Also as mentioned above, split image data B3 and split image data A2 are combined into one group, change the zone that writes with regional M1 and regional M4 for these group data.And Fig. 3 (c) is the example that writes split image data A3 after split image data A1.Even in this example, also split image data B3 and split image data A2 are combined into one group, for the data of this group, use regional M4, the zone that the M5 alternate writes.
And for example, split image data A1 and split image data B1 its to write the time started be consistent.Thereby, the regional conversion of data that can the zone that write the following data of split image data A1 is following with writing split image data B1, this is obviously easily to see.For other data that write the time started unanimity also is same.
Fig. 4 is the block diagram of other embodiment of the present invention.In Fig. 4, the structural detail identical with Fig. 1 repeats no more with identical label.
Present embodiment adopts memory 31 to replace the memory 21 of Fig. 1.Memory 31 is divided into six zones of M1~M6, and all there is 1/8 capacity of frame capacity in each zone.Promptly at this moment the capacity of memory 31 is 6/8 of frame capacity.22 controls of memory 31 usefulness memorizer control circuits write and read, and storage is the decoded data of the B picture of input successively, reads and be input to switch 16 by interlace sequence.
Describe with reference to the work of the key diagram of Fig. 5 below the embodiment of such formation.Fig. 5 (a) and (b) are (b) corresponding with Fig. 2 (a) respectively.Fig. 5 (a) represents writing and reading of memory 31, the dividing method of the pictorial data of Fig. 5 (b) expression 1 picture.Even in Fig. 5, also represent the data of odd number, represent the data of even field with netting twine with oblique line.
In the embodiment in figure 1, from readout time of the data in regulation zone with many to consistent pattern of the write time of other data in this zone.To this, present embodiment is to finish the pattern that obtains surplus to writing from the same area is read.Therefore, make memory control transfiguration easy, the restriction in the design of energy mitigation circuits.
In any zone, begin to set official hour between the write time if read concluding time and next data in the data of being stored, then write the combination of two continuous datas of the same area, become shown in following table 2.Bracket inner digital is represented frame number.
Table 2
Present data The data that may write Present data The data that may write
????A1(n) ????A4(n) ????B4(n) ????A3(n) ????A1(n+1) ????B1(n+1)
????B1(n) ????A2(n+1) ????B2(n+1) ????B3(n) ????A3(n+1) ????B3(n+1)
????A2(n) ????A4(n) ????B4(n) ????A4(n) ????A1(n+1) ????B1(n+1)
????B2(n) ????A2(n+1) ????B2(n+1) ????B4(n) ????A3(n+1) ????B3(n+1)
Fig. 5 is the example that split image data A1 and split image data A4 is alternately write regional M1.Only split image data B2, B3 are write regional M4, M5 respectively.Order by split image data A3, B1, A2, B4 writes regional M2 with data.Also the order by split image data B1, A2, B4, A3 writes regional M3 with data, by the order of split image data A2, B4, A3, B1 data is write M6.So shown in Fig. 5 (a), the interlacing conversion of certain hour can be arranged during reading and writing.
Also the embodiment with Fig. 1 is the same in the present embodiment, will not be defined in the pattern of Fig. 5 (a).Fig. 6 be the expression present embodiment other write the key diagram of pattern.
(b) any one of Fig. 6 (a) all is the pattern that is subject to above-mentioned table 2.When the data that write zones of different write the time started when consistent, also equally in these zones also can exchange the data that write with the embodiment of Fig. 1.
Therefore, in the present embodiment, constitute memory 43 and can carry out the interlacing conversion with 0.75 frame capacity.
Fig. 7 is the block diagram of other embodiment of expression the present invention.Structural detail identical with Fig. 4 in Fig. 7 is not elsewhere specified with identical symbol.
Present embodiment replaces memory 31 with memory 41.Memory 41 is divided into three zones of M1~M3, and all there is the capacity of frame capacity 1/4 in each zone.Promptly at this moment the capacity of memory 41 is 3/4 of frame capacity.22 controls of memory 41 usefulness memorizer control circuits write and read, and storage is the decoded data of the B picture of input successively, reads and be input to switch 16 by interlace sequence.
Describe with reference to the work of the key diagram of Fig. 8 below the embodiment of formation like this.Fig. 8 (a), (c) are corresponding with Fig. 5 (a) and (b) respectively.Fig. 8 (a) represents writing and reading of memory 41, the dividing method of the pictorial data of Fig. 8 (c) expression 1 picture.Other writes pattern and Fig. 8 (b) is illustrated in that present embodiment considers.The data of also representing odd field in Fig. 8 with oblique line are also represented the data of even field with netting twine.
In the embodiment of Fig. 4, making the image Segmentation number is 4, and the pictorial data of a frame is divided into A1~A4, and 8 split image data of B1~B4 are all controlled writing to memory to each data of having cut apart.Can use memory effectively more though the picture segmentation number is big more, after the picture segmentation number became greatly, memory control complicated.For the ease of control storage, present embodiment illustrates and the picture segmentation number is set at 2 example.
Memorizer control circuit 22 is cut apart the 1st and the 2nd along the above-below direction of picture respectively, will with the 1st 2 corresponding split image data A1, the A2 in zone and with the 2nd 2 regional corresponding split image data B1, the regional M1~M3 of B2 write memory 41.Split image data A1, it is shorter that A2 is stored in the time of memory 41, split image data A1 read time started and split image data A2 to write the time started consistent.Also owing to be 2 times of writing rate to the read-out speed of each data, thus can be with split image data A1, and A2 writes same zone.
Memorizer control circuit 22 is with split image data A1, and A2 writes regional M1.Also with split image data B1, B2 writes regional M2, M3 respectively to memorizer control circuit 22.Therefore shown in Fig. 8 (a), can also export by interlacing transform frame image.
Fig. 8 (b) is with split image data A1, and B2, A2 form one group, and the limit writes at regional M1 and regional M2 conversion limit, split image data B1 is write the example of regional M2.At this moment also can normally carry out the interlacing conversion.
So have in this embodiment, by making the effect of the easy control storage of the little energy of picture segmentation number.
According to above-mentioned the present invention, have and to cut down the effect that makes the image coded data that contains the B picture decode necessary memory, reduce circuit scale, reduce cost.

Claims (6)

1. image decoding apparatus is characterized in that:
Decoding mechanism, its input comprises the coded data of the two-way prediction coded data of the reference picture that uses the place ahead and rear, the coded data of being imported is used the block unit decoding and the output decoder data of regulation;
Storing mechanism, it has a plurality of regulations with capacity of the above-mentioned decoded data of storage 1 frame to cut apart the memory block of the capacity of one of number, by decoding processing to above-mentioned two-way prediction coded data, provide by the decoded data of the configuration frame of above-mentioned decoding mechanism output and store above-mentioned memory block into, obtain interlacing output by read the data of being stored by DISPLAY ORDER;
Controlling organization, it becomes picture segmentation afore mentioned rules to cut apart the split image zone of several 1/2 numbers with the vertical direction position accordingly, to as cutting apart each split image data that the corresponding above-mentioned decoded data in several each split image zone is listed as with above-mentioned each regulation of first and second respectively, control writing and reading of above-mentioned storing mechanism, by considering output control input time the writing and reading of above-mentioned each split image data to above-mentioned storing mechanism, will with the common storage area of the corresponding a plurality of above-mentioned split image storage in different above-mentioned split images zone to above-mentioned storing mechanism, obtain interlacing from above-mentioned storing mechanism and export.
2. according to the said image decoding apparatus of claim 1, it is bigger than the number of the storage area of above-mentioned storing mechanism to it is characterized in that afore mentioned rules is cut apart number.
3. according to the said image decoding apparatus of claim 1, it is characterized in that it is 4 that afore mentioned rules cuts apart several 1/2;
Above-mentioned storing mechanism has 1/8 five zones of its capacity for the capacity of storage 1 frame above-mentioned decoded data.
4. according to the said image decoding apparatus of claim 1, it is characterized in that it is 4 that afore mentioned rules cuts apart several 1/2;
Above-mentioned storing mechanism has 1/8 six zones of its capacity for the capacity of storage 1 frame above-mentioned decoded data.
5. according to the said image decoding apparatus of claim 1, it is characterized in that it is 2 that afore mentioned rules cuts apart several 1/2;
Above-mentioned storing mechanism has 1/4 three zones of its capacity for the capacity of storage 1 frame above-mentioned decoded data.
6. according to the said image decoding apparatus of claim 1, it is characterized in that above-mentioned coded data is the encoding image signal with the PAL mode.
CN 96107280 1995-04-14 1996-04-15 Image decoding device Pending CN1154631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 96107280 CN1154631A (en) 1995-04-14 1996-04-15 Image decoding device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP089085/95 1995-04-14
CN 96107280 CN1154631A (en) 1995-04-14 1996-04-15 Image decoding device

Publications (1)

Publication Number Publication Date
CN1154631A true CN1154631A (en) 1997-07-16

Family

ID=5119568

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 96107280 Pending CN1154631A (en) 1995-04-14 1996-04-15 Image decoding device

Country Status (1)

Country Link
CN (1) CN1154631A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1729690B (en) * 2002-11-13 2010-05-26 索尼电子有限公司 Method of real time MPEG-4 texture decoding for a multiprocessor environment
CN101924935B (en) * 2003-09-07 2012-12-05 微软公司 Advanced bi-directional predictive coding of interlaced video

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1729690B (en) * 2002-11-13 2010-05-26 索尼电子有限公司 Method of real time MPEG-4 texture decoding for a multiprocessor environment
CN101924935B (en) * 2003-09-07 2012-12-05 微软公司 Advanced bi-directional predictive coding of interlaced video

Similar Documents

Publication Publication Date Title
CN1134991C (en) Digital video signal inter-block interpolative predictive encoding/decoding apparatus and method providing high efficiency of encoding
EP1730964B1 (en) Video coding system providing separate coding chains for dynamically selected small-size or full-size playback
CN1151684C (en) Moving-picture coding-decoding apparatus and method, and moving-picture code recording medium
CN1200568C (en) Optimum scanning method for change coefficient in coding/decoding image and video
CN1224268C (en) Moving picture coding apparatus and moving picture decoding apparatus
CN1100872A (en) Apparatus and method for reproducing a prediction-encoded video signal
CN1233160C (en) Method for adaptive encoding and decoding sports image and device thereof
CN1968418A (en) System and method for image data processing using hybrid type
CN1893652A (en) Video encoding method and apparatus, and video decoding method and apparatus
CN1627824A (en) Bitstream-controlled post-processing filtering
JP4768728B2 (en) Method and apparatus for encoding a block of values
CN1495674A (en) Interpolation device for motion vector compensation and method
Sun et al. Real-time implementation of a new low-memory SPIHT image coding algorithm using DSP chip
US20100111432A1 (en) Device and Method for Coding a Transformation Coefficient Block
CN1615025A (en) Apparatus capable of performing both block-matching motion compensation and global motion compensation and method thereof
CN1574943A (en) Apparatus and method for controlling reverse-play for digital video bitstream
CN102113327B (en) Image encoding device, method, and integrated circuit
CN1186943C (en) Apparatus and method of coding/decoding and storage medium storing coded signal
CN1214648C (en) Method and apparatus for performing motion compensation in a texture mapping engine
CN1194544A (en) Coding and decoding device with movement compensation
US7929777B2 (en) Variable length decoding device, variable length decoding method and image capturing system
CN1112654C (en) Image processor
CN1271859C (en) Image processor
CN1268136C (en) Frame field adaptive coding method based on image slice structure
CN1143553C (en) Apparatus and method of coding/decoding moving picture and storage medium storing moving picture

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C01 Deemed withdrawal of patent application (patent law 1993)
WD01 Invention patent application deemed withdrawn after publication