CN115346875A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN115346875A CN115346875A CN202110533845.7A CN202110533845A CN115346875A CN 115346875 A CN115346875 A CN 115346875A CN 202110533845 A CN202110533845 A CN 202110533845A CN 115346875 A CN115346875 A CN 115346875A
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- 238000000034 method Methods 0.000 title claims abstract description 108
- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 364
- 238000000059 patterning Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims description 67
- 238000005530 etching Methods 0.000 claims description 49
- 230000000873 masking effect Effects 0.000 claims description 31
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region; forming a first mask material layer on the layer to be etched; forming a plurality of openings in the first mask material layer on the first region; forming a first mask structure in each opening, and forming a plurality of second mask structures which are separated from each other on the first mask material layer on the second area; and patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure. The forming method can improve the existing semiconductor structure.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous progress of semiconductor integrated circuit manufacturing technology, the performance is improved along with the progress of miniaturization of devices. In more and more advanced processes, it is required to realize as many devices as possible in as small an area as possible.
In the advanced process node, a semiconductor structure with a smaller critical dimension is formed by adopting a light source with a shorter wavelength, a multiple patterning process and the like, so that more devices can be realized in a smaller area, and the integration level of the semiconductor device is improved.
However, the performance of semiconductor devices still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of a semiconductor device.
In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region; forming a first mask material layer on the layer to be etched; forming a plurality of openings in the first mask material layer on the first region; forming a first mask structure in each opening, and forming a plurality of second mask structures which are separated from each other on the first mask material layer on the second area; and patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure.
Optionally, the material of the first mask structure includes silicon or germanium.
Optionally, the method for forming the first mask structure in each opening and forming a plurality of second mask structures separated from each other on the first mask material layer on the second region includes: before the opening is formed, a plurality of first sacrificial structures which are separated from each other are formed on the first mask material layer on the second area; forming a second mask material film on the surfaces of the first sacrificial structure and the first mask material layer; after forming the opening, forming a third mask material layer in the opening and on the surface of the second mask material film, wherein the third mask material layer is higher than or flush with the top surface of the first sacrificial structure; etching the first sacrificial structure and the third mask material layer until the surface of the first mask material layer is exposed to form the first mask structure; and after the first mask structure is formed, removing the second mask material film on the surface of the first mask material layer by adopting an anisotropic etching process to form the second mask structure.
Optionally, a material of the third mask material layer is the same as a material of the first sacrificial structure, and a material of the third mask material layer is different from a material of the second mask material film.
Optionally, the forming process of the first sacrificial structure includes a multiple patterning process.
Optionally, the method for forming a plurality of openings in the first mask material layer on the first region includes: forming an opening mask layer on the second mask material film, wherein the opening mask layer exposes the second mask material film on the first area; and etching the second mask material film and the first mask material layer by taking the opening mask layer as a mask so as to form the opening.
Optionally, the method for patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure includes: and etching the first mask material layer by taking the second mask structure as a mask until the surface of the layer to be etched is exposed, and forming a plurality of mutually-separated third mask structures on the second area.
Optionally, the first mask material layer includes: the mask structure comprises a lower first mask material layer and an upper first mask material layer located on the surface of the lower first mask material layer, wherein the lower first mask material layer is made of silicon nitride, an opening is located in the upper first mask material layer, and the lower first mask material layer is exposed at the bottom of the opening.
Optionally, the method for patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure further includes: and etching the first mask material layer by taking the second mask structure as a mask, and simultaneously etching the first mask material layer by taking the first mask structure as a mask to form a fourth mask structure between the first mask structure and the layer to be etched.
Optionally, the layer to be etched includes: a substrate and a second sacrificial material layer on the substrate.
Optionally, the method for patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure further includes: and etching the second sacrificial material layer by taking the first mask structure and the third mask structure as masks, forming a plurality of mutually-separated second sacrificial structures in the first area, and forming a plurality of mutually-separated third sacrificial structures in the second area.
Optionally, the method for patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure further includes: forming a first side wall on the side wall surface of the second sacrificial structure, and forming a second side wall on the side wall surface of the third sacrificial structure; after the first side wall and the second side wall are formed, removing the second sacrificial structure and the third sacrificial structure; after the second sacrificial structure and the third sacrificial structure are removed, the substrate of the first area is patterned by the first side walls, the substrate of the second area is patterned by the second side walls, a plurality of first fins which are separated from each other are formed in the first area, and a plurality of second fins which are separated from each other are formed in the second area.
Optionally, the layer to be etched further includes: a second layer of masking material located between the substrate and the second layer of sacrificial material.
Optionally, the method for patterning the substrate in the first area with the first sidewall and patterning the substrate in the second area with the second sidewall includes: etching the second mask material layer of the first region by taking the first side walls as masks, etching the second mask material layer of the second region by taking the second side walls as masks until the surface of the substrate is exposed, forming a plurality of mutually-separated first fin part mask structures in the first region, and forming a plurality of mutually-separated second fin part mask structures in the second region; and etching the substrate of the first region by taking the first fin part mask structure as a mask, and etching the substrate of the second region by taking the second fin part mask structure as a mask to form the first fin and the second fin.
Correspondingly, the technical solution of the present invention further provides a semiconductor structure formed by the above method, including: the layer to be etched comprises a first region and a second region, and the layer to be etched comprises a substrate, a second mask material layer positioned on the substrate and a second sacrificial material layer positioned on the second mask material layer; a first mask material layer positioned on the layer to be etched; a plurality of openings in the first mask layer over the first region; a first mask structure located within each opening; and a plurality of mutually-separated second mask structures positioned on the first mask material layer on the second area.
Correspondingly, the technical solution of the present invention further provides another semiconductor structure formed by the above method, including: the substrate comprises a first area and a second area, wherein a plurality of mutually-discrete first fins are arranged on the substrate in the first area, a plurality of mutually-discrete second fins are arranged on the substrate in the second area, and the distance between the side walls of the adjacent first fins is smaller than that between the side walls of the adjacent second fins; a first fin portion mask structure on the first fin; a second fin mask structure on the second fin.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure, due to the fact that the plurality of openings are formed in the first mask material layer on the first area and the first mask structure is formed in each opening, the mask structure with the large height-width ratio does not need to be formed to achieve pattern transmission in the pattern transmission process of the first mask structure, the risk that the first mask structure bends, deforms or falls down is reduced, the appearance of the first mask structure is improved, the pattern transmission can be better carried out on the layer to be etched, and therefore the performance and the reliability of the formed semiconductor structure are improved. Furthermore, by forming the first mask structure in the opening, the degree of freedom in selecting the material of the first mask structure can be increased, and therefore, by using a hard mask material having higher hardness as the material of the first mask structure, pattern transfer to the layer to be etched can be performed better, and thus, the performance and reliability of the formed semiconductor structure can be improved.
Drawings
FIGS. 1-3 are schematic cross-sectional views illustrating steps in a method of forming a semiconductor structure;
fig. 4 to fig. 15 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance and reliability of existing semiconductor structures still remain to be improved, and are now analyzed in connection with specific embodiments.
Fig. 1 to 3 are schematic cross-sectional views of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a layer to be etched 100 is provided, where the layer to be etched 100 includes a first region I and a second region II.
With continued reference to fig. 1, a first sacrificial material layer 110 is formed on the layer to be etched 100.
With continued reference to fig. 1, a plurality of mutually discrete first mask structures 120 are formed on the first sacrificial material layer 110 on the first region I.
Referring to fig. 2, after forming the first mask structure 120, a second mask patterning layer (not shown) is formed on the first sacrificial material layer 110, wherein the second mask patterning layer includes a second mask material layer and a lithography pattern layer located on a surface of the second mask material layer in the second region II; and etching the second mask material layer by using the photoetching pattern layer as a mask until the surface of the first sacrificial material layer 110 is exposed, and forming a second mask structure 130 in the second area II.
The first mask structure 120 is formed in the first region I, and the second mask structure 130 is formed in the second region II, so as to transfer different patterns to the first region I and the second region II, respectively, thereby forming device structures with different sizes or different pitches in the first region I and the second region II according to design requirements.
Referring to fig. 3, the first mask structure 120 and the second mask structure 130 are used as masks, the first sacrificial material layer 110 is etched until the surface of the layer to be etched 100 is exposed, a first sacrificial layer 121 is formed on the first region I, and a second sacrificial layer 131 is formed on the second region II.
The first sacrificial layer 121 and the second sacrificial layer 131 are used as core structures (cores) of a multi-patterning process to transfer a pattern with a smaller critical dimension to the layer to be etched 100, thereby improving the integration level of the semiconductor structure.
However, in the above method, in order to ensure the accuracy of the pattern of the lithography pattern layer, the second mask structure 130 is easily bent and fallen down, so that the second sacrificial layer 131 is formed with poor morphology, or it is difficult to transfer the pattern to form the second sacrificial layer 131, resulting in poor performance and reliability of the formed semiconductor structure.
Specifically, in one aspect, in order to avoid the pattern profile of the lithography pattern layer from being affected by the formed first mask structure 120, it is necessary to make the surface of the second mask material layer higher than the top surface of the first mask structure 120, so that, in the advanced process node, i.e., the process node where the pattern with smaller critical dimension needs to be formed, the formed second mask structure 130 is likely to have a larger aspect ratio, resulting in the second mask structure 130 being likely to bend and fall. On the other hand, due to limitations of the photolithography process for forming the photolithography pattern layer in the advanced process node and limitations of the material of the second mask material layer in order to form the photolithography pattern layer on a relatively flat surface, it is generally required to use spin-on organic carbon (SOC) as the material of the second mask material layer. The risk of the second mask structure 130 bending and falling is further exacerbated due to the lower hardness of the spin-on organic carbon (SOC).
In order to solve the above technical problem, embodiments of the present invention provide a semiconductor structure and a method for forming the same, in which a plurality of openings are formed in a first mask material layer on a first region, a first mask structure is formed in each opening, and a plurality of second mask structures separated from each other are formed on the first mask material layer on a second region, so that the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to direct contact or not.
Fig. 4 to fig. 15 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a layer to be etched 200 is provided, wherein the layer to be etched 200 includes a first region I and a second region II.
In this embodiment, the layer to be etched 200 includes: a substrate 201, and a second sacrificial material layer 220 located on the substrate 201.
The material of the substrate 201 includes a semiconductor material.
In this embodiment, the material of the substrate 201 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In the present embodiment, the substrate 201 in the first region I has a fin epitaxial layer 202 therein, and the material of the fin epitaxial layer 202 is different from that of the substrate 201, so that different types of devices can be formed in the first region I and the second region II.
In the present embodiment, the material of the fin epitaxial layer 202 includes silicon germanium. The first region I is used to form a P-type device and the second region II is used to form an N-type device.
In other embodiments, the substrate of the second region has a fin epitaxial layer therein, which is of a different material than the substrate, thereby enabling different types of devices to be formed in the first and second regions.
In other embodiments, the first region or the second region has a doped region within the substrate that is of opposite conductivity type to the substrate. Thus, material can be provided for forming P-type devices in the first regions and N-type devices in the second regions. Alternatively, material can be provided for forming N-type devices in the first regions and P-type devices in the second regions.
In the present embodiment, the second sacrificial material layer 220 provides material for the subsequent formation of the second sacrificial structure and the third sacrificial structure.
In the present embodiment, the material of the second sacrificial material layer 220 includes silicon.
In this embodiment, the layer to be etched 200 further includes: a second layer of masking material 210 located between the substrate 201 and the second layer of sacrificial material 220.
The second masking material layer 210 provides material for subsequent formation of a first fin mask structure and a second fin mask structure.
The second mask material layer 210 is beneficial to increasing the stability of the pattern in the subsequent pattern transfer process, so that the pattern with higher precision and better appearance is formed.
In this embodiment, the second mask material layer 210 includes: a second hard mask material layer 211, and a second oxide material layer 212 on the surface of the second hard mask material layer 211.
The material of the second hard mask material layer 211 is a hard mask material, such as silicon nitride, silicon carbide, or silicon carbonitride. In the present embodiment, the material of the second hard mask material layer 211 includes silicon nitride. Since the second hard mask material layer 211 is made of a hard mask material, stability of transferred patterns can be improved better when the first fin mask structure and the second fin mask structure are formed.
The material of the second oxide material layer 212 is, for example, an oxide such as silicon oxide or silicon oxycarbide. In the present embodiment, the material of the second oxide material layer 212 includes silicon oxide. The second oxide material layer 212 can improve the surface flatness of the second mask material layer 210, thereby contributing to the improvement of the accuracy of the pattern shape in transferring the pattern.
With continued reference to fig. 4, a first masking material layer 230 is formed on the layer to be etched 200.
In one aspect, the first mask material layer 230 provides support for subsequently forming the first mask structure to reduce the risk of the first mask structure bending, deforming, or falling. On the other hand, the first mask material layer 230 provides material for the subsequent formation of a third mask structure.
The first mask material layer 230 includes: a lower first mask material layer 231, and an upper first mask material layer 232 on the surface of the lower first mask material layer 231.
The material of the lower first mask material layer 231 is a hard mask material, such as silicon nitride, silicon carbide, or silicon carbonitride. In the present embodiment, the material of the lower first mask material layer 231 is silicon nitride. Since the material of the lower first mask material layer 231 is a hard mask material, the stability of the transferred pattern can be improved better when the third mask structure is formed.
The material of the upper first mask material layer 232 is, for example, an oxide such as silicon oxide, silicon oxycarbide, etc. In the present embodiment, the material of the upper first mask material layer 232 is silicon oxide. The surface flatness of the first mask material layer 230 can be improved by the upper first mask material layer 232, thereby contributing to an improvement in the accuracy of the pattern shape in the process of transferring the pattern.
Next, forming a plurality of openings in the first mask material layer 230 on the first region I; a first mask structure is formed in each opening, and several second mask structures separated from each other are formed on the first mask material layer 230 on the second region II. Please refer to fig. 5 to 9 for a detailed method of forming the opening, the first mask structure and the second mask structure.
Referring to fig. 5, a plurality of first sacrificial structures 240 are formed on the first masking material layer 230 on the second region II and separated from each other.
In the present embodiment, the material of the first sacrificial structure 240 includes silicon.
In this embodiment, the method for forming the first sacrificial structure 240 includes: forming a first sacrificial structure material layer (not shown) on the surface of the first mask material layer 230 on the first region I and the second region II; forming a plurality of mutually-separated first sacrificial structure mask structures (not shown) on the first sacrificial structure material layer on the first region I; the first sacrificial structure material layer is etched by using the first sacrificial structure mask structure as a mask until the first mask material layer 230 is exposed.
In this embodiment, the process of forming the first sacrificial structure material layer includes a deposition process including at least one of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of etching the first sacrificial structure material layer includes: at least one of a dry etching process and a wet etching process.
In other embodiments, the process for forming the first sacrificial structure includes a multiple patterning process.
With continued reference to fig. 5, a second mask material film 250 is formed on the surfaces of the first sacrificial structure 240 and the first mask material layer 230.
The second mask material film 250 provides material for subsequent formation of a second mask structure.
In the present embodiment, the process of forming the second mask material film 250 includes at least one of a chemical vapor deposition process or an atomic layer deposition process.
In the present embodiment, the material of the second mask material film 250 includes silicon nitride.
In other embodiments, the material of the second mask material film includes a hard mask material such as silicon carbide, silicon carbonitride, etc.
Referring to fig. 6, a plurality of openings 241 are formed in the first masking material layer 230 on the first region I.
The opening 241 provides a space for a first mask structure to be formed later.
In this embodiment, the method for forming the openings 241 in the first mask material layer 230 on the first region I includes: forming an opening mask layer 260 on the second mask material film 250, wherein the opening mask layer 260 exposes the second mask material film 250 on the first region I; and etching the second mask material film 250 and the first mask material layer 230 by using the opening mask layer 260 as a mask to form the opening 241.
In this embodiment, the method for etching the second mask material film 250 and the first mask material layer 230 by using the opening mask layer 260 as a mask to form the opening 241 includes: etching the second mask material film 250 by using the opening mask layer 260 as a mask until the first mask material layer 230 is exposed; after the first mask material layer 230 is exposed, the upper first mask material layer 232 is etched by using the opening mask layer 260 as a mask until the surface of the lower first mask material layer 231 is exposed, so as to form the opening 241.
As the opening 241 is formed, the underlying first mask material layer 231 remains. Accordingly, the first mask structure can be provided with support not only by forming the first mask structure within the opening 241 subsequently. Meanwhile, when the pattern of the first mask structure is transferred, the accuracy and stability of the transferred pattern shape can be improved by the lower first mask material layer 231 of the hard mask material. On the basis, the lower first mask material layer 231 can protect the surface of the second sacrificial material layer 220 in the etching process for forming the opening 241, so that the etching load in the pattern transfer process is reduced, and the second sacrificial structure with small top surface roughness and more uniform height is formed subsequently.
In the present embodiment, the process of etching the second mask material film 250 and the first mask material layer 230 includes at least one of a dry etching process and a wet etching process.
In other embodiments, the opening mask layer is used as a mask, and the second mask material film and the first mask material layer are etched until the surface of the second sacrificial material layer is exposed so as to form an opening.
In this embodiment, after the opening 241 is formed, the opening mask layer 260 is removed.
Referring to fig. 7, after forming the opening 241, a third masking material layer 270 is formed in the opening 241 and on the surface of the second masking material film 250, wherein the third masking material layer 270 is higher than the top surface of the first sacrificial structure 240.
In this embodiment, the method for forming the third mask material layer 270 includes: forming an initial third mask material layer (not shown) within the openings 241 and on the surface of the second mask material film 250, the initial third mask material layer surface being higher than the second mask material film 250 surface; the initial third masking material layer is planarized until the top surface of the second masking material film 250 is exposed.
In this embodiment, the process of forming the initial third mask material layer includes a deposition process including at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.
In this embodiment, the process of planarizing the initial third mask material layer includes a chemical mechanical polishing process.
In another embodiment, the third masking material layer is flush with the top surface of the first sacrificial structure. The method for forming the third mask material layer comprises the following steps: forming an initial third mask material layer (not shown) within the opening and on a surface of the second mask material film, the initial third mask material layer surface being higher than the second mask material film surface; and planarizing the initial third mask material layer until the top surface of the first sacrificial structure is exposed.
The third masking material layer 270 provides material for forming a first masking structure.
In the present embodiment, the material of the third mask material layer 270 is the same as the material of the first sacrificial structure 240. Therefore, in the subsequent etching process for forming the first mask structure, the first sacrificial structure 240 can be simultaneously etched to remove the first sacrificial structure 240, thereby reducing the formation steps of the semiconductor structure and improving the efficiency of forming the semiconductor structure.
In the present embodiment, the material of the third mask material layer 270 is different from the material of the second mask material film 250. Therefore, in the subsequent etching process for forming the first mask structure, the material of the third mask material layer 270 and the material of the second mask material film 250 can have different etching rates, so as to reduce the loss of the second mask material film 250 on the sidewall of the first sacrificial structure 240, thereby forming a second mask structure with better topography.
Referring to fig. 8, the first sacrificial structure 240 and the third masking material layer 270 are etched until the surface of the first masking material layer 230 is exposed, and a first masking structure 271 is formed in the opening 241.
Specifically, in the present embodiment, during the etching of the third mask material layer 270, the etching process consumes the second mask material film 250 on the top surface of the first sacrificial structure 240, so as to expose the top surface of the first sacrificial structure 240, and the first sacrificial structure 240 is etched while the third mask material layer 270 is etched.
In the present embodiment, the material of the first mask structure 271 includes silicon.
In other embodiments, the material of the first mask structure includes germanium.
In this embodiment, etching the first sacrificial structure 240 and the third mask material layer 270 includes at least one of a dry etching process and a wet etching process.
Referring to fig. 9, after the first mask structure 271 is formed, the second mask material film 250 on the surface of the first mask material layer 230 is removed by an anisotropic etching process, and a plurality of mutually separated second mask structures 251 are formed on the first mask material layer 230 on the second region II.
Because the plurality of openings 241 are formed in the first mask material layer 230 on the first region I, and the first mask structure 271 is formed in each opening 241, it is not necessary to form a mask structure with a high aspect ratio to realize the transfer of the pattern in the pattern transfer process of forming the first mask structure 271, and therefore, the risk of the first mask structure 271 bending, deforming or falling is reduced, the morphology of the first mask structure 271 is improved, the pattern transfer can be better performed on the layer to be etched 200, and thus, the performance and reliability of the formed semiconductor structure are improved.
Furthermore, by forming the first mask structure 271 in the opening 241, the degree of freedom in selecting the material of the first mask structure 271 can be increased, and thus, by using a hard mask material (e.g., silicon or germanium) having higher hardness as the material of the first mask structure 271, pattern transfer to the layer to be etched 200 can be performed better, thereby improving the performance and reliability of the formed semiconductor structure.
Specifically, the second mask material film 250 is etched through the anisotropic etching process, the second mask material film 250 in the horizontal direction is removed, and the second mask material film 250 in the vertical direction is left, so that the second mask structure 251 is formed.
In this embodiment, the anisotropic etching process includes a plasma etching process.
Next, the first mask material layer 230 and the layer to be etched 200 are patterned according to the first mask structure 271 and the second mask structure 251. The specific steps for patterning the first mask material layer 230 and the layer to be etched 200 are shown in fig. 10 to 15.
Referring to fig. 10, the first mask material layer 230 is etched by using the second mask structure 251 as a mask until the surface of the layer to be etched 200 is exposed, and a plurality of mutually separated third mask structures 233 are formed on the second region II.
In this embodiment, while the first mask material layer 230 is etched by using the second mask structure 251 as a mask, the lower first mask material layer 231 in the first mask material layer 230 is also etched by using the first mask structure 271 as a mask, and a fourth mask structure 234 is formed between the first mask structure 271 and the layer to be etched 200.
Since the material of the fourth mask structure 234 is provided by the underlying first mask material layer 231, i.e., the fourth mask structure 234 is a hard mask material, it is advantageous to improve the accuracy and stability of the transferred pattern shape of the first mask structure.
In the present embodiment, after the third mask structure 233 is formed, the second mask structure 251 is removed.
Referring to fig. 11, the second sacrificial material layer 220 is etched by using the first mask structure 271 and the third mask structure 233 as masks until the surface of the second mask material layer 210 is exposed, a plurality of second sacrificial structures 221 separated from each other are formed in the first region I, and a plurality of third sacrificial structures 222 separated from each other are formed in the second region II.
In this embodiment, in the same etching step, the second sacrificial material layer 220 is etched by using the first mask structure 271 and the third mask structure 233 as masks. Thus, the formation efficiency of the semiconductor structure is improved. Meanwhile, because the fourth mask structure 234 is arranged between the first mask structure 271 and the layer to be etched 200, and the material of the fourth mask structure 234 and the material of the third mask structure 233 have the same hard mask material, the etching load can be reduced while the second sacrificial structure 221 and the third sacrificial structure 222 are formed in the same etching step, so that the heights of the formed second sacrificial structure 221 and the third sacrificial structure 222 are more uniform, and the performance and reliability of the semiconductor structure are improved.
In other embodiments, the second sacrificial structure and the third sacrificial structure are not formed in the same etching step. Specifically, the first mask structure is used as a mask, the second sacrificial material layer of the first area is etched independently until the surface of the second mask material layer of the first area is exposed, and a plurality of mutually-separated second sacrificial structures are formed in the first area. And independently etching the second sacrificial material layer in the second region by taking the third mask structure as a mask until the surface of the second mask material layer in the second region is exposed, and forming a plurality of mutually-separated third sacrificial structures in the second region.
Referring to fig. 12, first sidewalls 281 are formed on sidewall surfaces of the second sacrificial structure 221, and second sidewalls 282 are formed on sidewall surfaces of the third sacrificial structure 222.
In this embodiment, the method for forming the first sidewall 281 and the second sidewall 282 includes: forming sidewall films (not shown) on the surfaces of the second sacrificial structure 221, the third sacrificial structure 222 and the first mask material layer 210; the sidewall film is etched by an anisotropic etching process until the top surfaces of the second sacrificial structure 221, the third sacrificial structure 222 and the surface of the first mask material layer 210 are exposed.
In the present embodiment, the material of the first sidewall 281 and the second sidewall 282 is different from the material of the second sacrificial material layer 220. Therefore, it is possible to have different etching rates for the materials of the second sacrificial structure 221 and the third sacrificial structure 222 and the materials of the first sidewall 281 and the second sidewall 282 in the subsequent etching process for removing the second sacrificial structure 221 and the third sacrificial structure 222, so as to leave the first sidewall 281 and the second sidewall 282 while removing the second sacrificial structure 221 and the third sacrificial structure 222, and reduce the loss of the first sidewall 281 and the second sidewall 282, thereby improving the precision of pattern transfer.
In this embodiment, the material of the first and second sidewalls 281 and 282 includes silicon nitride.
In this embodiment, after the first and second sidewalls 281 and 282 are formed, the second and third sacrificial structures 221 and 222 are removed.
The process of removing the second sacrificial structure 221 and the third sacrificial structure 222 includes at least one of a dry etching process and a wet etching process.
In this embodiment, after removing the second sacrificial structure 221 and the third sacrificial structure 222, the substrate 201 in the first region I is patterned with the first sidewalls 281, and the substrate 201 in the second region II is patterned with the second sidewalls 282, so that a plurality of first fins are formed in the first region I and a plurality of second fins are formed in the second region II. Please refer to fig. 13 to fig. 15 for the specific steps of patterning the substrate in the first region with the first sidewall and patterning the substrate in the second region with the second sidewall.
Referring to fig. 13, the second mask material layer 210 in the first region I is etched by using the first sidewalls 281 as a mask, and the second mask material layer 210 in the second region II is etched by using the second sidewalls 282 as a mask until the surface of the substrate 201 is exposed, so as to form a plurality of first fin mask structures 291 that are separated from each other in the first region I, and form a plurality of second fin mask structures 292 that are separated from each other in the second region II.
In the present embodiment, the process of etching the second mask material layer 210 includes at least one of a dry etching process and a wet etching process.
In the present embodiment, after the first fin mask structure 291 and the second fin mask structure 292 are formed, the first sidewall 281 and the second sidewall 282 are removed.
Referring to fig. 14 and fig. 15, fig. 15 is a schematic perspective view of the semiconductor structure in fig. 14, fig. 14 is a schematic cross-sectional view along the direction X1-X2 in fig. 15, the substrate 201 in the first region I and the fin epitaxial layer 202 in the substrate 201 are etched by using the first fin mask structure 291 as a mask, and the substrate 201 in the second region II is etched by using the second fin mask structure 292 as a mask, so as to form a plurality of first fins 203 separated from each other in the first region I, and a plurality of second fins 204 separated from each other in the second region II.
In this embodiment, the first and second fins 203, 204 are used to form P-type and N-type devices, respectively.
It is to be understood that, due to the pattern transfer through the opening mask layer 260 (shown in fig. 6) and the first sacrificial structure 240 (shown in fig. 6), respectively, the independence between the pattern of the first fin 203 in the first region I and the pattern of the second fin 204 in the first region II is high, i.e., the pattern of the first fin 203 in the first region I and the pattern of the second fin 204 in the second region II may be different.
In the present embodiment, the spacing between the sidewalls of adjacent first fins 203 is greater than the spacing between the sidewalls of adjacent second fins 204. In other embodiments, the fin epitaxial layer is absent from the substrate. On the basis, the first fin portion mask structure is used as a mask to etch the substrate of the first area, the second fin portion mask structure is used as a mask to etch the substrate of the second area, so that a plurality of mutually-separated first fins are formed in the first area, and a plurality of mutually-separated second fins are formed in the second area, and different patterns are transmitted between the first area and the second area.
In other embodiments, the spacing between the sidewalls of adjacent first fins is less than the spacing between the sidewalls of adjacent second fins.
In the present embodiment, after the first fin 203 and the second fin 204 are formed, the first fin mask structure 291 (shown in fig. 13) and the second fin mask structure 292 (shown in fig. 13) are removed.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 9, including: a layer to be etched 200, wherein the layer to be etched 200 comprises a first region I and a second region II; a first mask material layer 210 on the layer to be etched 200; a plurality of openings 241 (shown in FIG. 6) in the first masking material layer 210 over the first region I; a first mask structure 271 located within each opening 241; a plurality of second mask structures 251 separated from each other are located on the first mask material layer 210 on the second region II.
The layer to be etched 200 includes: a substrate 201, a layer of second masking material 210 located on the substrate 201, and a layer of second sacrificial material 220 located on the layer of second masking material 210.
The material of the substrate 201 includes a semiconductor material.
In this embodiment, the material of the substrate 201 includes silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP and the like.
In the present embodiment, the substrate 201 in the first region I has a fin epitaxial layer 202 therein, and the material of the fin epitaxial layer 202 is different from that of the substrate 201, so that different types of devices can be formed in the first region I and the second region II.
In the present embodiment, the material of the fin epitaxial layer 202 includes silicon germanium. The first region I is used to form a P-type device and the second region II is used to form an N-type device.
In other embodiments, the substrate of the second region has a fin epitaxial layer therein, and the material of the fin epitaxial layer is different from that of the substrate, so that different types of devices can be formed in the first region and the second region.
In other embodiments, the first or second region has a doped region within the substrate that is opposite in conductivity type to the substrate. Thus, material can be provided for forming P type devices in the first regions and N type devices in the second regions. Alternatively, material can be provided for forming N type devices in the first regions and P type devices in the second regions.
In the present embodiment, the material of the second sacrificial material layer 220 includes silicon.
In this embodiment, the second mask material layer 210 includes: a second hard mask material layer 211, and a second oxide material layer 212 on the surface of the second hard mask material layer 211.
The material of the second hard mask material layer 211 is a hard mask material, such as silicon nitride, silicon carbide, or silicon carbonitride. In the present embodiment, the material of the second hard mask material layer 211 includes silicon nitride.
The material of the second oxide material layer 212 is, for example, an oxide such as silicon oxide or silicon oxycarbide.
In the present embodiment, the material of the second oxide material layer 212 includes silicon oxide.
The first mask material layer 230 includes: a lower first mask material layer 231, and an upper first mask material layer 232 on the surface of the lower first mask material layer 231.
The material of the lower first mask material layer 231 is a hard mask material, such as silicon nitride, silicon carbide, or silicon carbonitride.
The material of the upper first mask material layer 232 is, for example, an oxide such as silicon oxide, silicon oxycarbide, etc. In the present embodiment, the material of the upper first mask material layer 232 is silicon oxide.
In the present embodiment, the material of the first mask structure 271 includes silicon. In other embodiments, the material of the first mask structure includes germanium.
In the present embodiment, the material of the second mask material film 250 includes silicon nitride. In other embodiments, the material of the second mask material film includes a hard mask material such as silicon carbide, silicon carbonitride, etc.
Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 14 to fig. 15, including: the substrate 201 comprises a first area I and a second area II, a plurality of mutually-discrete first fins 203 are arranged on the substrate 201 in the first area I, a plurality of mutually-discrete second fins 204 are arranged on the substrate 201 in the second area II, and the space between the side walls of the adjacent first fins 203 is smaller than the space between the side walls of the adjacent second fins 204; a first fin mask structure 291 (shown in fig. 13) on the first fin 203; a second fin mask structure 292 (shown in fig. 13) is located on the second fin 204.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (16)
1. A method of forming a semiconductor structure, comprising:
providing a layer to be etched, wherein the layer to be etched comprises a first region and a second region;
forming a first mask material layer on the layer to be etched;
forming a plurality of openings in the first mask material layer on the first region;
forming a first mask structure in each opening, and forming a plurality of mutually-separated second mask structures on the first mask material layer on the second area;
and patterning the first mask material layer and the layer to be etched according to the first mask structure and the second mask structure.
2. The method of forming a semiconductor structure of claim 1, wherein a material of the first mask structure comprises silicon or germanium.
3. The method of claim 1, wherein forming a first mask structure within each opening, and forming a plurality of second mask structures on the first masking material layer over the second region, wherein the method comprises: before the opening is formed, a plurality of first sacrificial structures which are separated from each other are formed on the first mask material layer on the second area; forming a second mask material film on the surfaces of the first sacrificial structure and the first mask material layer; after forming the opening, forming a third mask material layer in the opening and on the surface of the second mask material film, wherein the third mask material layer is higher than or flush with the top surface of the first sacrificial structure; etching the first sacrificial structure and the third mask material layer until the surface of the first mask material layer is exposed to form the first mask structure; and after the first mask structure is formed, removing the second mask material film on the surface of the first mask material layer by adopting an anisotropic etching process to form the second mask structure.
4. The method of claim 3, wherein a material of the third masking material layer is the same as a material of the first sacrificial structure, and wherein a material of the third masking material layer is different from a material of the second masking material film.
5. The method of claim 3, wherein the process of forming the first sacrificial structure comprises a multiple patterning process.
6. The method of forming a semiconductor structure of claim 3, wherein the forming openings in the first layer of masking material over the first region comprises: forming an opening mask layer on the second mask material film, wherein the opening mask layer exposes the second mask material film on the first area; and etching the second mask material film and the first mask material layer by taking the opening mask layer as a mask so as to form the opening.
7. The method of forming a semiconductor structure of claim 1, wherein the patterning the layer of the first masking material and the layer to be etched according to the first mask structure and the second mask structure comprises: and etching the first mask material layer by taking the second mask structure as a mask until the surface of the layer to be etched is exposed, and forming a plurality of mutually-separated third mask structures on the second area.
8. The method of forming a semiconductor structure of claim 7, wherein the first masking material layer comprises: the mask structure comprises a lower first mask material layer and an upper first mask material layer located on the surface of the lower first mask material layer, wherein the lower first mask material layer is made of silicon nitride, an opening is located in the upper first mask material layer, and the lower first mask material layer is exposed at the bottom of the opening.
9. The method for forming a semiconductor structure according to claim 8, wherein the method for patterning the layer of the first masking material and the layer to be etched according to the first mask structure and the second mask structure further comprises: and etching the first mask material layer by taking the second mask structure as a mask, and simultaneously etching the first mask material layer by taking the first mask structure as a mask to form a fourth mask structure between the first mask structure and the layer to be etched.
10. The method of forming a semiconductor structure of claim 7, wherein the layer to be etched comprises: the substrate and a second sacrificial material layer located on the substrate.
11. The method of forming a semiconductor structure of claim 10, wherein the method of patterning the layer of first masking material and the layer to be etched according to the first mask structure and the second mask structure further comprises: and etching the second sacrificial material layer by taking the first mask structure and the third mask structure as masks, forming a plurality of mutually-separated second sacrificial structures in the first area, and forming a plurality of mutually-separated third sacrificial structures in the second area.
12. The method of forming a semiconductor structure of claim 11, wherein the method of patterning the layer of first masking material and the layer to be etched according to the first mask structure and the second mask structure further comprises: forming a first side wall on the side wall surface of the second sacrificial structure, and forming a second side wall on the side wall surface of the third sacrificial structure; after the first side wall and the second side wall are formed, removing the second sacrificial structure and the third sacrificial structure; after the second sacrificial structure and the third sacrificial structure are removed, the substrate of the first area is patterned by the first side walls, the substrate of the second area is patterned by the second side walls, a plurality of first fins which are separated from each other are formed in the first area, and a plurality of second fins which are separated from each other are formed in the second area.
13. The method of forming a semiconductor structure of claim 12, wherein the layer to be etched further comprises: a second layer of masking material located between the substrate and the second layer of sacrificial material.
14. The method of forming a semiconductor structure according to claim 13, wherein the patterning the substrate of the first region with the first sidewall and the patterning the substrate of the second region with the second sidewall comprises: etching the second mask material layer in the first area by taking the first side walls as masks, etching the second mask material layer in the second area by taking the second side walls as masks until the surface of the substrate is exposed, forming a plurality of mutually-separated first fin part mask structures in the first area, and forming a plurality of mutually-separated second fin part mask structures in the second area; and etching the substrate in the first region by taking the first fin part mask structure as a mask, and etching the substrate in the second region by taking the second fin part mask structure as a mask to form the first fin and the second fin.
15. A semiconductor structure, comprising:
the etching method comprises the steps that a layer to be etched comprises a first area and a second area, and the layer to be etched comprises a substrate, a second mask material layer located on the substrate and a second sacrificial material layer located on the second mask material layer;
a first mask material layer positioned on the layer to be etched;
a plurality of openings in the first mask layer over the first region;
a first mask structure located within each opening;
and a plurality of mutually-separated second mask structures positioned on the first mask material layer on the second area.
16. A semiconductor structure, comprising:
the substrate comprises a first area and a second area, wherein a plurality of mutually-discrete first fins are arranged on the substrate in the first area, a plurality of mutually-discrete second fins are arranged on the substrate in the second area, and the distance between the side walls of the adjacent first fins is smaller than that between the side walls of the adjacent second fins;
a first fin portion mask structure on the first fin;
a second fin mask structure on the second fin.
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