CN115208190B - DCDC converter, switching power supply, and electronic device - Google Patents

DCDC converter, switching power supply, and electronic device Download PDF

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Publication number
CN115208190B
CN115208190B CN202211109551.2A CN202211109551A CN115208190B CN 115208190 B CN115208190 B CN 115208190B CN 202211109551 A CN202211109551 A CN 202211109551A CN 115208190 B CN115208190 B CN 115208190B
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current
signal
output
current sampling
tube
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CN115208190A (en
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张亮
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Shenzhen Injoinic Technology Co Ltd
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Shenzhen Injoinic Technology Co Ltd
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Priority to PCT/CN2022/132136 priority patent/WO2024055408A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/1566—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application provides a DCDC converter, a switching power supply and electronic equipment, wherein one end of a peak current sampling module in the DCDC converter is connected with a drain electrode of a power tube, is connected with an input voltage through an inductor and is connected with a first output voltage through a diode, and the other end of the peak current sampling module is connected with a ramp wave generating module; one end of the ramp generating module is connected with the adder, the other end of the ramp generating module is connected with the negative input end of the comparator, one end of a switch corresponding to each current sampling module connected with the adder is connected with the first output voltage, and the other end of the switch outputs corresponding second output voltage; a divided voltage signal of the first output voltage is connected to a negative input end of the error amplifier, a positive input end of the error amplifier is connected to a reference voltage, and an output end of the error amplifier is connected to a positive input end of the comparator through the compensation network; the output end of the comparator is connected with one end of the driving module, and the other end of the driving module is connected with the grid electrode of the power tube. The load transient response speed can be improved.

Description

DCDC converter, switching power supply and electronic equipment
Technical Field
The application relates to the technical field of electronics, in particular to a DCDC converter, a switching power supply and electronic equipment.
Background
Transient response means that the DCDC can react quickly when the load changes rapidly, and provide enough power in a short time, so that the output can be stable without large overshoot or undershoot. In some applications, such as CPU core voltage or rf power amplifier circuits, fast transient response is important. The better solution of transient response at present is mainly proposed for BUCK converters, for example, the COT (constant on time) can rapidly increase or decrease the duty ratio by changing the frequency when the load jumps transiently, so that the output voltage does not change greatly. However, for the BOOST and BUCK-BOOST converters, because a right half-plane zero point exists, the crossing frequency of the converter must be less than half of the zero point, so that the bandwidth of the converter is small, the load transient response speed is very slow, and no better scheme can solve the problem at present. Therefore, the problem of how to increase the transient response speed of the load needs to be solved urgently.
Disclosure of Invention
The embodiment of the application provides a DCDC converter, a switching power supply and an electronic device, which can improve the transient response speed of a load.
In a first aspect, an embodiment of the present application provides a DCDC converter, including: an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp generating module and a driving module, wherein,
one end of the peak current sampling module is connected with a drain electrode of the power tube, is connected with input voltage through an inductor and is connected with first output voltage through a diode, and the other end of the peak current sampling module is connected with the ramp wave generating module;
one end of the ramp generating module is connected with an adder, the other end of the ramp generating module is connected with the negative input end of the comparator, the adder is also connected with a plurality of current sampling modules, one end of a switch corresponding to each current sampling module is connected with the first output voltage, and the other end of the switch outputs a corresponding second output voltage;
the first output voltage is divided by a first resistor and a second resistor, the first output voltage is connected to the negative input end of the error amplifier through a divided voltage signal of the first resistor, the positive input end of the error amplifier is connected to a reference voltage, and the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network;
the output end of the comparator is connected to one end of the driving module, the other end of the driving module is connected to the grid electrode of the power tube, and the source electrode of the power tube is grounded.
In a second aspect, embodiments of the present application provide a switching power supply, which includes a DCDC converter as described in the first aspect.
In a third aspect, an electronic device is provided in an embodiment of the present application, where the electronic device includes the DCDC converter according to the first aspect or the switching power supply according to the second aspect.
The embodiment of the application has the following beneficial effects:
as can be seen, in the DCDC converter, the switching power supply, and the electronic device described in the embodiments of the present application, the DCDC converter includes: the device comprises an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp wave generating module and a driving module, wherein one end of the peak current sampling module is connected with a drain electrode of the power tube, is connected with input voltage through an inductor and is connected with first output voltage through a diode, and the other end of the peak current sampling module is connected with the ramp wave generating module; one end of the ramp generating module is connected with the adder, the other end of the ramp generating module is connected with the negative input end of the comparator, the adder is also connected with a plurality of current sampling modules, one end of a switch corresponding to each current sampling module is connected with the first output voltage, and the other end of the switch outputs the corresponding second output voltage; the first output voltage is divided by a first resistor and a second resistor, a divided voltage signal of the first output voltage passing through the first resistor is connected to the negative input end of the error amplifier, the positive input end of the error amplifier is connected to a reference voltage, and the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network; the output end of the comparator is connected with one end of the driving module, the other end of the driving module is connected with the grid electrode of the power tube, and the source electrode of the power tube is grounded, so that the transient response speed of the load can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a BOOST converter provided in an embodiment of the present application;
FIG. 2 is a schematic waveform diagram illustrating a light-load jump heavy load of a BOOST converter according to an embodiment of the present application;
FIG. 3 is a waveform diagram illustrating a heavy load, jump and light load of a BOOST converter according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a fast transient response DCDC converter provided in an embodiment of the present application;
fig. 5 is a schematic structural diagram of a ramp generating module according to an embodiment of the present disclosure;
fig. 6 is a schematic waveform diagram of a ramp generating module according to an embodiment of the present disclosure;
fig. 7 is a schematic waveform diagram illustrating a light-load, jumping and heavy-load of a DCDC converter according to an embodiment of the present application;
fig. 8 is a waveform diagram of a heavy load, a skip load and a light load of a DCDC converter according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions of the present application, the following description is given for clarity and completeness in conjunction with the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person skilled in the art without making any inventive step on the basis of the description of the embodiments of the present application belong to the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, software, product, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements recited, but may also include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The embodiments of the present application will be described with reference to the drawings, in which a dot at the intersection of intersecting wires indicates that the wires are connected, and a dot-free intersection indicates that the wires are not connected.
In the related art, please refer to fig. 1, as fig. 1 is a schematic diagram of a multi-port output BOOST converter, in the schematic diagram, ci is an input capacitor, L is an inductor, D is a freewheeling diode, BG is a power tube, co is an output capacitor, vo is an output voltage, S1 to Sn are multi-port output switches, vo1 to Von are output voltages of each channel, R1 and R2 are voltage dividing resistors, EA is an error amplifier, C0, C1 and Rc1 form a compensation network, CMP is a comparator, and Vslope is a ramp compensation voltage.
The working principle of the multi-port output BOOST converter is as follows: an error amplification signal Vea is generated after the divided voltage VFB of the output voltage and the reference voltage VREF pass through an error amplifier EA, a signal peak current signal Vcs obtained by sampling of a peak current sampling module is superposed with a ramp compensation signal Vslope to obtain a triangular wave signal Vramp, the Vramp and the Vea are compared through a comparator CMP to obtain a duty ratio signal PWMON, and a driving signal BG _ DRV of a power tube BG is generated after the driving signal DRIVE. In one period, when BG _ DRV is high, BG is conducted, the current on an inductor L is increased and stores energy, LX is low, a freewheeling diode D is turned off, and the output is provided with energy by a capacitor Co; when BG _ DRV is low, BG is turned off, inductor current raises LX and turns on diode D to freewheel, at which time inductor current not only provides energy for the load, but also charges capacitor Co, during which time inductor current decreases and the final value equals the initial inductor current value at the beginning of the cycle to reach magnetic balance, and the process is repeated for the next cycle. Therefore, as long as BG has stable on-off time (namely stable duty ratio), stable output Vo can be obtained, and then S1-Sn are switched on according to different requirements, so that branch output Vo 1-Von can be obtained.
And then, analyzing the process of obtaining the stable duty ratio by the multi-port output BOOST converter. Supposing that the branch switches S1-Sn open one or more paths suddenly, the load current of the circuit becomes large suddenly, vo decreases, the divided voltage VFB also decreases and is lower than the reference VREF, vea rises after EA, the high level time of a duty ratio PWMON signal obtained after comparison with Vramp increases, namely the duty ratio increases, so that the opening time of BG increases, the inductive current rises, the energy provided for output also increases, vo gradually rises, and a stable value is reached after multiple periods. Then, due to the limitation of the right half-plane zero point, the loop bandwidth determined by the compensation networks C0, rc1 and C1 is very small, so the change rate of Vea is very slow, the duty ratio is also very slow to increase, which causes the inductor current to rise only slowly, and the output voltage Vo has a large undershoot voltage.
On the contrary, in the same way, assuming that the branch switches S1 to Sn are suddenly turned off one or more paths, the load current will suddenly decrease, vo will rise, the divided voltage VFB will also rise and be higher than the reference VREF, vea will drop after EA, and the high level time of the duty ratio PWMON signal obtained after comparison with Vramp will decrease, i.e., the duty ratio decreases, so the on-time of BG will decrease, the inductor current will decrease, the energy provided for output will also decrease, so Vo will gradually decrease, and reach a stable value after a plurality of cycles. Then, due to the limitation of the right half-plane zero point, the loop bandwidth determined by the compensation networks C0, rc1 and C1 is very small, so the rate of change of Vea is very slow, and the reduction of the duty ratio is also very slow, which causes that the inductive current can only be slowly reduced, and the output voltage Vo has a very large overshoot voltage.
Specifically, as shown in fig. 2, fig. 2 is a waveform of the multi-port output BOOST converter during light load, jump and heavy load. When the branch switches S1-Sn suddenly open one or more paths, the load current Iload can be increased instantly, the output voltage Vo starts to fall because the inductive current is smaller than the load current requirement, the divided voltage VFB is smaller than the reference voltage VREF, the output Vea of EA will slowly rise, the duty ratio of PWM signals is increased, the inductive current rises, the output voltage continuously falls when the inductive current is smaller than the load current in the rising process, and the output voltage starts to rise until the inductive current rises to be larger than the load current and finally tends to be stable. The whole adjusting process time is shown as t1 in the figure, the size of t1 and the loop bandwidth are in a positive and negative example relationship, and the BOOST loop bandwidth is limited by the right half-plane zero point and cannot be very large, so that the small signal response speed of the loop cannot be very fast, and the undershoot voltage delta Vdrop of Vo in the light load jump heavy load process can be very large.
Specifically, as shown in fig. 3, fig. 3 is a waveform of a multi-port output BOOST converter during heavy load, jump and light load. When the branch switches S1-Sn suddenly turn off one or more paths, the load current can be instantly reduced, because the inductive current is larger than the load current demand, the output voltage Vo starts to rise, the divided voltage VFB is larger than the reference voltage VREF, and the output Vea of EA slowly falls, so that the duty ratio of the PWM signal is reduced, the inductive current falls, in the falling process, when the inductive current is larger than the load current, the output voltage continuously rises, and the output voltage does not start to fall until the inductive current falls to be smaller than the load current and finally tends to be stable. The whole adjusting process time is shown as t2 in the figure, the size of t2 is in a positive and negative example relation with the loop bandwidth, and the loop bandwidth of the BOOST is limited by the right half-plane zero point and cannot be very large, so that the small signal response speed of the loop cannot be very fast, and the overshoot voltage delta Vshoot of Vo in the heavy-load, jump and light-load process is very large.
To solve the drawbacks of the related art, please refer to fig. 4, fig. 4 is a schematic structural diagram of a DCDC converter according to an embodiment of the present application, where the DCDC converter includes: error amplifier EA, compensation network, comparator CMP, peak current sampling module, power tube BG, ramp generating module, and driving module DRIVE,
one end of the peak current sampling module is connected with a drain electrode of the power tube BG, is connected with an input voltage Vin through an inductor L and is connected with a first output voltage Vo through a diode D, and the other end of the peak current sampling module is connected with a ramp wave generating module;
one end of the ramp generating module is connected with an adder ADD, the other end of the ramp generating module is connected with a negative input end (-) of the comparator CMP, the adder ADD is further connected with a plurality of current sampling modules, one end of a switch corresponding to each current sampling module is connected with the first output voltage Vo, and the other end of the switch outputs a corresponding second output voltage;
the first output voltage is divided by a first resistor R1 and a second resistor R2, the first output voltage is connected to a negative input end (-) of the error amplifier EA through a divided voltage signal VFB of the first resistor, a positive input end (+) of the error amplifier EA is connected to a reference voltage VREF, and an output end of the error amplifier EA is connected to a positive input end (+) of the comparator CMP through the compensation network;
the output end of the comparator CMP is connected to one end of the driving module DRIVE, the other end of the driving module DRIVE is connected to the grid of the power tube BG, and the source electrode of the power tube BG is grounded.
Wherein, if there are n current sampling modules, and n is an integer greater than 1, different current sampling modules correspond to different switches, respectively as follows: the current sampling module corresponds to S1, and a corresponding branch circuit samples current Ics1 and second output voltage Vo1; the current sampling module corresponds to S2, and a corresponding branch circuit samples current Ics2 and second output voltage Vo2; 8230; the current sampling module corresponds to Sn, and the corresponding branch circuit samples the current Icsn and the second output voltage Von.
In the embodiment of the application, loads can be hung on each of the Vo 1-Von branches, that is, each of the second output voltages is provided for a corresponding load. Vo is total voltage output, vo 1-Von are output voltage branches opened according to application requirements, vo cannot be independently loaded generally, and the opened branches are generally loaded, so that each branch can be loaded.
The DCDC converter mentioned in the embodiment of the application can avoid the influence of low output loop bandwidth and quickly react to load transient change.
Optionally, the input voltage Vin is grounded through an input capacitor Ci, and the output terminal of the diode D is grounded through an output capacitor Co.
The input voltage Vin is grounded through an input capacitor Ci, and the output terminal of the diode D is grounded through an output capacitor Co.
Optionally, the compensation network includes: a first capacitor C0, a second capacitor C1 and a third resistor Rcl;
the output end of the error amplifier EA is sequentially connected with the third resistor Rcl and the second capacitor C1, and the second capacitor C1 is grounded;
the error amplifier EA is grounded through the first capacitor C0.
Wherein, C0, C1 and Rc1 form a compensation network.
Wherein the DCDC converter is to:
superposing the output current sampling signals of each path in the plurality of current sampling modules to obtain a total output current sampling signal Ics;
and passing the total output current sampling signal Ics, the peak sampling current Ipk sampled by the peak current sampling module, the ramp compensation current Islope and the direct current signal Idc through the ramp generation module to obtain a triangular wave signal Vramp.
Each branch circuit is provided with a current sampling module, current signals of the branch circuits S1 to Sn are sampled to obtain sampling signals Ics1 to Icsn, then the sampling currents can be superposed to obtain a total output current sampling signal Ics, and the signal, a peak sampling current Ipk, a ramp compensation current Islope and a direct current signal Idc enter a ramp generation module to generate a triangular wave signal Vramp.
Specifically, as shown in fig. 4, LOOP2 in the figure is an output voltage LOOP, a voltage division signal VFB of an output voltage Vo and a reference voltage VREF generate an error signal Vea after passing through an error amplifier EA, the error signal Vea is compared with a triangular wave signal Vramp to obtain a duty ratio signal PWMON, and then a power tube BG is driven to obtain a stable output voltage. In order to obtain a high-precision output voltage, the gain of the LOOP2 is large, so that a compensation network composed of C0, C1 and Rc1 is required to ensure the stability. In the figure, LOOP1 is an output current LOOP, each branch sampling current Ics 1-Icsn is superposed by an adder ADD to obtain a total output current sampling signal Ics, a triangular wave signal Vramp is generated by a ramp generating module and is compared with an error signal Vea to obtain a duty ratio signal PWMON, and then a power tube BG is driven to obtain stable output voltage. It can be seen that the output current enters the LOOP of LOOP1 and participates in controlling the output voltage, and the gain of the LOOP is low, so that no additional compensation network is needed, the bandwidth is large, and the LOOP can react to the instantaneous change of the output current.
In the embodiment of the present application, the LOOP2 refers to an output voltage LOOP. The feedback signal is derived from the output voltage Vo, and is subjected to feedback voltage division, an error amplifier, a comparator and a driving module to generate a signal with a certain duty ratio to control the on and off of the power tube, and the feedback path is a LOOP2. The specific working principle is as follows: when the output voltage is higher than the set voltage, VFB is increased, the error signal Vea is reduced after EA, the duty ratio obtained after comparison with the ramp signal is reduced, so that the turn-on time of the power tube BG is reduced, the energy provided by the converter for output is reduced, and the output voltage is reduced and returns to the set voltage; similarly, when the output voltage is lower than the set voltage, VFB is reduced, the error signal Vea is increased after EA, the duty ratio obtained by comparison is increased, BG opening time is increased, and energy provided by the converter for output is increased, so that the output voltage returns to a normal value.
In the embodiment of the present application, the LOOP1 refers to an output current LOOP. The feedback signal is derived from output currents Ics 1-Icsn, a total output current feedback signal Ics is obtained through current superposition, then the feedback signal enters the ramp generating module, and the ramp generating module, the comparator and the driving module generate a duty ratio to control the on and off of the power tube, and the feedback path is a LOOP LOOP1. The specific working principle is as follows: when S1-Sn branches are suddenly conducted (the branches have loads), ics can be increased, the direct current value of a ramp signal generated by a ramp module can be reduced, so that the duty ratio can be increased, the BG (pulse-width modulation) opening time can be increased, the energy provided by the converter for output is increased, and therefore large undershoot voltage can not be generated in the output; similarly, when S1~ Sn cut off suddenly when one way or multichannel, ics can reduce, and the ramp signal direct current value that the ramp module produced can increase, therefore the duty cycle can reduce behind the comparator, and BG on-time can reduce, and the energy that the converter provided for the output is too little, therefore big upper surge voltage can not appear in the output.
In the embodiment of the present application, the duty ratio can be adjusted by both LOOPs LOOP1 and LOOP2. Because the gain of the LOOP1 of the output current mode is very small, the bandwidth is very large, namely the adjusting speed is very fast, and therefore, the fast response to the load transient change with large amplitude change can be realized, and when the load has no transient change, the change of the load current is very small, the low LOOP gain can not introduce the very small value into the duty ratio, so that the LOOP2 with high gain and low bandwidth can not be influenced, thereby ensuring that the two LOOPs do not influence each other, ensuring that the duty ratio is not disordered, and ensuring the stability.
Optionally, the DCDC converter is configured to:
when at least one branch circuit corresponding to the plurality of current sampling modules is conducted, the load current Iload is suddenly increased, the output current sampling signal of the current sampling module corresponding to the at least one branch circuit also rapidly rises, the total output current sampling signal Ics passing through the adder ADD rapidly rises, and the direct-current level value of the triangular wave signal Vramp is rapidly reduced after the total output current sampling signal Ics enters the ramp wave generation module.
In specific implementation, when the branches S1 to Sn are suddenly connected to one or more paths, the load current Iload will suddenly increase, the outputs Ics1 to Icsn of the current sampling modules of S1 to Sn will rapidly increase corresponding to the connected branches, the total output current sampling signal Ics after passing through the adder ADD will rapidly rise, and after entering the ramp generating module, the dc level value of the triangular wave Vramp will be rapidly reduced, because the LOOP speed of LOOP1 is much greater than LOOP2, vea will remain unchanged at this time, a larger peak current is required when the peak value of the triangular wave Vramp rises to reach the value of Vea, and the rising rate of the inductive current is unchanged, so that a larger peak current means a longer BG on-time, that is, the duty ratio is increased. The inductor current increases and the energy supplied to the load increases as the duty cycle increases. Because the load current is increased instantly, the load current is directly fed back to Vramp through the output current LOOP LOOP1 to increase the duty ratio, and does not depend on the output voltage LOOP LOOP2 any more, the reaction speed is very high, the undershoot of the output voltage Vo is very small, and the purpose of improving the transient response speed of the load is achieved.
Optionally, the DCDC converter is configured to:
when at least one branch circuit corresponding to the plurality of current sampling modules is turned off, the load current Iload can be suddenly reduced, the output current sampling signal of the current sampling module corresponding to the at least one branch circuit can also be rapidly reduced, the total output current sampling signal Ics passing through the adder ADD can be rapidly reduced, and the direct-current level value of the triangular wave signal Vramp can be rapidly increased after the total output current sampling signal Ics enters the ramp wave generating module.
In specific implementation, when the branches S1 to Sn are suddenly turned off one or more branches, the load current Iload is suddenly reduced, the outputs Ics1 to Icsn of the current sampling modules of S1 to Sn are rapidly reduced corresponding to the turned-on branches, the total output current sampling signal Ics after passing through the adder ADD is rapidly reduced, the direct current level value of the triangular wave Vramp is rapidly increased after entering the ramp generating module, because the LOOP speed of LOOP1 is much greater than LOOP2, vea is basically kept unchanged at this time, a smaller peak current is required when the peak value of the triangular wave Vramp rises to reach the value of Vea, and the rising rate of the inductive current is unchanged, so that the smaller peak current means that a shorter BG turn-on time is required, that is, the duty ratio is reduced. The inductor current is reduced after the duty cycle is reduced, and the energy supplied to the load is reduced. Because the load current is instantly reduced by directly feeding back to Vramp through the output current LOOP LOOP1 to reduce the duty ratio, and the duty ratio does not depend on the output voltage LOOP LOOP2 any more, the reaction speed is very high, and the overshoot of the output voltage Vo is very small, thereby achieving the purpose of improving the transient response speed of the load.
Optionally, as shown in fig. 5, the ramp generating module includes: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1 and a second NMOS tube MN2;
the ramp compensation current Islope is connected to a drain electrode and a gate electrode of the first PMOS transistor MP1, a source electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor MP2, a source electrode of the third PMOS transistor MP3, a source electrode of the fourth PMOS transistor MP4, a source electrode of the fifth PMOS transistor MP5 and a source electrode of the sixth PMOS transistor MP6, and a gate electrode of the first PMOS transistor MP1 is connected to a gate electrode of the second PMOS transistor MP 2;
the drain electrode of the second PMOS transistor MP2 is connected to the drain electrode of the fourth PMOS transistor MP4, the drain electrode of the fifth PMOS transistor MP5, the drain electrode of the second NMOS transistor MN2, and is grounded through a fourth resistor R, and the drain electrode of the second PMOS transistor MP2 is further configured to output the triangular wave signal Vramp;
the peak sampling current Ipk is connected to a grid electrode and a drain electrode of the third PMOS tube MP3, and the grid electrode of the third PMOS tube MP3 is connected with the grid electrode of the fourth PMOS tube MP 4; the drain electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the second NMOS tube MN2;
the total output current sampling signal Islope is accessed to a grid electrode and a drain electrode of the first NMOS tube MN1, the grid electrode of the first NMOS tube MN1 is connected with a grid electrode of the second NMOS tube MN2, and a source electrode of the first NMOS tube MN1 and a source electrode of the second NMOS tube MN2 are both grounded;
the direct current signal Idc is connected to the drain and the gate of the sixth PMOS transistor MP6, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP 5.
Further, the specific principle of the ramp generating module is as follows:
the first PMOS tube and the second PMOS tube form a current mirror for mirroring the ramp compensation current;
the third PMOS tube and the fourth PMOS tube form a current mirror for mirroring the peak sampling current;
the fifth PMOS tube and the sixth PMOS tube form a current mirror for mirroring the direct current signal;
the first NMOS tube and the second NMOS tube form a current mirror for mirroring a total output current sampling signal;
the ramp compensation current, the peak sampling current, the direct current signal and the total output current sampling signal all flow into the fourth resistor and are converted into the triangular wave signal, and the triangular wave signal satisfies the following relationship:
Figure 155752DEST_PATH_IMAGE001
wherein,Vrampwhich represents a signal of a triangular wave,Islopeshows a ramp compensation current,IpkRepresents the peak sample current,IdcWhich is representative of a direct current signal that is,Icsrepresents the total output current sample signal and,Rrepresenting the resistance of the fourth resistor.
In the specific implementation, MP1 and MP2 form a current mirror, the mirror slope compensation current Islope signal, MP3 and MP4 form a current mirror, the mirror peak sampling current Ipk, MP5 and MP6 form a current mirror, the mirror dc current signal Idc, MN1 and MN2 form a current mirror, the mirror outputs the current signal Ics, these current signals all flow into the resistor R, and are converted into the triangular wave signal Vramp, which satisfies the relationship:
Figure 360468DEST_PATH_IMAGE001
optionally, when slope and Ipk are both signals changing from cycle to cycle, the dc voltage signal of Vramp is determined according to the following formula:
Figure 559369DEST_PATH_IMAGE002
where VDC represents a dc voltage signal of Vramp.
Wherein Islope and Ipk are both signals that change from cycle to cycle, and assuming that the dc voltage signal of Vramp is VDC, then:
Figure 228247DEST_PATH_IMAGE002
it can be seen that as the output current increases, i.e., ics becomes larger, VDC will become smaller, i.e., the dc component of Vramp will decrease, whereas as the output current decreases, the dc component of Vramp will increase.
In a specific implementation, as shown in fig. 6, fig. 6 is a waveform diagram of the ramp generating module. Wherein Ipk is a peak current sampling signal when BG is on, thus being a ramp signal when BG is on and being 0 when BG is off; islope is a ramp compensation signal, and is also a ramp signal when BG is switched on and is 0 when BG is switched off; idc is a direct current signal, so that BG is not changed whether being switched on or switched off; the Ics is an output current sampling signal and can change when a load changes, and particularly can change instantaneously when the S1-Sn branches are switched on or switched off; vramp is a ramp signal finally generated, and it can be seen that VDC decreases rapidly when Ics becomes suddenly large, and VDC increases rapidly when Ics becomes suddenly small.
In order to make the working principle of the circuit clearer in the load jump process (typically, the S1-SN branch circuit suddenly turning on and off), we further analyze the waveform of the transient jump.
Further, as shown in fig. 7, fig. 7 is a waveform diagram of a light load, jump and heavy load of the DCDC converter of the present invention. As can be seen from the figure, the dc value VDC of Vramp is higher before the jump, i.e. when the load is light, because the output current sampling signal Ico is smaller at this time. When the branches S1 to Sn are suddenly conducted to one or more paths, the load current Iload can be suddenly increased, the outputs Ics1 to Icsn of the current sampling modules of S1 to Sn can be rapidly increased corresponding to the conducted branches, and the total output current sampling signal Ics after passing through the adder ADD can be rapidly increased, so that the direct-current voltage value of Vramp is rapidly reduced, the response speed of Vea is very slow, the time for the Vramp peak value to rise to the Vea is increased, namely the duty ratio is increased, and the inductive current is also increased. Since the increase of the inductor current is fast, the inductor current will exceed the load current for a short time, the output voltage stops decreasing and rises slowly, and then the output voltage LOOP2 adjusts the output voltage to the set voltage value. After the heavy load is stabilized, the dc value VDC of Vramp is low because the output current sampling signal Ics is large. It can be seen that, in the process of changing from light load jump to heavy load, the first half of the output voltage drop process is mainly controlled by the output current LOOP1, and the second half of the output voltage rise process is controlled by the output voltage LOOP2, so that the output voltage undershoot Δ Vdrop is greatly reduced compared with the traditional process of completely controlling by LOOP2.
Further, as shown in fig. 8, fig. 8 is a waveform diagram of a heavy load, a skip load and a light load of the DCDC converter of the present invention. As can be seen from the figure, before the jump, i.e. when the load is heavy, the dc value VDC of Vramp is low because the output current sampling signal Ics is large at this time. When the branches S1-Sn suddenly turn off one or more branches, the load current Iload suddenly decreases, the output currents Ics 1-Icsn of the current sampling modules of S1-Sn are quickly reduced corresponding to the turned-on branches, and the total output current sampling signal Ics after passing through the adder ADD is quickly reduced, so that the direct current voltage value of Vramp is quickly increased, the response speed of Vea is slow, the time for the Vramp peak value to rise to the Vea is reduced, namely the duty ratio is reduced, and the inductive current is also reduced. Since the inductor current decreases rapidly, the inductor current will be lower than the load current for a short time, the output voltage stops rising and slowly decreases, and then the output voltage LOOP2 adjusts the output voltage to the set voltage value. After the light load is stabilized, the dc value VDC of Vramp is high because the output current sampling signal Ics is small. It can be seen that, during the process of the load jumping from heavy load to light load, the first half of the output voltage rising process is mainly controlled by the output current LOOP1, and the second half of the output voltage falling process is controlled by the output voltage LOOP2, so the overshoot Δ Vshoot of the output voltage is much reduced compared with the traditional process of completely controlling the output voltage LOOP2.
It can be seen that the DCDC converter described in the embodiments of the present application includes: the device comprises an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp wave generating module and a driving module, wherein one end of the peak current sampling module is connected with a drain electrode of the power tube, is connected with input voltage through an inductor and is connected with first output voltage through a diode, and the other end of the peak current sampling module is connected with the ramp wave generating module; one end of the ramp generating module is connected with the adder, the other end of the ramp generating module is connected with the negative input end of the comparator, the adder is also connected with a plurality of current sampling modules, one end of a switch corresponding to each current sampling module is connected with the first output voltage, and the other end of the switch outputs the corresponding second output voltage; the first output voltage is divided by a first resistor and a second resistor, a divided voltage signal of the first output voltage passing through the first resistor is connected to the negative input end of the error amplifier, the positive input end of the error amplifier is connected to a reference voltage, and the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network; the output end of the comparator is connected to one end of the driving module, the other end of the driving module is connected to the grid electrode of the power tube, and the source electrode of the power tube is grounded, so that the transient response speed of the load can be improved.
In the related art, the load transient response performance of the DCDC is poor, and is mainly limited by the output loop bandwidth: for BUCK converters, the output loop bandwidth is limited by the switching frequency, and for BOOST converters, the output loop bandwidth is limited by both the switching frequency and the right half-plane stack zero. In the embodiment of the application, the load current is sampled and output, the ramp signal Vramp is introduced, an output current loop is established for the ramp signal Vramp, the duty ratio can be rapidly adjusted through changing the Vramp to stabilize the output when the load current changes, the slow adjustment is not needed to be carried out through the output voltage loop, the limitation of the bandwidth of the output loop is avoided, meanwhile, the gain of the newly added output current loop is very small, the stability of the newly added output current loop is not needed to be adjusted through additionally adding a compensation network, and therefore the loop design complexity of the circuit cannot be increased.
In practical application, when the branches S1 to Sn are suddenly connected to one or more paths, the load current Iload is suddenly increased, the outputs Ics1 to Icsn of the current sampling modules of S1 to Sn are rapidly increased corresponding to the connected branches, the total output current sampling signal Ics after passing through the adder ADD is rapidly increased, the dc level value of the triangular wave Vramp is rapidly reduced after entering the ramp generating module, because the LOOP speed of LOOP1 is much greater than LOOP2, vea is basically kept unchanged at this time, a larger peak current is required when the peak value of the triangular wave Vramp rises to reach the value of Vea, and the rising rate of the inductive current is unchanged, so that the larger peak current means that a longer BG on time is required, that is, the duty ratio is increased. The inductor current increases and the energy supplied to the load increases as the duty cycle increases. Because the instant increase of the load current is directly fed back to Vramp through the output current LOOP LOOP1 to increase the duty ratio, and the load current does not depend on the output voltage LOOP LOOP2 any more, the reaction speed is very high, and the undershoot of the output voltage Vo is very small. When the branches S1 to Sn suddenly turn off one or more branches, the load current Iload suddenly decreases, the output currents Ics1 to Icsn of the current sampling modules of S1 to Sn are quickly reduced corresponding to the conducting branches, the total output current sampling signal Ics after passing through the adder ADD quickly drops, the direct current level value of the triangular wave Vramp can be quickly increased after entering the ramp generating module, because the LOOP speed of LOOP1 is far greater than LOOP2, vea basically keeps unchanged at the moment, the peak value of the triangular wave Vramp is increased to reach the value of Vea, smaller peak current is needed, the rising speed of the inductive current is unchanged, and the smaller peak current means that shorter BG on-time is needed, namely, the duty ratio is reduced. The inductor current is reduced after the duty cycle is reduced, and the energy supplied to the load is reduced. Because the load current becomes smaller instantly, the load current is directly fed back to Vramp through the output current LOOP LOOP1 to reduce the duty ratio, and the load current does not depend on the output voltage LOOP LOOP2 any more, so the reaction speed is very high, the overshoot of the output voltage Vo is very small, and further, the transient response speed of the load can be improved.
The embodiment of the present application further provides a switching power supply, which may include any one of the DCDC converters described above, and the switching power supply can improve a load transient response speed.
The embodiment of the present application further provides an electronic device, which may include any one of the DCDC converters or the switching power supply, and the electronic device can improve a load transient response speed. The electronic device may include at least one of: chips, chargers, outdoor power supplies, etc., without limitation.
The foregoing is an implementation of the embodiments of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiments of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.

Claims (9)

1. A DCDC converter, comprising: an error amplifier, a compensation network, a comparator, a peak current sampling module, a power tube, a ramp generating module and a driving module, wherein,
one end of the peak current sampling module is connected with a drain electrode of the power tube, is connected with an input voltage through an inductor and is connected with a first output voltage through a diode, and the other end of the peak current sampling module is connected with the ramp wave generating module;
one end of the ramp wave generation module is connected with an adder, the other end of the ramp wave generation module is connected with the negative input end of the comparator, the adder is further connected with a plurality of current sampling modules, one end of a switch corresponding to each current sampling module is connected with the first output voltage, and the other end of the switch outputs a corresponding second output voltage;
the first output voltage is divided by a first resistor and a second resistor, the first output voltage is connected to the negative input end of the error amplifier through a divided voltage signal of the first resistor, the positive input end of the error amplifier is connected to a reference voltage, and the output end of the error amplifier is connected to the positive input end of the comparator through the compensation network;
the output end of the comparator is connected to one end of the driving module, the other end of the driving module is connected to the grid electrode of the power tube, and the source electrode of the power tube is grounded;
wherein the DCDC converter is to:
superposing the output current sampling signals of each path in the plurality of current sampling modules to obtain a total output current sampling signal;
enabling the total output current sampling signal, the peak sampling current sampled by the peak current sampling module, the ramp compensation current and the direct current signal to pass through the ramp generating module to obtain a triangular wave signal;
wherein the ramp generating module comprises: a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first NMOS tube MN1 and a second NMOS tube MN2;
the ramp compensation current Islope is connected to a drain and a gate of the first PMOS transistor MP1, a source of the first PMOS transistor is connected to a source of the second PMOS transistor MP2, a source of the third PMOS transistor MP3, a source of the fourth PMOS transistor MP4, a source of the fifth PMOS transistor MP5, and a source of the sixth PMOS transistor MP6, and a gate of the first PMOS transistor MP1 is connected to a gate of the second PMOS transistor MP 2;
the drain electrode of the second PMOS transistor MP2 is connected to the drain electrode of the fourth PMOS transistor MP4, the drain electrode of the fifth PMOS transistor MP5, the drain electrode of the second NMOS transistor MN2, and the ground through a fourth resistor R, and the drain electrode of the second PMOS transistor MP2 is further configured to output the triangular wave signal Vramp;
the peak sampling current Ipk is connected to the grid electrode and the drain electrode of the third PMOS tube MP3, and the grid electrode of the third PMOS tube MP3 is connected with the grid electrode of the fourth PMOS tube MP 4; the drain electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the second NMOS tube MN2;
the total output current sampling signal Islope is accessed to a grid electrode and a drain electrode of the first NMOS tube MN1, the grid electrode of the first NMOS tube MN1 is connected with a grid electrode of the second NMOS tube MN2, and a source electrode of the first NMOS tube MN1 and a source electrode of the second NMOS tube MN2 are both grounded;
the direct current signal Idc is connected to the drain and the gate of the sixth PMOS transistor MP6, and the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth PMOS transistor MP 5.
2. The DCDC converter of claim 1, wherein the input voltage is coupled to ground through an input capacitor, and wherein the output of the diode is coupled to ground through an output capacitor.
3. The DCDC converter of claim 2, wherein the compensation network comprises: a first capacitor, a second capacitor and a third resistor;
the output end of the error amplifier is sequentially connected with the third resistor and the second capacitor, and the second capacitor is grounded;
the error amplifier is grounded through the first capacitor.
4. The DCDC converter of claim 1, wherein the DCDC converter is configured to:
when at least one branch circuit corresponding to the plurality of current sampling modules is conducted, the load current can be suddenly increased, the output current sampling signal of the current sampling module corresponding to the at least one branch circuit can also rapidly rise, the total output current sampling signal passing through the adder can rapidly rise, and the direct current level value of the triangular wave signal can be rapidly reduced after entering the ramp generating module.
5. The DCDC converter of claim 1, wherein the DCDC converter is configured to:
when at least one branch circuit corresponding to the plurality of current sampling modules is turned off, the load current can be suddenly reduced, the output current sampling signal of the current sampling module corresponding to the at least one branch circuit can be rapidly reduced, the total output current sampling signal after passing through the adder can be rapidly reduced, and the direct current level value of the triangular wave signal can be rapidly increased after entering the ramp generating module.
6. The DCDC converter of claim 1,
the first PMOS tube and the second PMOS tube form a current mirror for mirroring the ramp compensation current;
the third PMOS tube and the fourth PMOS tube form a current mirror for mirroring the peak sampling current;
the fifth PMOS tube and the sixth PMOS tube form a current mirror for mirroring the direct current signal;
the first NMOS tube and the second NMOS tube form a current mirror for mirroring a total output current sampling signal;
the ramp compensation current, the peak sampling current, the direct current signal and the total output current sampling signal all flow into the fourth resistor and are converted into the triangular wave signal, and the triangular wave signal satisfies the following relationship:
Figure 61164DEST_PATH_IMAGE001
here, vramp represents a triangular wave signal, islope represents a ramp compensation current, ipk represents a peak sampling current, idc represents a direct current signal, ics represents a total output current sampling signal, and R represents a resistance value of the fourth resistor.
7. The DCDC converter of claim 6,
when slope and Ipk are both signals changing from cycle to cycle, then the dc voltage signal of Vramp is determined according to the following formula:
Figure 106481DEST_PATH_IMAGE002
where VDC represents a dc voltage signal of Vramp.
8. A switching power supply characterized in that it comprises a DCDC converter according to any of claims 1-7.
9. An electronic device, characterized in that the electronic device comprises a DCDC converter according to any of claims 1-7, or a switching power supply according to claim 8.
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