CN115167214B

CN115167214B - Integrated chip for vehicle-mounted Ethernet, vehicle-mounted control system and vehicle

Info

Publication number: CN115167214B
Application number: CN202210832877.1A
Authority: CN
Inventors: 周立功; 蓝甲; 黄敏思
Original assignee: Guangzhou Zhiyuan Electronics Co Ltd
Current assignee: Guangzhou Zhiyuan Electronics Co Ltd
Priority date: 2022-07-14
Filing date: 2022-07-14
Publication date: 2024-07-16
Anticipated expiration: 2042-07-14
Also published as: CN115167214A

Abstract

The invention discloses an integrated chip for a vehicle-mounted Ethernet, a vehicle-mounted control system and a vehicle. The invention belongs to the technical field of automobiles. The integrated chip is in communication connection with the MAC controller through a communication interface and is used for sending and receiving data frames of the Ethernet; the integrated chip includes: the peripheral circuit, the PHY chip and the interface filter circuit are packaged in the integrated chip through a glue filling technology; the peripheral circuit is connected with the PHY chip and used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip; the interface filter circuit is connected with the PHY chip and is used for carrying out filter protection on the PHY chip. The technical scheme provided by the invention does not need to process the layout and design of the wiring between the peripheral circuit and the interface filter circuit, and only needs to design the wiring between the MAC controller and the PHY chip, thereby greatly simplifying the hardware design and avoiding the bad wiring from influencing the stability of data transmission.

Description

Integrated chip for vehicle-mounted Ethernet, vehicle-mounted control system and vehicle

Technical Field

The present invention relates to the field of automotive technologies, and in particular, to an integrated chip for a vehicle-mounted ethernet, a vehicle-mounted control system, and a vehicle.

Background

With the advancement of society, the Internet of vehicles has been used in automobile development technology. The vehicle networking senses the state information of the vehicle by using a sensing technology, and realizes intelligent management of traffic, intelligent decision of traffic information service and intelligent control of the vehicle by using a wireless communication network and a modern intelligent information processing technology. With the development of the internet of vehicles, the demand for chip functions in the vehicle-mounted ethernet is increasing, and PHY (Port PHYSICAL LAYER ) is a common abbreviation for OSI model physical layer. And ethernet is a technology that operates the OSI (Open System Interconnection Reference Model, open systems interconnection communication reference model) physical layer. An ethernet PHY is a chip that can send and receive ethernet data frames.

The existing vehicle-mounted Ethernet chip is complex in wiring and poor in data transmission quality, so that development and design of the vehicle-mounted Ethernet are difficult to meet, and the technical problem to be solved by the person skilled in the art is urgent.

Disclosure of Invention

The invention provides an integrated chip for a vehicle-mounted Ethernet, a vehicle-mounted control system and a vehicle, which do not need to process wiring layout and design between a peripheral circuit and an interface filter circuit, and only need to design wiring between a MAC controller and a PHY chip, thereby greatly simplifying hardware design and avoiding bad wiring from influencing the stability of data transmission.

The first aspect of the embodiment of the invention provides an integrated chip for a vehicle-mounted Ethernet, which is in communication connection with a MAC controller through a communication interface and is used for sending and receiving data frames of the Ethernet;

The integrated chip includes: the peripheral circuit, the PHY chip and the interface filter circuit are packaged in the integrated chip through a glue filling technology;

the peripheral circuit is connected with the PHY chip and used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip;

the interface filter circuit is connected with the PHY chip and is used for carrying out filter protection on the PHY chip.

A second aspect of the embodiment of the present invention provides a vehicle-mounted control system, including the integrated chip for a vehicle-mounted ethernet of the first aspect.

A third aspect of an embodiment of the present invention provides a vehicle, including the integrated chip for on-board ethernet of the first aspect.

The integrated chip, the vehicle-mounted control system and the vehicle for the vehicle-mounted Ethernet are packaged in the integrated chip through the glue filling technology, and the integrated chip is connected with the MAC controller through the communication interface to realize data communication. Therefore, the wiring layout and design between the peripheral circuit and the interface filter circuit are not required to be processed, only the wiring between the MAC controller and the PHY chip is required to be designed, the hardware design is greatly simplified, the bad wiring is avoided to influence the stability of data transmission, and the technical problems that the wiring of the existing vehicle-mounted Ethernet chip is complex, the data transmission quality is poor, and the development and design of the vehicle-mounted Ethernet are difficult to meet are solved.

Drawings

Fig. 1 is a schematic structural diagram of an integrated chip and a MAC controller according to an embodiment of the present invention;

Fig. 2 is an interface distribution schematic diagram of a PHY chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a peripheral circuit according to an embodiment of the present invention;

Fig. 4 is a schematic structural diagram of an interface filter circuit according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed but may include other elements not expressly listed or inherent to such article or apparatus.

Fig. 1 is a schematic structural diagram of an integrated chip and a MAC controller provided in an embodiment of the present invention, referring to fig. 1, which is an integrated chip for a vehicle-mounted ethernet provided in an embodiment of the present invention, where the integrated chip is connected to the MAC controller by a communication interface in a communication manner, and is used to send and receive data frames of the ethernet; the integrated chip includes: the peripheral circuit, the PHY chip and the interface filter circuit are packaged in the integrated chip through a glue filling technology; the peripheral circuit is connected with the PHY chip and used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip; the interface filter circuit is connected with the PHY chip and is used for carrying out filter protection on the PHY chip.

PHY is a port physical layer that typically connects the device MAC of a data link layer to a physical medium, such as fiber or copper cable. Typical PHYs include PCS (Physical Coding Sublayer ) and PMD (PHYSICAL MEDIA DEPENDENT, physical medium dependent sublayer). The PCS codes and decodes the transmitted and received information to make it easier for the receiver to recover the signal.

PHY chips are widely used in ethernet devices, where an ethernet PHY is a chip that can send and receive ethernet data frames. In addition, the PHY chip has no MAC address. Therefore, the PHY chip needs to be connected with the MAC controller through a communication interface to realize transmission and reception of the data frame. The MAC controller is responsible for completing data encapsulation and decapsulation of the 802.3ab, adapting to a physical interface of a hardware PHY chip and forming a communication interface of a physical layer. The PHY chip is a physical interface transceiver that implements the physical layer IEEE-802.3 standard, defining an ethernet PHY. The PHY chip can detect whether data is being transmitted on the network, and can provide an important function of connection with the peer device and display the state and working state of the current connection.

The PHY chip may send and receive data frames to and from the MAC controller. Because the PHY chip has no frame concept, when the PHY chip receives the data sent by the MAC controller, no matter the address or the CRC check bit data, 1 bit error detection code is added only every 4 bits, then the parallel data is converted into serial data stream data, and then the data is coded into analog signals according to the coding rule of a physical layer to send out the data. Among them, the encoding rule includes, but is not limited to, NRZ encoding or manchester encoding. The process of the PHY chip receiving data is the opposite, i.e., the decoding process. The PHY chip also has an important function of implementing part of the CSMA/CD function, i.e. it can detect whether there is data on the network to be transmitted, wait if so, wait for a random time to send out the data once the network is detected to be idle, and wait for a random time to resend the data if a data collision is found.

In the integrated chip of this embodiment, the PHY chip needs to be designed with a peripheral circuit and an interface filter circuit. The peripheral circuit may be a circuit in the circuit board, which is composed of one or more components such as a resistor, an inductor, a capacitor, and the like, and a wire connecting these components. The peripheral circuitry may be circuitry that causes the PHY chip to perform different functions. Specifically, the peripheral circuit in this embodiment may implement one or more of reset control, clock signal control, and operation mode control for the PHY chip.

Currently, UTP (Unshielded TWISTED PAIR ) is mostly used for data transmission lines between different components in peripheral circuits. However, since the peripheral circuit includes various components, the data transmission lines connecting these components are easily interfered by magnetic field signals and easily radiated to the outside, and thus it is generally required to perform anti-interference processing on the data transmission lines in the in-vehicle ethernet. The interface filter circuit is required to be designed when the vehicle-mounted Ethernet is designed, so that the design can play a role in protecting signal transmission, impedance matching, waveform restoration, signal clutter suppression and the like.

The present embodiment integrates peripheral circuitry, PHY chip, and interface filter circuitry on the chip. The peripheral circuit is connected with the PHY chip and used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip.

The reset control may be to restore the working state of the PHY chip to the original state, which is equivalent to initializing the PHY chip. The clock signal control may be that each operation corresponds to a time, and controls what data is transmitted or what operation is performed by the PHY chip at what time. The operating mode control may be an operating mode of the control PHY chip. For example, an operation mode of controlling the PHY chip to communicate with the MAC controller, an operation mode of address configuration of the PHY chip, and an operation mode of delay configuration of the reception clock timing. The interface filter circuit is connected with the PHY chip and is used for carrying out filter protection on the PHY chip without considering the distribution of data transmission lines between the peripheral circuit and the PHY chip. The technical scheme is designed in such a way, so that the hardware design in the vehicle-mounted Ethernet can be greatly simplified, and the bad wiring is prevented from affecting the stability of data transmission.

In this embodiment, optionally, the communication interface includes an RGMII interface and an RMII interface.

The determination of the working state of the PHY chip by the MAC control and the implementation of the control function are generally implemented by reading and writing PHY chip registers through the SMI (Serial Management Interface) interface. The MAC controller can synchronize the SMI bus and continuously read the data in the PHY chip register to know the current connection speed, duplex capability and other states of the PHY chip, and can also set the PHY chip register through the SMI bus to achieve the control purpose. Such as auto-negotiation on and off, etc. Specifically, data exchange is performed between the MAC controller and the PHY chip through a communication interface. Currently, more commonly used communication interfaces include GMII/RGMII, MII/RMII. MII/RMII is called a media independent interface, supports data transmission modes of 10Mbps and 100Mbps, and is mainly used for interconnecting the MAC controller and the PHY chip. MII interface, 10Mbps need clock 2.5MHz,100Mbps need clock 25MHz, one time transmission data is 4bit and the clock of MAC controller and PHY chip is not needed to synchronize. The RMII interface, which transmits data at a time of 2b it, requires a clock of 50MHz for 100mbps, and the MAC controller and PHY chip require the same clock for synchronization. GMII/RGMII is a gigabit media independent interface of the IEEE standard supporting a data transmission mode of 1000 Mbps. The GMII interface requires a 125MHz clock, 8 bits of data are transferred at a time, and the interface is similar to the MII interface. In a bit different way, the tx_clk of the MII interface is provided by the PHY chip to the MAC controller; while the GMII interface gtx_clk is given to the PHY chip by the MAC controller. The RGMII interface still requires a 125MHz clock, 4 bits of data to be transferred at a time, and samples are required on both the rising and falling edges of the clock in order to maintain a 1000Mbps rate.

As shown in fig. 2, the PHY chip and the MAC controller can perform data transmission through MDIO, MDC, TXD [0..3], TXC, TXEN, RXD [0..3], RXC, and RXDV. The MDIO is mainly used for managing bidirectional data between the MAC controller and the PHY chip; the MAC controller manages a data clock sent to the PHY chip through the MDC; the MAC controller sends data to the PHY chip through TXD [0..3 ]; the MAC controller sends clock data to the PHY chip through TXC; the MAC controller receives data transmitted by the PHY chip through RXD [0..3 ]. The MAC controller receives clock data transmitted from the PHY chip through the RXC.

In this embodiment, the PHY chip and the MAC controller in the integrated chip may use an RGMII interface or an RMII interface to implement communication. By the design, the upgrading design of the vehicle-mounted Ethernet can be facilitated for a user, and the overall production cost is reduced.

In this embodiment, optionally, the peripheral circuit includes a reset module, a clock module, and a mode configuration module, where the reset module, the clock module, and the mode configuration module are respectively connected to a reset pin, a clock signal pin, and a working mode pin of the PHY chip.

It can be understood that, in the on-vehicle ethernet, the clock module, the reset module and the mode configuration module are all necessary module structures for implementing various functions of the on-vehicle ethernet. The reset module is used for restoring the circuit to the original state. A clock module is an oscillating circuit that produces accurate motion like a clock. In the on-board ethernet, any operation is time-ordered, and the circuit that generates this time is the clock module. The mode configuration module is used for configuring the working mode of the circuit. Specifically, the reset module in this embodiment is connected to a reset pin of the PHY chip, so as to control and initialize the reset of the PHY chip in the vehicle ethernet. The clock module is connected with a clock signal pin of the PHY chip and provides a clock signal for the PHY chip so that the PHY chip can work according to time sequence. In practical applications, a clock signal is required when the PHY chip communicates with the MAC controller, and the clock module provides the clock signal. The mode configuration module is used for configuring the working mode of the PHY chip, and can comprise master-slave mode configuration, communication mode configuration with the MAC controller, address configuration of the PHY chip, delay configuration of receiving clock time sequence and the like. Wherein, master-slave mode configuration: when two devices are in communication, for example, a first device may communicate a synchronous ethernet clock over interface a on the first device to interface B on the second device. When the interface a and the interface B delivering the synchronous ethernet clock are the specific type of interface, the physical layer master-slave mode of the interface a and the interface B is also determined, that is, the master mode and the slave mode are determined. Communication mode configuration with MAC controller: the PHY chip is configured to transmit the first clock data to the MAC controller and/or the PHY chip is configured to receive the second clock data transmitted by the MAC controller. The technical scheme is designed in such a way, so that the stability and the accuracy of data transmission between the MAC controller and the integrated chip can be ensured when the integrated chip realizes different functions in the vehicle-mounted Ethernet.

As shown in fig. 3, in the present embodiment, optionally, the reset module includes a first power supply VDD1, a first resistor R1, a first diode D1, and a first capacitor C1; the cathode of the first diode D1 and one end of the first resistor R1 are connected with the first power supply VDD1, and the anode of the first diode D1 and the other end of the first resistor R1 are connected with a reset pin of the PHY chip; one end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected with a reset pin of the PHY chip.

In this embodiment, the first power supply VDD1 is 3.3V; the first diode D1 is a diode of model 1N4148 WS; the first resistor R1 is 10KΩ (+ -0.1%; the first capacitance C1 is 0.1 μf,16V. Specifically, after power-on, a current passes through the first resistor R1 and charges the first capacitor C1, and in the process that the RESET terminal voltage slowly rises from 0V to 3.3V at first, power-on RESET initialization can be achieved.

In this embodiment, optionally, the clock module includes a second capacitor C2, a third capacitor C3, and a crystal oscillator; one end of the second capacitor C2 and one end of the third capacitor C3 are grounded, and the other end of the second capacitor C2 and the other end of the third capacitor C3 are respectively connected with a clock signal pin of the PHY chip; the first end of the crystal oscillator is connected with one end of the second capacitor C2, the second end of the crystal oscillator is grounded, the third end of the crystal oscillator is connected with the other end of the third capacitor C3, and the fourth end of the crystal oscillator is grounded.

The second capacitor C2 and the third capacitor C3 are 15pf and 16v; the crystal oscillator was 25.0000MHz, + -20 ppm. Specifically, after power-up, the PHY chip drives the crystal oscillator to generate a clock, and the design of this embodiment can simplify the circuit structure for generating a clock signal and reduce the cost.

In this embodiment, optionally, the mode configuration module includes a second power supply VDD2, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7; one ends of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected with the second power supply VDD2, and the other ends of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are respectively connected with a first working mode pin, a second working mode pin, a third working mode pin and a fourth working mode pin of the PHY chip; one ends of the sixth resistor R6 and the seventh resistor R7 are grounded, and the other ends of the sixth resistor R6 and the seventh resistor R7 are respectively connected to a fifth working mode pin and a sixth working mode pin of the PHY chip.

The second power supply VDD2 is 3.3V; the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are all 10kΩ. Specifically, if there is a 10kΩ resistor connected to the second power supply VDD2, a high level is generated. The 10kΩ resistor is grounded and a low level is generated. After power-up, the PHY chip automatically samples the initial level of a specific pin, such as a high level or a low level, and determines the current operating mode of the PHY chip according to the sampled level state.

As shown in fig. 4, in this embodiment, optionally, the PHY chip includes a first filter pin and a second filter pin, and the interface filter circuit includes an ESD electrostatic tube D2, a first LRC low-pass filter, a second LRC low-pass filter, a common mode inductance module, a protection module, and a damping absorption module; the first LRC low-pass filter is connected with a first filtering pin of the PHY chip, and the second LRC low-pass filter is connected with a second filtering pin of the PHY chip; the ESD electrostatic tube D2, the common mode inductance module, the protection module and the damping absorption module are respectively connected to a first filtering pin and a second filtering pin of the PHY chip.

The first filtering pin is TRX_P, the second filtering pin is TRX_N, the MDI interface is a vehicle-mounted Ethernet physical layer differential communication interface, communication can be carried out based on a transmission medium standard of 1000BASE-T1 or 100BASE-T1, and the maximum signal rate can reach 1000Mbps. Under high-rate signal transmission, the MDI interface is very likely to interfere with the external EMI radiation, so that the normal operation of external equipment is affected, and meanwhile, under a severe use environment, the on-board Ethernet is not protected by an isolation transformer similar to the traditional Ethernet, so that the equipment in the use process is easy to damage a chip under the influence of static electricity, surge and the like. According to the technical scheme, the interface filter module is packaged in the integrated chip, so that the design can not only avoid EMI radiation interference, but also protect the PHY chip and various devices in the vehicle-mounted Ethernet.

In this embodiment, optionally, the first LRC low pass filter includes a first inductance L1, a tenth resistance R10, a thirteenth resistance R13, and an eighth capacitance C8; the first end of the first inductor L1 and the first end of the tenth resistor R10 are connected with the first filtering pin, the second end of the first inductor L1 and the first end of the thirteenth resistor R13 are connected, the second end of the tenth resistor R10 and the second end of the thirteenth resistor R13 are connected with the first end of the eighth capacitor C8, and the second end of the eighth capacitor C8 is grounded; the second LRC low-pass filter comprises a third inductor L3, an eleventh resistor R11, a twelfth resistor R12 and a seventh capacitor C7; the first end of the third inductor L3 and the first end of the eleventh resistor R11 are connected with the second filtering pin, the second end of the third inductor L3 is connected with the first end of the twelfth resistor R12, the second end of the eleventh resistor R11 and the second end of the twelfth resistor R12 are connected with the first end of the seventh capacitor C7, and the second end of the seventh capacitor C7 is grounded; the common-mode inductance module comprises a common-mode inductance L2, the common-mode inductance L2 is connected between the first filtering pin and the second filtering pin, the protection module comprises a fourth capacitor C4 and a fifth capacitor C5, and the fourth capacitor C4 and the fifth capacitor C5 are both connected with the common-mode inductance L2; the damping absorption module comprises a sixth capacitor C6, an eighth resistor R8, a ninth resistor R9 and a fourteenth resistor R14; the sixth capacitor C6 is connected with the fourteenth resistor R14 in parallel and then grounded; the eighth resistor R8 and the ninth resistor R9 are connected in parallel and then connected with the protection module, the sixth capacitor C6 and the fourteenth resistor R14, respectively.

The first inductor L1 and the third inductor L3 are 120mH; the tenth resistor R10, thirteenth resistor R13, eleventh resistor R11, and twelfth resistor R12 are 50Ω; the seventh capacitor C7 and the eighth capacitor C8 are 150pF and 100V; common mode inductance L2 is SDCW2012-2-900TF; the fourth capacitor C4 and the fifth capacitor C5 are 0.1 mu F and 100V; the eighth resistor R8 and the ninth resistor R9 are 1KΩ (+ -5%; the sixth capacitance C6 is 4.7nF,630V; the fourteenth resistor R14 is 100KΩ (+ -5%). The first inductor L1, the tenth resistor R10, the thirteenth resistor R13, the eighth capacitor C8, the third inductor L3, the eleventh resistor R11, the twelfth resistor R12, and the seventh capacitor C7 ensure that the LRC low-pass filter can maintain a 100 Ω differential impedance, and the interface filter circuit in this embodiment is strictly simulated by the ADS software, so that it can be ensured that spurious harmonic signals on a hundred mega network or gigabit network communication circuit can be effectively filtered under the 100 Ω differential impedance, and the signal transmission of the interface filter circuit is not affected. The ESD electrostatic tube D2 is an ultra-low junction capacitor, so that the vehicle-mounted Ethernet PHY can be effectively protected when external static electricity is generated. The common mode inductance L2 can filter out common mode interference on the MDI interface line. The fourth capacitor C4 and the fifth capacitor C5 provide DC direct current isolation protection for the MDI interface, so that the damage of an external fault line or the damage of direct current voltage to devices in the PHY chip can be prevented, the sixth capacitor C6 is in a conducting state in a high-frequency state, and resonance energy of a voltage peak of the communication interface in the working process is absorbed through the eighth resistor R8 and the ninth resistor R9, so that the EMI radiation interference can be avoided.

The embodiment of the invention provides a vehicle-mounted control system, which comprises the integrated chip for the vehicle-mounted Ethernet.

The embodiment of the invention provides a vehicle, which comprises the integrated chip for the vehicle-mounted Ethernet.

The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present utility model, and are not to be construed as limiting the scope of the utility model. It should be noted that any modifications, equivalent substitutions, improvements, etc. made by those skilled in the art without departing from the spirit and principles of the present utility model are intended to be included in the scope of the present utility model.

Claims

1. The integrated chip is used for the vehicle-mounted Ethernet and is characterized in that the integrated chip is in communication connection with the MAC controller through a communication interface and is used for sending and receiving data frames of the Ethernet;

the integrated chip includes: the peripheral circuit, the interface filter circuit and the PHY chip are packaged in the integrated chip through a glue filling technology;

the peripheral circuit is connected with the PHY chip and is used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip;

the interface filter circuit is connected with the PHY chip and is used for carrying out filter protection on the PHY chip;

the PHY chip comprises a first filtering pin and a second filtering pin, and the interface filtering circuit comprises an ESD electrostatic tube (D2), a first LRC low-pass filter, a second LRC low-pass filter, a common mode inductance module, a protection module and a damping absorption module;

the first LRC low-pass filter is connected with a first filtering pin of the PHY chip, and the second LRC low-pass filter is connected with a second filtering pin of the PHY chip;

The ESD electrostatic tube (D2), the common mode inductance module, the protection module and the damping absorption module are respectively connected between a first filtering pin and a second filtering pin of the PHY chip;

Wherein the first LRC low pass filter includes a first inductance (L1), a tenth resistance (R10), a thirteenth resistance (R13), and an eighth capacitance (C8); the first end of the first inductor (L1) and the first end of the tenth resistor (R10) are connected with the first filtering pin, the second end of the first inductor (L1) and the first end of the thirteenth resistor (R13) are connected, the second end of the tenth resistor (R10) and the second end of the thirteenth resistor (R13) are connected with the first end of the eighth capacitor (C8), and the second end of the eighth capacitor (C8) is grounded;

The second LRC low pass filter includes a third inductance (L3), an eleventh resistance (R11), a twelfth resistance (R12), and a seventh capacitance (C7); the first end of the third inductor (L3) and the first end of the eleventh resistor (R11) are connected with the second filtering pin, the second end of the third inductor (L3) and the first end of the twelfth resistor (R12) are connected, the second end of the eleventh resistor (R11) and the second end of the twelfth resistor (R12) are connected with the first end of the seventh capacitor (C7), and the second end of the seventh capacitor (C7) is grounded;

The common mode inductance module comprises a common mode inductance (L2), the common mode inductance (L2) is connected between the first filtering pin and the second filtering pin, the protection module comprises a fourth capacitor (C4) and a fifth capacitor (C5), and the fourth capacitor (C4) and the fifth capacitor (C5) are both connected with the common mode inductance (L2);

The damping absorption module comprises a sixth capacitor (C6), an eighth resistor (R8), a ninth resistor (R9) and a fourteenth resistor (R14);

the sixth capacitor (C6) is connected with the fourteenth resistor (R14) in parallel and then grounded;

the eighth resistor (R8) and the ninth resistor (R9) are connected in parallel and then are respectively connected with the protection module, the sixth capacitor (C6) and the fourteenth resistor (R14).

2. The integrated chip for in-vehicle ethernet as recited in claim 1, wherein said communication interface comprises an RGMII interface and an RMII interface.

3. The integrated chip for the on-board ethernet according to claim 1, wherein said peripheral circuit comprises a reset module, a clock module, and a mode configuration module, said reset module, said clock module, and said mode configuration module being respectively connected to a reset pin, a clock signal pin, and an operational mode pin of said PHY chip.

4. An integrated chip for an on-board ethernet according to claim 3, wherein said reset module comprises a first power supply (VDD 1), a first resistor (R1), a first diode (D1) and a first capacitor (C1);

The cathode of the first diode (D1) and one end of the first resistor (R1) are connected with the first power supply (VDD 1), and the anode of the first diode (D1) and the other end of the first resistor (R1) are connected with a reset pin of the PHY chip;

One end of the first capacitor (C1) is grounded, and the other end of the first capacitor (C1) is connected with a reset pin of the PHY chip.

5. An integrated chip for an on-board ethernet according to claim 3, wherein said clock module comprises a second capacitor (C2), a third capacitor (C3) and a crystal oscillator;

one end of the second capacitor (C2) and one end of the third capacitor (C3) are grounded, and the other end of the second capacitor (C2) and the other end of the third capacitor (C3) are respectively connected with two clock signal pins of the PHY chip;

The first end of the crystal oscillator is connected with the other end of the second capacitor (C2), the second end of the crystal oscillator is grounded, the third end of the crystal oscillator is connected with the other end of the third capacitor (C3), and the fourth end of the crystal oscillator is grounded.

6. The integrated chip for an on-board ethernet according to claim 3, wherein said mode configuration module comprises a second power supply (VDD 2), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6), and a seventh resistor (R7);

One ends of the second resistor (R2), the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) are all connected with the second power supply (VDD 2), and the other ends of the second resistor (R2), the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) are respectively connected with a first working mode pin, a second working mode pin, a third working mode pin and a fourth working mode pin of the PHY chip;

One ends of the sixth resistor (R6) and the seventh resistor (R7) are grounded, and the other ends of the sixth resistor (R6) and the seventh resistor (R7) are respectively connected to a fifth working mode pin and a sixth working mode pin of the PHY chip.

7. An in-vehicle control system comprising an integrated chip for in-vehicle ethernet as claimed in any of claims 1-6.

8. A vehicle comprising an integrated chip for on-board ethernet according to any of claims 1-6.