CN115167214A

CN115167214A - Integrated chip for vehicle-mounted Ethernet, vehicle-mounted control system and vehicle

Info

Publication number: CN115167214A
Application number: CN202210832877.1A
Authority: CN
Inventors: 周立功; 蓝甲; 黄敏思
Original assignee: Guangzhou Zhiyuan Electronics Co Ltd
Current assignee: Guangzhou Zhiyuan Electronics Co Ltd
Priority date: 2022-07-14
Filing date: 2022-07-14
Publication date: 2022-10-11
Anticipated expiration: 2042-07-14
Also published as: CN115167214B

Abstract

The invention discloses an integrated chip for a vehicle-mounted Ethernet, a vehicle-mounted control system and a vehicle. The invention belongs to the technical field of automobiles. The integrated chip is in communication connection with the MAC controller through a communication interface and is used for sending and receiving data frames of the Ethernet; the integrated chip includes: the peripheral circuit, the interface filter circuit and the PHY chip are packaged in the integrated chip through a glue pouring technology; the peripheral circuit is connected with the PHY chip and is used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip; the interface filter circuit is connected with the PHY chip and used for carrying out filtering protection on the PHY chip. According to the technical scheme provided by the invention, the wiring layout and design between the peripheral circuit and the interface filter circuit do not need to be processed, and only the wiring between the MAC controller and the PHY chip needs to be designed, so that the hardware design is greatly simplified, and the influence of bad wiring on the stability of data transmission is avoided.

Description

Integrated chip for vehicle-mounted Ethernet, vehicle-mounted control system and vehicle

Technical Field

The invention relates to the technical field of automobiles, in particular to an integrated chip for a vehicle-mounted Ethernet, a vehicle-mounted control system and a vehicle.

Background

With the progress of society, the internet of vehicles has been mature and applied in the automobile development technology. The Internet of vehicles senses the state information of vehicles by using a sensing technology and realizes intelligent management of traffic, intelligent decision of traffic information service and intelligent control of vehicles by using a wireless communication network and a modern intelligent information processing technology. With the development of the internet of vehicles, the demand for chip functions in the vehicle-mounted ethernet network is increasing, and the PHY (Port Physical Layer) is a common abbreviation for the OSI model Physical Layer. Ethernet is a technology for operating the OSI (Open System Interconnection Reference Model) physical layer. An ethernet PHY is a chip that can send and receive ethernet data frames.

The existing vehicle-mounted Ethernet chip is complex in wiring and poor in data transmission quality, so that the development and design of the vehicle-mounted Ethernet are difficult to meet, and the technical problem to be solved by technical personnel in the field is urgently needed.

Disclosure of Invention

The invention provides an integrated chip for a vehicle-mounted Ethernet, a vehicle-mounted control system and a vehicle, which are not required to process wiring layout and design between a peripheral circuit and an interface filter circuit, only wiring between an MAC controller and a PHY chip is required to be designed, hardware design is greatly simplified, and the influence of bad wiring on data transmission stability is avoided.

A first aspect of the embodiments of the present invention provides an integrated chip for a vehicle-mounted ethernet, where the integrated chip is in communication connection with an MAC controller through a communication interface, and is configured to send and receive data frames of the ethernet;

the integrated chip includes: the peripheral circuit, the interface filter circuit and the PHY chip are packaged in the integrated chip through a glue pouring technology;

the peripheral circuit is connected with the PHY chip and is used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip;

the interface filter circuit is connected with the PHY chip and used for carrying out filtering protection on the PHY chip.

A second aspect of an embodiment of the present invention provides a vehicle-mounted control system, including the integrated chip for a vehicle-mounted ethernet in the first aspect.

A third aspect of the embodiments of the present invention provides a vehicle, including the integrated chip for an onboard ethernet network of the first aspect.

According to the integrated chip for the vehicle-mounted Ethernet, the vehicle-mounted control system and the vehicle, the PHY chip, the peripheral circuit and the interface filter circuit are packaged in the integrated chip through the glue pouring technology, and the integrated chip is connected with the MAC controller through the communication interface to achieve data communication. Therefore, wiring layout and design between a peripheral circuit and an interface filter circuit do not need to be processed, only wiring between the MAC controller and the PHY chip needs to be designed, hardware design is greatly simplified, and the problem that poor wiring affects data transmission stability is avoided, so that the technical problem that development and design of the vehicle-mounted Ethernet are difficult to meet due to the fact that the existing vehicle-mounted Ethernet chip is complex in wiring and poor in data transmission quality is solved.

Drawings

Fig. 1 is a schematic structural diagram of an integrated chip and an MAC controller according to an embodiment of the present invention;

fig. 2 is a schematic diagram of interface distribution of a PHY chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a peripheral circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an interface filter circuit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such system, article, or apparatus.

Fig. 1 is a schematic structural diagram of an integrated chip and an MAC controller according to an embodiment of the present invention, and please refer to fig. 1, which is an integrated chip for a vehicle-mounted ethernet according to an embodiment of the present invention, wherein the integrated chip is communicatively connected to the MAC controller through a communication interface, and is configured to send and receive data frames of the ethernet; the integrated chip includes: the peripheral circuit, the interface filter circuit and the PHY chip are packaged in the integrated chip through a glue pouring technology; the peripheral circuit is connected with the PHY chip and is used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip; the interface filter circuit is connected with the PHY chip and used for carrying out filtering protection on the PHY chip.

The PHY is a port physical layer, and in general, connects a device MAC of a data link layer to a physical medium, such as an optical fiber or copper cable. Typical PHYs include PCS (Physical Coding Sublayer) and PMD (Physical Media Dependent Sublayer). The PCS encodes and decodes the transmitted and received information to make it easier for the receiver to recover the signal.

PHY chips are widely used in ethernet devices, and an ethernet PHY is a chip that can send and receive ethernet data frames. Furthermore, the PHY chip has no MAC address. Therefore, the PHY chip needs to be connected to the MAC controller through a communication interface to transmit and receive data frames. The MAC controller is responsible for realizing the encapsulation and the decapsulation of the 802.3ab data, and is also responsible for adapting a physical interface of a hardware PHY chip to form a communication interface of a physical layer. The PHY chip is a physical interface transceiver that implements the physical layer IEEE-802.3 standard, defining an ethernet PHY. The PHY chip can detect whether data is transmitted on the network, and can provide important functions for connecting with the opposite device and display the current connection state and working state of the PHY chip.

The PHY chip may transmit and receive data frames from the MAC controller to the MAC controller. Because the PHY chip has no frame concept, when the PHY chip receives data sent by the MAC controller, no matter the data is address or CRC check bit data, 1 bit error detection code is added for every 4 bits, then parallel data is converted into serial data stream, and then the data is coded into analog signals according to the coding rule of a physical layer to send the data out. The encoding rules include, but are not limited to, NRZ encoding or manchester encoding. The PHY chip receives data in the reverse way, i.e. the decoding process. The PHY chip also has an important function of implementing part of the CSMA/CD function, i.e. it can detect whether there is data on the network to transmit, wait if there is data on the network, wait for a random time to transmit data once the network is detected to be idle, and wait for a random time to retransmit data if data collision is found.

In the integrated chip in this embodiment, peripheral circuit design and interface filter circuit design need to be performed on the PHY chip. The peripheral circuit may be a circuit formed by one or more components such as resistors, inductors and capacitors in the circuit board, and wires connecting the components. The peripheral circuits may be circuits that cause the PHY chip to implement different functions. Specifically, the peripheral circuit in this embodiment may implement one or more of reset control, clock signal control, and operation mode control on the PHY chip.

At present, UTP (Unshielded Twisted Pair) is mostly used for data transmission lines between different components in peripheral circuits. However, since the peripheral circuit includes various components, and data transmission lines connecting these components are easily interfered by magnetic field signals and easily radiate to the outside, it is generally necessary to perform anti-interference processing on the data transmission lines in the vehicle-mounted ethernet. In the embodiment, an interface filter circuit needs to be designed when the vehicle-mounted Ethernet is designed, so that the design can play a role in protecting signal transmission, impedance matching, waveform restoration, signal clutter suppression and the like.

The embodiment integrates the peripheral circuit, the PHY chip and the interface filter circuit on a chip. The peripheral circuit is connected with the PHY chip and is used for carrying out at least one of reset control, clock signal control and working mode control on the PHY chip.

The reset control may be to restore the operating state of the PHY chip to the original state, which is equivalent to initializing the PHY chip. The clock signal control may be time for each job, controlling when the PHY chip sends what data or does what job. The operation mode control may be to control an operation mode of the PHY chip. For example, an operation mode of controlling the PHY chip to communicate with the MAC controller, an operation mode of address configuration of the PHY chip, and an operation mode of delay configuration of the reception clock timing. The interface filter circuit is connected with the PHY chip and used for carrying out filtering protection on the PHY chip without considering the distribution of a data transmission line between the peripheral circuit and the PHY chip. This technical scheme designs like this, can simplify the hardware design in the on-vehicle ethernet greatly, avoids bad walk the stability that the line influences data transmission.

In this embodiment, optionally, the communication interface includes an RGMII interface and an RMII interface.

The determination of the operating state of the PHY chip and the implementation of the control function by the MAC control are generally implemented by reading and writing PHY chip registers through an SMI (Serial Management Interface) Interface. The MAC controller can synchronize the SMI bus, continuously read the data in the PHY chip register to know the current states of the PHY chip such as connection speed, duplex capability and the like, and can also set the PHY chip register through the SMI bus to achieve the control purpose. Such as auto-negotiated opening and closing, etc. Specifically, data exchange is performed between the MAC controller and the PHY chip through a communication interface. Currently, the more common communication interfaces include GMII/RGMII, MII/RMII. The MII/RMII is called a media independent interface, supports data transmission modes of 10Mbps and 100Mbps, and is mainly used for interconnection of the MAC controller and the PHY chip. The MII interface needs 2.5MHz for 10Mbps clock, 25MHz for 100Mbps clock, 4bit for one-time data transmission and does not need the clocks of the MAC controller and the PHY chip for synchronization. The RMII interface needs 50MHz clock for transmitting data 2bit and 100Mbps at one time, and the MAC controller and the PHY chip need the same clock for synchronization. GMII/RGMII is a gigabit media independent interface of the IEEE standard, supporting a data transmission mode of 1000Mbps. The GMII interface requires a 125MHz clock, with 8 bits of data transmitted at one time, and is similar to the MII interface. The difference is that the TX _ CLK of the MII interface is sent to the MAC controller by the PHY chip; and the GTX _ CLK of the GMII interface is given to the PHY chip by the MAC controller. The RGMII interface still needs a 125MHz clock, the data is transmitted at one time and is 4 bits, and in order to keep the rate of 1000Mbps, the sampling is needed on the rising edge and the falling edge of the clock.

As shown in FIG. 2, the PHY chip and the MAC controller may perform data transmission via MDIO, MDC, TXD [0..3], TXC, TXEN, RXD [0..3], RXC, and RXDV. The MDIO is mainly used for managing bidirectional data between the MAC controller and the PHY chip; the MAC controller sends a data clock to the PHY chip through the MDC management; the MAC controller sends data to the PHY chip through TXD [0..3 ]; the MAC controller sends the clock data to the PHY chip through the TXC; the MAC controller receives the data transmitted by the PHY chip through the RXD [0..3 ]. And the MAC controller receives clock data transmitted by the PHY chip through the RXC.

In this embodiment, the PHY chip and the MAC controller in the integrated chip may implement communication using an RGMII interface or an RMII interface. Due to the design, the upgrading design of the vehicle-mounted Ethernet by a user can be facilitated, and the overall production cost is reduced.

In this embodiment, optionally, the peripheral circuit includes a reset module, a clock module, and a mode configuration module, where the reset module, the clock module, and the mode configuration module are respectively connected to a reset pin, a clock signal pin, and a working mode pin of the PHY chip.

It can be understood that, in the vehicle-mounted ethernet, the clock module, the reset module and the mode configuration module are all module structures essential for realizing various functions of the vehicle-mounted ethernet. The reset module is used for restoring the circuit to the original state. The clock module is an oscillating circuit that produces accurate movement like a clock. In the vehicle ethernet, any work is in time sequence, and the circuit that generates this time is the clock module. The mode configuration module is used for configuring the working mode of the circuit. Specifically, the reset module in this embodiment is connected to a reset pin of the PHY chip, so as to perform reset control and initialization on the PHY chip in the vehicle-mounted ethernet. The clock module is connected with a clock signal pin of the PHY chip and provides a clock signal for the PHY chip so that the PHY chip can work according to a time sequence. In practical applications, when the PHY chip communicates with the MAC controller, a clock signal is required, and the clock module provides the clock signal. The mode configuration module is used for configuring the working mode of the PHY chip, and may include a master-slave mode configuration, a communication mode configuration with the MAC controller, an address configuration of the PHY chip, a delay configuration of a receiving clock timing, and the like. Wherein, the master-slave mode configuration: when two devices are communicating, for example, a first device may pass a synchronous ethernet clock through interface a on the first device to interface B of a second device. When the interface A and the interface B which transfer the synchronous Ethernet clock are interfaces of a specific type, the physical layer master-slave mode of the interface A and the interface B, namely the master mode and the slave mode, is also determined. Communication mode configuration with the MAC controller: and configuring the PHY chip to send first clock data to the MAC controller and/or configuring the PHY chip to receive second clock data sent by the MAC controller. By the design of the technical scheme, the stability and the accuracy of data transmission between the MAC controller and the integrated chip can be ensured when the integrated chip realizes different functions in the vehicle-mounted Ethernet.

As shown in fig. 3, in this embodiment, optionally, the reset module includes a first power supply VDD1, a first resistor R1, a first diode D1, and a first capacitor C1; the cathode of the first diode D1 and one end of the first resistor R1 are both connected with a first power supply VDD1, and the anode of the first diode D1 and the other end of the first resistor R1 are both connected with a reset pin of the PHY chip; one end of the first capacitor C1 is grounded, and the other end of the first capacitor C1 is connected to a reset pin of the PHY chip.

In this embodiment, the first power supply VDD1 is 3.3V; the first diode D1 is a 1N4148WS type diode; the first resistor R1 is 10K omega +/-0.1%; the first capacitance C1 is 0.1 μ F,16V. Specifically, after power-on, a current flows through the first resistor R1 and charges the first capacitor C1, and in the process that the RESET terminal voltage slowly rises from 0V to 3.3V at the beginning, power-on RESET initialization can be realized.

In this embodiment, optionally, the clock module includes a second capacitor C2, a third capacitor C3, and a crystal oscillator; one end of the second capacitor C2 and one end of the third capacitor C3 are both grounded, and the other end of the second capacitor C2 and the other end of the third capacitor C3 are respectively connected with a clock signal pin of the PHY chip; the first end of the crystal oscillator is connected with one end of the second capacitor C2, the second end of the crystal oscillator is grounded, the third end of the crystal oscillator is connected with the other end of the third capacitor C3, and the fourth end of the crystal oscillator is grounded.

The second capacitor C2 and the third capacitor C3 are both 15pF and 16V; the crystal oscillator was 25.0000MHz,. + -. 20ppm. Specifically, after power is supplied, the PHY chip drives the crystal oscillator to generate a clock, and this embodiment is designed to simplify a circuit structure for generating a clock signal and reduce cost.

In this embodiment, optionally, the mode configuration module includes a second power supply VDD2, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7; one end of each of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 is connected with the second power supply VDD2, and the other end of each of the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 is connected with the first working mode pin, the second working mode pin, the third working mode pin and the fourth working mode pin of the PHY chip respectively; one ends of the sixth resistor R6 and the seventh resistor R7 are both grounded, and the other ends of the sixth resistor R6 and the seventh resistor R7 are connected to the fifth operating mode pin and the sixth operating mode pin of the PHY chip, respectively.

The second power supply VDD2 is 3.3V; the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are all 10K omega. Specifically, if a 10K Ω resistor is connected to the second power supply VDD2, a high level is generated. Grounding the 10K omega resistor results in a low level. After power-on, the PHY chip may automatically sample an initial level, such as a high level or a low level, of a specific pin, and determine a current operating mode of the PHY chip according to a sampled level state.

As shown in fig. 4, in this embodiment, optionally, the PHY chip includes a first filtering pin and a second filtering pin, and the interface filtering circuit includes an ESD electrostatic discharge tube D2, a first LRC low-pass filter, a second LRC low-pass filter, a common-mode inductance module, a protection module, and a damping absorption module; the first LRC low-pass filter is connected with a first filtering pin of the PHY chip, and the second LRC low-pass filter is connected with a second filtering pin of the PHY chip; the ESD electrostatic tube D2, the common-mode inductance module, the protection module and the damping absorption module are respectively connected to a first filtering pin and a second filtering pin of the PHY chip.

The first filtering pin is TRX _ P, the second filtering pin is TRX _ N, the MDI interface is a vehicle-mounted Ethernet physical layer differential communication interface, communication can be carried out based on a transmission medium standard of 1000BASE-T1 or 100BASE-T1, and the signal rate can reach 1000Mbps at most. Under high-rate signal transmission, the MDI interface is likely to generate EMI radiation interference to the outside world, affecting the normal operation of external devices, and at the same time, under a severe use environment, because the vehicle-mounted ethernet does not have the protection of an isolation transformer similar to the conventional ethernet, the device in the use process is easily damaged by the chip under the influence of static electricity, surge, and the like. According to the technical scheme, the interface filtering module is packaged in the integrated chip, so that the design can not only avoid EMI radiation interference, but also protect various devices in the PHY chip and the vehicle-mounted Ethernet.

In this embodiment, optionally, the first LRC low-pass filter includes a first inductor L1, a tenth resistor R10, a thirteenth resistor R13, and an eighth capacitor C8; a first end of the first inductor L1 and a first end of the tenth resistor R10 are both connected to the first filtering pin, a second end of the first inductor L1 is connected to a first end of the thirteenth resistor R13, a second end of the tenth resistor R10 and a second end of the thirteenth resistor R13 are both connected to a first end of the eighth capacitor C8, and a second end of the eighth capacitor C8 is grounded; the second LRC low-pass filter comprises a third inductor L3, an eleventh resistor R11, a twelfth resistor R12 and a seventh capacitor C7; a first end of a third inductor L3 and a first end of an eleventh resistor R11 are connected with a second filtering pin, a second end of the third inductor L3 is connected with a first end of a twelfth resistor R12, a second end of the eleventh resistor R11 and a second end of the twelfth resistor R12 are connected with a first end of a seventh capacitor C7, and a second end of the seventh capacitor C7 is grounded; the common-mode inductor module comprises a common-mode inductor L2, the common-mode inductor L2 is connected between the first filtering pin and the second filtering pin, the protection module comprises a fourth capacitor C4 and a fifth capacitor C5, and the fourth capacitor C4 and the fifth capacitor C5 are both connected with the common-mode inductor L2; the damping absorption module comprises a sixth capacitor C6, an eighth resistor R8, a ninth resistor R9 and a fourteenth resistor R14; the sixth capacitor C6 is connected with the fourteenth resistor R14 in parallel and then grounded; the eighth resistor R8 and the ninth resistor R9 are connected in parallel and then are respectively connected with the protection module, the sixth capacitor C6 and the fourteenth resistor R14.

The first inductor L1 and the third inductor L3 are both 120mH; the tenth resistor R10, the thirteenth resistor R13, the eleventh resistor R11, and the twelfth resistor R12 are all 50 Ω; the seventh capacitor C7 and the eighth capacitor C8 are both 150pF,100V; the common-mode inductor L2 is SDCW2012-2-900TF; the fourth capacitor C4 and the fifth capacitor C5 are both 0.1 muF and 100V; the eighth resistor R8 and the ninth resistor R9 are both 1K omega +/-5%; the sixth capacitor C6 is 4.7nF,630V; the fourteenth resistance R14 is 100K Ω, ± 5%. The first inductor L1, the tenth resistor R10, the thirteenth resistor R13, the eighth capacitor C8, the third inductor L3, the eleventh resistor R11, the twelfth resistor R12, and the seventh capacitor C7 ensure that the LRC low-pass filter can maintain 100 Ω differential impedance, and the interface filter circuit in this embodiment is strictly simulated by ADS software, so that stray harmonic signals on a hundred-mega network or gigabit network communication line can be effectively filtered under 100 Ω differential impedance, and signal transmission of the interface filter circuit is not affected. The ESD electrostatic tube D2 is an ultra-low junction capacitor, and can ensure that the vehicle-mounted Ethernet PHY is effectively protected when in external static electricity. And the common-mode inductor L2 can filter out common-mode interference on the MDI interface line. The fourth capacitor C4 and the fifth capacitor C5 provide DC direct current isolation protection for the MDI interface, can prevent external wrong connection or direct current voltage from damaging devices in the PHY chip, and the sixth capacitor C6 is in a conducting state under a high-frequency state, and absorbs resonance energy of voltage spikes of the communication interface in the working process through the eighth resistor R8 and the ninth resistor R9, so that EMI radiation interference can be avoided.

The embodiment of the invention provides a vehicle-mounted control system which comprises the integrated chip for the vehicle-mounted Ethernet.

The embodiment of the invention provides a vehicle, which comprises the integrated chip for the vehicle-mounted Ethernet of the embodiment.

The above embodiments are further detailed to explain the objects, technical solutions and advantages of the present invention, and it should be understood that the above embodiments are only examples of the present invention and are not intended to limit the scope of the present invention. It should be understood that any modifications, equivalents, improvements and the like, which come within the spirit and principle of the invention, may occur to those skilled in the art and are intended to be included within the scope of the invention.

Claims

1. An integrated chip for a vehicle-mounted Ethernet is characterized in that the integrated chip is in communication connection with an MAC controller through a communication interface and used for sending and receiving data frames of the Ethernet;

2. The integrated chip for vehicular ethernet according to claim 1, wherein said communication interface comprises an RGMII interface and an RMII interface.

3. The integrated chip for vehicle-mounted Ethernet according to claim 1, wherein the peripheral circuit comprises a reset module, a clock module and a mode configuration module, and the reset module, the clock module and the mode configuration module are respectively connected with a reset pin, a clock signal pin and an operation mode pin of the PHY chip.

4. The integrated chip for vehicle Ethernet of claim 3, wherein the reset module comprises a first power supply (VDD 1), a first resistor (R1), a first diode (D1) and a first capacitor (C1);

the cathode of the first diode (D1) and one end of the first resistor (R1) are both connected with the first power supply (VDD 1), and the anode of the first diode (D1) and the other end of the first resistor (R1) are both connected with the reset pin of the PHY chip;

one end of the first capacitor (C1) is grounded, and the other end of the first capacitor (C1) is connected with a reset pin of the PHY chip.

5. The integrated chip for vehicular Ethernet of claim 3, wherein the clock module comprises a second capacitor (C2), a third capacitor (C3) and a crystal oscillator;

one end of the second capacitor (C2) and one end of the third capacitor (C3) are grounded, and the other end of the second capacitor (C2) and the other end of the third capacitor (C3) are respectively connected with a clock signal pin of the PHY chip;

and a first end of the crystal oscillator is connected with one end of a second capacitor (C2), a second end of the crystal oscillator is grounded, a third end of the crystal oscillator is connected with the other end of a third capacitor (C3), and a fourth end of the crystal oscillator is grounded.

6. The integrated chip for vehicle Ethernet of claim 3, wherein the mode configuration module comprises a second power supply (VDD 2), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a sixth resistor (R6) and a seventh resistor (R7);

one end of each of the second resistor (R2), the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) is connected to the second power supply (VDD 2), and the other end of each of the second resistor (R2), the third resistor (R3), the fourth resistor (R4) and the fifth resistor (R5) is connected to the first operating mode pin, the second operating mode pin, the third operating mode pin and the fourth operating mode pin of the PHY chip, respectively;

one end of each of the sixth resistor (R6) and the seventh resistor (R7) is grounded, and the other end of each of the sixth resistor (R6) and the seventh resistor (R7) is connected to a fifth operating mode pin and a sixth operating mode pin of the PHY chip, respectively.

7. The integrated chip for vehicle Ethernet according to claim 1, wherein the PHY chip comprises a first filtering pin and a second filtering pin, and the interface filtering circuit comprises an ESD electrostatic tube (D2), a first LRC low-pass filter, a second LRC low-pass filter, a common-mode inductance module, a protection module and a damping absorption module;

the first LRC low-pass filter is connected with a first filtering pin of the PHY chip, and the second LRC low-pass filter is connected with a second filtering pin of the PHY chip;

the ESD electrostatic tube (D2), the common-mode inductance module, the protection module and the damping absorption module are respectively connected between a first filtering pin and a second filtering pin of the PHY chip.

8. The integrated chip for vehicular ethernet according to claim 7, wherein the first LRC low pass filter comprises a first inductor (L1), a tenth resistor (R10), a thirteenth resistor (R13) and an eighth capacitor (C8); a first end of the first inductor (L1) and a first end of the tenth resistor (R10) are both connected to the first filter pin, a second end of the first inductor (L1) and a first end of the thirteenth resistor (R13) are both connected, a second end of the tenth resistor (R10) and a second end of the thirteenth resistor (R13) are both connected to a first end of the eighth capacitor (C8), and a second end of the eighth capacitor (C8) is grounded;

the second LRC low-pass filter comprises a third inductor (L3), an eleventh resistor (R11), a twelfth resistor (R12) and a seventh capacitor (C7); a first end of the third inductor (L3) and a first end of the eleventh resistor (R11) are both connected to the second filter pin, a second end of the third inductor (L3) and a first end of the twelfth resistor (R12) are both connected, a second end of the eleventh resistor (R11) and a second end of the twelfth resistor (R12) are both connected to a first end of the seventh capacitor (C7), and a second end of the seventh capacitor (C7) is grounded;

the common-mode inductor module comprises a common-mode inductor (L2), the common-mode inductor (L2) is connected between the first filtering pin and the second filtering pin, the protection module comprises a fourth capacitor (C4) and a fifth capacitor (C5), and the fourth capacitor (C4) and the fifth capacitor (C5) are both connected with the common-mode inductor (L2);

the damping absorption module comprises a sixth capacitor (C6), an eighth resistor (R8), a ninth resistor (R9) and a fourteenth resistor (R14);

the sixth capacitor (C6) is connected with the fourteenth resistor (R14) in parallel and then is grounded;

the eighth resistor (R8) and the ninth resistor (R9) are connected in parallel and then are respectively connected with the protection module, the sixth capacitor (C6) and the fourteenth resistor (R14).

9. An onboard control system, comprising an integrated chip for an onboard ethernet according to any one of claims 1 to 8.

10. A vehicle comprising an integrated chip for on-board ethernet according to any of claims 1 to 8.