CN115132663A - Manufacturing method of work function layer, metal gate and semiconductor device with metal gate - Google Patents
Manufacturing method of work function layer, metal gate and semiconductor device with metal gate Download PDFInfo
- Publication number
- CN115132663A CN115132663A CN202211037095.5A CN202211037095A CN115132663A CN 115132663 A CN115132663 A CN 115132663A CN 202211037095 A CN202211037095 A CN 202211037095A CN 115132663 A CN115132663 A CN 115132663A
- Authority
- CN
- China
- Prior art keywords
- layer
- work function
- metal
- type gate
- function layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 197
- 239000002184 metal Substances 0.000 title claims abstract description 197
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 72
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000007769 metal material Substances 0.000 claims abstract description 16
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 34
- 229910052782 aluminium Inorganic materials 0.000 claims description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 26
- 238000005121 nitriding Methods 0.000 claims description 25
- 150000002736 metal compounds Chemical class 0.000 claims description 24
- -1 nitrogen-containing metal compound Chemical class 0.000 claims description 24
- 239000003795 chemical substances by application Substances 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000005269 aluminizing Methods 0.000 claims description 9
- 238000001764 infiltration Methods 0.000 claims description 6
- 230000008595 infiltration Effects 0.000 claims description 6
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 238000012545 processing Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 37
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 7
- 239000002994 raw material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910010038 TiAl Inorganic materials 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910021324 titanium aluminide Inorganic materials 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical group [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 3
- 238000000354 decomposition reaction Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910004491 TaAlN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 229910034327 TiC Inorganic materials 0.000 description 2
- 229910008482 TiSiN Inorganic materials 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a manufacturing method of a work function layer, a metal gate and a semiconductor device with the metal gate. The method comprises the following steps: providing a substrate provided with an insulating medium layer, wherein a first type gate groove and a second type gate groove are arranged at intervals in the insulating medium layer, and high-k gate medium layers are arranged at the bottoms of the first type gate groove and the second type gate groove; forming a metal layer, wherein the metal layer at least covers the side walls of the first type gate groove and the second type gate groove and the high-k gate dielectric layer; forming a first work function layer at least covering the side wall of the first type gate groove and the high-k gate dielectric layer by adopting a reaction of a non-metal material and a metal layer; and reacting the first metal with the metal layer with the work function value larger than that of the first metal to form a second work function layer with the work function value smaller than that of the first work function layer and at least covering the side wall of the second type gate groove and the high-k gate dielectric layer. The method increases the adjustable range of the metal work function and improves the applicability of the metal work function processing technology.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a work function layer, a metal gate and a semiconductor device with the metal gate.
Background
With the continuous development of integrated circuit manufacturing technology, the feature size of MOS transistors is smaller and smaller, and the material selection, preparation, and equivalent work function adjustment of the metal gate stack structure of the high-k material gate dielectric/metal gate MOS device become technical difficulties.
In addition, in order to ensure the requirements of devices, a CMOS device generally adopts a double-metal gate structure, but because respective electrodes of an NMOS and a PMOS need different work functions, when the back gate process is adopted to simultaneously achieve the work functions of the NMOS and the PMOS at present, TiN and TiAl are used as the work functions of the PMOS and the NMOS, and the work function TiN of the PMOS needs to be firstly made, then the TiN on the NMOS needs to be removed, and then the work function of the NMOS needs to be made, so that the adjustable range of the work function is limited, in addition, more metal filling layers exist, and the process difficulty is higher. Therefore, how to improve the metal work function process and improve the applicability of the metal work function process to meet the requirements of different devices becomes a major problem to be solved urgently.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a work function layer, a metal gate and a semiconductor device with the metal gate, so as to solve the problem that the adjustable range of the work function of metal in the prior art is small.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for fabricating a work function layer, including the steps of: providing a substrate, wherein an insulating medium layer is arranged on the substrate, a first type gate groove and a second type gate groove are arranged at intervals in the insulating medium layer, and high-k gate medium layers are arranged at the bottoms of the first type gate groove and the second type gate groove; forming a metal layer on the insulating medium layer, wherein the metal layer at least covers the side wall of the first type gate groove, the side wall of the second type gate groove and the high-k gate medium layer; forming a first work function layer by reacting a non-metal material with a part of the metal layer, wherein the first work function layer at least covers the side wall of the first type gate groove and the high-k gate dielectric layer; and forming a second work function layer by reacting the first metal with part of the metal layer, wherein the work function value of the first metal is smaller than that of the metal layer, the work function value of the first work function layer is larger than that of the second work function layer, and the second work function layer at least covers the side wall of the second type gate trench and the high-k gate dielectric layer.
Furthermore, the thickness of the metal layer is 2 nm-10 nm.
Further, the step of forming the first work function layer includes: shielding the second type gate groove to expose the first type gate groove; and infiltrating a non-metal material into the part of the metal layer, which is positioned in the first type gate groove, so as to form a first work function layer.
Further, the step of forming the second work function layer includes: shielding the first type gate groove to expose the second type gate groove; and infiltrating the first metal into the part of the metal layer, which is positioned in the second-type gate trench, so as to form a second work function layer.
Further, the step of forming the first work function layer includes: and nitriding the metal layer to form a nitrogen-containing metal compound layer, wherein the first work function layer comprises the nitrogen-containing metal compound layer, and the nitrogen-containing metal compound layer at least covers the high-k gate dielectric layer and the side wall of the first type gate groove.
Further, the step of forming the nitrogen-containing metal compound layer includes: the work function value of the nitrogen-containing metal compound layer is adjusted by adjusting the nitrogen content during nitriding heat treatment, and the nitrogen content in the nitrogen-containing metal compound layer is in direct proportion to the work function value of the first work function layer.
Furthermore, the nitriding heat treatment time is 1-10 h, and the nitriding heat treatment temperature is 500-750 ℃.
Further, the material forming the second work function layer includes an alumetizing agent, and the step of forming the second work function layer includes: and diffusing active aluminum atoms in the aluminizing agent into the metal layer by adopting an embedding infiltration method to form an aluminum-containing metal compound layer, wherein the second work function layer comprises an aluminum-containing metal compound layer, and the aluminum-containing metal compound layer at least covers the high-k gate dielectric layer and the side wall of the second type gate groove.
Further, the step of forming the aluminum-containing metal compound layer includes: the work function value of the aluminum-containing metal compound layer is adjusted by adjusting the aluminum content in the aluminizing agent, and the aluminum content of the aluminum-containing metal compound layer is inversely proportional to the work function value of the second work function layer.
In order to achieve the above object, according to an aspect of the present invention, there is provided a metal gate including a gate layer and a work function layer, wherein the work function layer is prepared by the above method for preparing the work function layer.
According to another aspect of the present invention, there is provided a semiconductor device including: the semiconductor device comprises a semiconductor substrate, wherein an insulating medium layer is arranged on the surface of one side of the semiconductor substrate, which is provided with a source drain region, and a first type gate groove and a second type gate groove which are arranged at intervals are arranged in the insulating medium layer; the high dielectric constant material layer covers the bottoms of the first type gate groove and the second type gate groove; and the metal gate covers the high-dielectric-constant material layer, and the gate layer in the metal gate is positioned on one side, away from the high-dielectric-constant material layer, of the work function layer in the metal gate.
The technical scheme of the invention is applied to provide a method for manufacturing a work function layer, which comprises the following steps: providing a substrate, wherein an insulating medium layer is arranged on the substrate, a first type gate groove and a second type gate groove are arranged at intervals in the insulating medium layer, and high-k gate medium layers are arranged at the bottoms of the first type gate groove and the second type gate groove; forming a metal layer on the insulating medium layer, wherein the metal layer at least covers the side wall of the first type gate groove, the side wall of the second type gate groove and the high-k gate medium layer; forming a first work function layer by reacting a non-metal material with the metal layer, wherein the first work function layer at least covers the side wall of the first type gate groove and the high-k gate dielectric layer; and forming a second work function layer by adopting the reaction of the first metal and the metal layer, wherein the work function value of the first metal is smaller than that of the metal layer, the work function value of the first work function layer is larger than that of the second work function layer, and the second work function layer at least covers the side wall of the second type gate groove and the high-k gate dielectric layer. The first work function layer and the second work function layer formed in the first type gate groove and the second type gate groove respectively are obtained by converting the metal layer, so that the number of metal filling layers in a metal gate work function process is reduced, and the process difficulty is further reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic cross-sectional view illustrating a metal layer formed in a method for forming a work function layer according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view illustrating a nitriding process performed in the metal layer shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of an aluminizing process performed on the metal layer shown in FIG. 2;
fig. 4 is a schematic cross-sectional view illustrating a work function layer formed by a method for forming a work function layer according to an embodiment of the present invention.
Wherein the figures include the following reference numerals:
10. a substrate; 20. an insulating dielectric layer; 30. a first type gate trench; 40. a second type gate trench; 50. a dielectric layer; 60. a high-k gate dielectric layer; 70. a metal layer; 80. a mask plate; 90. a first work function layer; 100. a second work function layer.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As mentioned in the background art, since the respective electrodes of the NMOS and the PMOS require different work functions, for the N-type semiconductor device, a metal having a small work function needs to be selected, and for the P-type semiconductor device, a metal having a large work function needs to be selected, which can reduce the schottky barrier height of the metal and semiconductor interface, and is beneficial to the injection of carriers. However, for a semiconductor device generally adopting a dual metal gate structure, when a gate-last process is adopted to manufacture the semiconductor device to simultaneously achieve work functions of an NMOS and a PMOS at present, TiN and TiAl need to be selected to be used as the work functions of the PMOS and the NMOS, the work function TiN of the PMOS needs to be manufactured first, then the TiN on the NMOS needs to be removed, and then the work function of the NMOS needs to be manufactured, so that the adjustable range of the work function is limited, in addition, more metal filling layers exist, and the process difficulty is high.
In order to solve the above technical problem, the applicant of the present invention proposes a method for fabricating a work function layer, the method comprising: providing a substrate, wherein an insulating medium layer is arranged on the substrate, a first type gate groove and a second type gate groove are arranged at intervals in the insulating medium layer, and high-k gate medium layers are arranged at the bottoms of the first type gate groove and the second type gate groove; forming a metal layer on the insulated gate dielectric layer, wherein the metal layer at least covers the side wall of the first type gate groove, the side wall of the second type gate groove and the high-k gate dielectric layer; forming a first work function layer by reacting a non-metal material with a part of the metal layer, wherein the first work function layer at least covers the side wall of the first type gate groove and the high-k gate dielectric layer; and forming a second work function layer by reacting the first metal with part of the metal layer, wherein the work function value of the first metal is smaller than that of the metal layer, the work function value of the first work function layer is larger than that of the second work function layer, and the second work function layer at least covers the side wall of the second type gate groove and the high-k gate dielectric layer.
In the method, at least the side wall of the first type gate groove, the side wall of the second type gate groove and the metal layer of the high-k gate dielectric layer are formed on the substrate, then the metal layers at the bottom and the side wall of the first type gate groove and the second type gate groove are converted through the reaction of the non-metal material and partial metal layer and the reaction of the first metal and partial metal layer, and further the first work function layer and the second work function layer are respectively obtained at the bottom and the side wall of the first type gate groove and the second type gate groove, so the number of the metal filling layers in the metal gate work function process is reduced through the manufacturing method, the process difficulty is further reduced, and the function values of the first work function layer and the second work function layer can be respectively regulated and controlled according to the requirements of different devices because the first work function layer and the second work function layer are formed by adopting different processes, thereby enlarging the adjustable range of the metal work function and improving the applicability of the metal work function processing technology.
An exemplary embodiment of a method of fabricating a work function layer provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.
As shown in fig. 1, fig. 1 shows a schematic cross-sectional structure of a metal layer formed in a method for manufacturing a work function layer according to an embodiment of the present invention, first, a substrate 10 is provided, an insulating dielectric layer 20 is disposed on the substrate 10, the insulating dielectric layer 20 has a first-type gate trench 30 and a second-type gate trench 40 therein, bottoms of the first-type gate trench 30 and the second-type gate trench 40 are connected to the substrate 10, and the remaining insulating dielectric layer 20 on the substrate 10 separates the first-type gate trench 30 from the second-type gate trench 40. The high-k gate dielectric layer 60 is respectively positioned at the bottom of the first type gate trench 30 and the bottom of the second type gate trench 40; a metal layer 70 is then formed on one side of the substrate 10 such that the metal layer 70 covers at least the sidewalls of the first-type gate trench 30, the sidewalls of the second-type gate trench 40, and the high-k gate dielectric layer 60.
The substrate 10 may include any suitable semiconductor substrate material, and may specifically be, but not limited to, Si, Ge, GeSi, GaAs, InP, GaInAs, SiC, SOI (silicon on insulator), or any iii/V compound semiconductor. The insulating dielectric layer 20 may comprise a composite of silicon dioxide and silicon nitride. The substrate 10 may include various doping configurations according to design requirements known in the art (e.g., p-type substrate or n-type substrate). In addition, the substrate 10 may optionally include an epitaxial layer, which may be stress altered to enhance performance.
In some optional embodiments, an etching process is used to form the first-type gate trench 30 and the second-type gate trench 40, where the second-type gate trench 40 corresponds to a P-type semiconductor device when the first-type gate trench 30 corresponds to an N-type semiconductor device, and the second-type gate trench 40 corresponds to an N-type semiconductor device when the first-type gate trench 30 corresponds to a P-type semiconductor device.
With the reduction of the characteristic dimension of the device, in order to maintain good device characteristics and ensure the effective control of the gate on the channel carrier distribution, in the process of reducing the characteristic dimension of the semiconductor device, each structural parameter needs to follow a certain rule, namely, a proportional reduction rule, however, when the thickness of the gate oxide layer is reduced to be below 2nm, the quantum direct tunneling effect becomes very obvious, therefore, a high-k material is used for replacing silicon dioxide as the gate dielectric layer material to form a high-k gate dielectric layer 60, and the high-k gate dielectric layer 60 can use a thick dielectric layer thickness under the condition of maintaining the same equivalent oxide layer thickness, so that the gate leakage current caused by the quantum direct tunneling effect is obviously reduced.
After the first-type gate trench 30 and the second-type gate trench 40 are formed, depositing a high-k material in the first-type gate trench 30 and the second-type gate trench 40 to form a high-k gate dielectric layer 60, and allowing the high-k gate dielectric layer 60 to cover the bottoms of the first-type gate trench 30 and the second-type gate trench 40, and then forming a metal layer 70 on the side of the insulating dielectric layer 20 away from the substrate 10, so that the metal layer 70 covers the side of the insulating dielectric layer 20 away from the substrate 10, the side wall of the first-type gate trench 30, the side wall of the second-type gate trench 40, and the high-k gate dielectric layer 60, as shown in fig. 1.
The material of the high-k gate dielectric layer 60 is, for example, a high-k dielectric material, such as HfO 2 、ZrO 2 、Al 2 O 3 、AlN、TiO 2 、La 2 O 3 、Y 2 O 3 、Gd 2 O 3 、Ta 2 O 5 Or a combination thereof, optionally, the high-k gate dielectric layer 60 is formed by, for example, atomic layer deposition.
In some optional embodiments, a dielectric layer 50 is further disposed in the first-type gate trench 30 and the second-type gate trench 40, the dielectric layer 50 is disposed between the substrate 10 and the high-k gate dielectric layer 60, and the dielectric layer 50 is added to increase the stress of the first-type gate trench 30 and the second-type gate trench 40 or increase the adhesion between the first-type gate trench 30 and the second-type gate trench 40 and the substrate 10, and has a function of preventing current leakage, optionally, the material of the dielectric layer 50 is, for example, silicon oxide, and the forming method of the dielectric layer 50 is, for example, a thermal oxidation method or a chemical vapor deposition method.
In addition, the metal layer 70 is used as a precursor for forming a work function layer, and different materials are infiltrated into the metal layer 70, so that the internal structure of the metal layer 70 is changed, and the work function value is further changed, so that the work function value meets the requirements of different semiconductor devices.
In some optional embodiments, the metal material of the metal layer 70 is titanium, because the work function value of titanium is relatively large, it can form good ohmic contact with many materials, the contact resistance is relatively small, and because the adhesion of metal titanium is relatively strong, its compound has good conductivity and good heat resistance, and it is mainly used as contact metal.
It should be noted that the metal material of the metal layer 70 may be any other metal that can form a work function layer, and those skilled in the art can reasonably select the metal material according to actual requirements, and the invention is not limited thereto.
In some alternative embodiments, the thickness of the metal layer 70 is 2nm to 10nm, and the metal layer 70 in the first-type gate trench 30 and the second-type gate trench 40 may have the same or different thicknesses, respectively, so as to transform into a first work function layer and a second work function layer having the same or different thicknesses. Preferably, the metal layer 70 in the first-type gate trench 30 and the second-type gate trench 40 has the same thickness, the thickness of the metal layer 70 is 3nm to 8nm, and the thickness of the work function layer can be further adjusted by adjusting the thickness of the metal layer 70, so as to adjust the threshold voltage of the semiconductor device having the work function layer.
In order to simplify the metal work function process, in some optional embodiments, a non-metal material is directly adopted to react with a part of the metal layer 70 to form a first work function layer 90, as shown in fig. 2, that is, the first work function layer 90 is obtained by converting a part of the metal layer 70, and the first work function layer 90 at least covers the sidewall of the first-type gate trench 30 and the high-k gate dielectric layer 60, as shown in fig. 3. Therefore, the first work function layer 90 is not formed on the side wall of the first-type gate trench 30 and the region outside the high-k gate dielectric layer 60, reaction raw materials are saved, and the step of removing the redundant first work function layer 90 is omitted due to the fact that the redundant first work function layer 90 is not formed, and the metal work function manufacturing process is simplified.
The non-metallic material may include a material that can chemically react with the metal layer 70 and can reduce a work function value of the metal layer 70.
In some alternative embodiments, when the first-type gate trench 30 corresponds to an N-type semiconductor device, the first work function layer 90 includes an N-type work function metal layer, and the material thereof is, for example, TiAl, TiAlN, TaC, TaAlN or TiC. When the first-type gate trench 30 corresponds to a P-type semiconductor device, the first work function layer 90 includes a P-type work function metal layer, such as TiN, TiSiN, or TaN.
In some optional embodiments, the step of forming the first work function layer 90 further includes: shielding the second-type gate trench 40 to expose the first-type gate trench 30; a non-metallic material is infiltrated in the portion of the metal layer 70 located in the first-type gate trench 30 to form a first work function layer 90, as shown in fig. 2.
In the above embodiment, the second-type gate trench 40 is blocked, so that only the first-type gate trench 30 is exposed on the first side of the substrate 10, thereby ensuring that the raw material for forming the first work function layer 90 is not diffused into the second-type gate trench 40 during the process of forming the first work function layer 90, resulting in unnecessary loss of raw material, and simultaneously avoiding forming the first work function layer 90 at a place where the first work function layer 90 is not required to be formed, thereby reducing the step of removing the unnecessary first work function layer 90 and simplifying the steps of metal work function.
In some alternative embodiments, as shown in fig. 2, a mask 80 or a photo mask is used to shield the second-type gate trenches 40, thereby avoiding the formation of the first work function layer 90 where the first work function layer 90 is not required to be formed.
In some alternative embodiments, the work function value of the metal layer 70 is known, and for the semiconductor device in this embodiment, the work function value of the metal layer 70 is smaller than the work function value required by the semiconductor device, so that the metal layer 70 is non-metalized by infiltrating a non-metal material into the portion of the metal layer 70 located in the first-type gate trench 30, and the mobility of electrons in the metal layer 70 is bound to some extent, thereby increasing the work function value of the metal layer 70, so as to form the first work function layer 90 having a work function value larger than that of the metal layer 70.
In some alternative embodiments, the step of forming the first work function layer 90 by infiltrating a non-metallic material into a portion of the metal layer 70 located in the first-type gate trench 30 includes: the metal layer 70 is nitrided heat treated to form a nitrogen-containing metal compound layer, and the first work function layer 90 includes a nitrogen-containing metal compound layer covering at least the high-k gate dielectric layer 60 and the sidewalls of the first-type gate trench 30. Optionally, the metal layer 70 is a metal titanium layer, and after the nitridation process is performed, the formed nitrogen-containing metal compound layer is a titanium nitride layer, that is, the first work function layer 90 is a titanium nitride layer, as shown in fig. 2.
In the above embodiment, the material forming the first work function layer 90 includes nitrogen gas, ammonia gas and the metal layer 70, and since the work function value of the metal layer 70 can be improved by nitriding, when nitriding heat treatment is performed on the metal layer 70, nitrogen gas is introduced into the metal layer 70, and flowing ammonia gas is introduced and heated, and after a long period of heat preservation, the ammonia gas is thermally decomposed to generate active nitrogen molecules, which are continuously adsorbed on the surface of the metal layer 70 and diffused into the metal layer 70, thereby changing the chemical composition and structure of the metal layer 70, forming a nitrogen-containing metal compound layer, and improving the work function value of the original metal layer 70.
In some alternative embodiments, the step of forming the nitrogen-containing metal compound layer includes: the work function value of the nitrogen-containing metal compound layer is adjusted by adjusting the nitrogen content during the nitriding heat treatment, and the nitrogen content in the nitrogen-containing metal compound layer is proportional to the work function value of the first work function layer 90.
In the above embodiment, the higher the nitrogen content in the nitrogen-containing metal compound layer, the larger the work function value of the first work function layer 90, and the lower the nitrogen content in the nitrogen-containing metal compound layer, the smaller the work function value of the first work function layer 90.
In some alternative embodiments, the nitriding heat treatment is carried out for a time of 1h to 10h and at a temperature of 500 ℃ to 750 ℃. In this embodiment, the active nitrogen molecules permeating into the metal layer 70 during the nitriding process are controlled by controlling the time of introducing nitrogen gas during the nitriding process, wherein the longer the duration of the nitriding process is, the more active nitrogen molecules permeate into the metal layer 70, the higher the nitrogen content in the metal layer 70 is (i.e. the nitrogen content in the metal layer 70 may be 10%, 20%, 30%, 40%, etc.), and the larger the first work function value is; in addition, the temperature of the heat treatment in the nitriding process is controlled, so as to control the speed of active nitrogen molecules permeating into the metal layer 70, wherein the higher the temperature is, the faster the permeation speed is.
In some embodiments, the first work function layer 90 is formed by nitriding, i.e. the nitriding temperature and the ammonia decomposition rate are controlled to be constant during the whole nitriding process, the temperature is controlled to be about 500 ℃ and the time is 10 hours, so as to form the first work function layer 90, in this embodiment, the temperature is controlled to be low, so that the diffusion layer of the first work function layer 90 is formed to be shallow.
In other embodiments, the first work function layer 90 is formed by a multi-step nitriding method, and the deep-penetrated first work function layer 90 can be formed by performing nitriding and diffusion at different temperatures, different ammonia decomposition rates, and different times, respectively, at a temperature higher than that in a general nitriding method during the entire nitriding process, but the first work function layer 90 in this embodiment is distorted more greatly due to an excessively high temperature, and therefore, it is preferable that the temperature of the nitriding process is controlled to 500 ℃ to form the first work function layer 90 having excellent performance.
Similarly, as shown in fig. 3 and 4, in order to save reaction raw materials and simplify the metal work function process, in some alternative embodiments, a first metal is used to react with a portion of the metal layer 70 to form a second work function layer 100, the work function value of the first metal is smaller than that of the metal layer 70, the work function value of the first work function layer 90 is larger than that of the second work function layer 100, and the second work function layer 100 at least covers the sidewall of the second-type gate trench 40 and the high-k gate dielectric layer 60. In this embodiment, the second work function layer 100 is transformed from the metal layer 70 by the reaction of the first metal with a portion of the metal layer 70, and the work function value of the second work function layer 100 is smaller than that of the metal layer 70, and since the work function value of the first work function layer 90 is larger than that of the metal layer 70, the work function value of the first work function layer 90 is larger than that of the second work function layer 100.
In some alternative embodiments, when the second-type gate trench 40 corresponds to an N-type semiconductor device, the second work function layer 100 includes an N-type work function metal layer, and the material thereof is, for example, TiAl, TiAlN, TaC, TaAlN or TiC. When the second-type gate trench 40 corresponds to a P-type semiconductor device, the second work function layer 100 includes a P-type work function metal layer, which is made of TiN, TiSiN, or TaN, for example.
In some alternative embodiments, the step of forming the second work function layer 100 includes: masking the first-type gate trench 30 to expose the second-type gate trench 40, as shown in fig. 3; the first metal is infiltrated in the portion of the metal layer 70 located in the second-type gate trench 40 to form a second work function layer 100, as shown in fig. 4.
In the above embodiment, since the first-type gate trench 30 is shielded, only the second-type gate trench 40 is exposed on the first side of the substrate 10, thereby ensuring that the raw material for forming the second work function layer 100 is not diffused into the first-type gate trench 30 during the process of forming the second work function layer 100, causing unnecessary loss of the raw material, and simultaneously avoiding forming the second work function layer 100 at a place where the second work function layer 100 is not required to be formed, thereby reducing the step of removing the unnecessary second work function layer 100 and simplifying the steps of the metal work function process.
In some alternative embodiments, the first-type gate trench 30 is masked with a mask plate 80 or a light shield, thereby preventing the second work function layer 100 from being formed where the second work function layer 100 is not required to be formed. In some optional embodiments, the work function value of the metal layer 70 is known, and for the semiconductor device in this embodiment, the work function value of the metal layer 70 is larger than the work function value required by the semiconductor device, so that by infiltrating the first metal into the portion of the metal layer 70 located in the second-type gate trench, since the work function value of the first metal is smaller than the work function value of the metal layer 70, the work function value of the metal layer 70 is reduced, thereby forming the second work function layer 100 with a work function smaller than that of the metal layer 70.
In some alternative embodiments, as shown in fig. 3, the first metal is aluminum metal. Alternatively, the material forming the second work function layer 100 includes an alumetizing agent, and the step of forming the second work function layer 100 includes: diffusing active aluminum atoms in the alumetizing agent into the metal layer 70 using pack cementation to form an aluminum-containing metal compound layer, the second work function layer 100 comprising an aluminum-containing metal compound layer, the aluminum-containing metal compound layer covering at least the high-k gate dielectric layer 60 and the sidewalls of the second-type gate trench 40, and after the aluminum-containing metal compound layer is formed, the nitrogen-containing metal compound layer outside the first-type gate trench 30 is removed by dry etching or wet etching, to leave the nitrogen-containing metal compound layer in the first-type gate trench 30, a first work function layer 90 corresponding to the first-type gate trench 30 is obtained, and removing the aluminum-containing metal compound layer outside the second-type gate trench 40 to leave the aluminum-containing metal compound layer in the second-type gate trench 40, resulting in a second work function layer 100 corresponding to the second-type gate trench 40, as shown in fig. 4. Optionally, the metal layer 70 is a metal titanium layer, and after the embedding infiltration method is adopted, the formed aluminum-containing metal compound layer is a titanium aluminide layer, that is, the second work function layer 100 is a titanium aluminide layer.
In the above embodiment, the embedding infiltration method is adopted to heat the aluminizing agent and keep the temperature for a period of time, so that the aluminum atoms in the aluminizing agent are activated to reach the condition of entering the metal layer 70, and then the activated aluminum atoms are diffused into the metal layer 70, thereby changing the chemical composition and the tissue of the metal layer 70, forming the aluminum-containing metal compound layer, and reducing the work function value of the original metal layer 70. Alternatively, the metal layer 70 is a metal titanium layer, and since the work function value of the metal aluminum is smaller than that of the metal titanium, the work function value of the metal titanium layer can be reduced by forming the second work function layer 100 as a titanium aluminide metal compound layer after heating and maintaining the alumetizing agent for a certain period of time by the embedding infiltration method.
In some alternative embodiments, the step of forming the aluminum-containing metal compound layer includes: the work function value of the aluminum-containing metal compound layer is adjusted by adjusting the aluminum content in the alumetizing agent (i.e., the aluminum content in the metal layer 70 may be 10%, 20%, 30%, 40%, etc.), which is inversely proportional to the work function value of the second work function layer 100.
In the above embodiment, the higher the aluminum content in the aluminum-containing metal compound layer, the smaller the work function value of the second work function layer 100, and the lower the aluminum content in the aluminum-containing metal compound layer, the larger the work function value of the second work function layer 100.
In some embodiments, the aluminizing agent includes Al, NH 4 Cl and Al 2 O 3 In the powder mixture of (1), wherein 4 Cl is used as a catalyst, and halogen (Cl) generated by decomposition reacts with Al in the infiltration agent to form AlCl and AlCl at the aluminizing temperature 2 The low-valent chloride diffuses through the aluminum-poor region to the metallic titanium layer for surface reaction, active Al atoms are released, and AlCl is formed 3 High valence AlCl 3 Formation of active Al 3+ ,Al 3+ Is adsorbed on the surface of the crystal lattice of the metallic titanium layer and then enters the titanium crystal lattice through a vacancy diffusion mechanism to form a titanium aluminide metallic compound layer, namely a second work function layer 100. Alternatively, Al or NH as described above 4 Cl and Al 2 O 3 The powder mixture of (1) is mixed in proportions of 10%, 5% and 85%, respectively, and is subjected to pack cementation under a closed condition in which the mass of the metal layer 70 is not lost, thereby forming an excellent work function layer.
In some optional embodiments, the first work function layer 90 and the second work function layer 100 outside the sidewall and the bottom of the first-type gate trench 30 and the sidewall and the bottom of the second-type gate trench 40 are removed by etching, as shown in fig. 4, fig. 4 shows a schematic cross-sectional structure of the work function layer formed by the method for manufacturing the work function layer according to the embodiment of the present invention, each metal gate trench has only one work function layer, that is, the first-type gate trench 30 has the first work function layer 90, and the second-type gate trench 40 has the second work function layer 100, so that the problem of more metal filling layers in a metal work function process is solved, and the first work function layer 90 and the second work function layer 100 are formed by independent processes, so that the adjustability of the metal gate work function process is improved, and the adjustable range of the work function is expanded.
According to another aspect of the present application, a metal gate is provided, which includes a gate layer and a work function layer, the gate layer and the work function layer are stacked, and the work function layer is formed by the above work function forming method.
According to another aspect of the present application, there is also provided a semiconductor device including: the semiconductor device comprises a semiconductor substrate, wherein an insulating medium layer is arranged on the surface of one side of the semiconductor substrate, which is provided with a source drain region, and a first type gate groove and a second type gate groove which are arranged at intervals are arranged in the insulating medium layer; the high dielectric constant material layer covers the bottoms of the first type gate groove and the second type gate groove; and the metal gate covers the high-dielectric-constant material layer, and the gate layer in the metal gate is positioned on one side, away from the high-dielectric-constant material layer, of the work function layer in the metal gate.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
1. in the manufacturing method of the work function layer, the first work function layer and the second work function layer which are respectively formed in the first type gate groove and the second type gate groove are obtained by converting the metal layer, so that the number of metal filling layers in a metal gate work function process is reduced, and the process difficulty is further reduced;
2. the first work function layer and the second work function layer are formed by adopting different processes, so that the work function values of the first work function layer and the second work function layer can be respectively regulated and controlled according to the requirements of different devices, the adjustable range of the metal work function is enlarged, and the applicability of the metal work function processing process is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (11)
1. A method for manufacturing a work function layer is characterized by comprising the following steps:
providing a substrate, wherein an insulating medium layer is arranged on the substrate, a first type gate groove and a second type gate groove are arranged at intervals in the insulating medium layer, and high-k gate medium layers are arranged at the bottoms of the first type gate groove and the second type gate groove;
forming a metal layer on the insulating dielectric layer, wherein the metal layer at least covers the side wall of the first type gate trench, the side wall of the second type gate trench and the high-k gate dielectric layer;
forming a first work function layer by reacting a non-metal material with a part of the metal layer, wherein the first work function layer at least covers the side wall of the first type gate groove and the high-k gate dielectric layer;
and forming a second work function layer by reacting a first metal with part of the metal layer, wherein the work function value of the first metal is smaller than that of the metal layer, the work function value of the first work function layer is larger than that of the second work function layer, and the second work function layer at least covers the side wall of the second type gate groove and the high-k gate dielectric layer.
2. The method of claim 1, wherein the metal layer has a thickness of 2nm to 10 nm.
3. The method of claim 1, wherein the step of forming the first work function layer comprises:
shielding the second type gate groove to expose the first type gate groove;
and infiltrating the non-metal material into the part of the metal layer, which is positioned in the first type gate groove, so as to form the first work function layer.
4. The method of claim 1, wherein the step of forming the second work function layer comprises:
shielding the first type gate groove to expose the second type gate groove;
and infiltrating the first metal into the part of the metal layer, which is positioned in the second-type gate groove, so as to form the second work function layer.
5. The method of any of claims 1 to 4, wherein the step of forming the first work function layer comprises:
and nitriding the metal layer to form a nitrogen-containing metal compound layer, wherein the first work function layer comprises the nitrogen-containing metal compound layer, and the nitrogen-containing metal compound layer at least covers the high-k gate dielectric layer and the side wall of the first type gate trench.
6. The method according to claim 5, wherein the step of forming the nitrogen-containing metal compound layer comprises:
and adjusting the work function value of the nitrogen-containing metal compound layer by adjusting the nitrogen content during the nitriding heat treatment, wherein the nitrogen content in the nitrogen-containing metal compound layer is in direct proportion to the work function value of the first work function layer.
7. The method for manufacturing the work function layer according to claim 5, wherein the nitriding heat treatment time is 1-10 hours, and the nitriding heat treatment temperature is 500-750 ℃.
8. The method of claim 1, wherein the material forming the second work function layer comprises an alumetizing agent, and the step of forming the second work function layer comprises:
and diffusing active aluminum atoms in the aluminizing agent into the metal layer by adopting an embedding infiltration method to form an aluminum-containing metal compound layer, wherein the second work function layer comprises the aluminum-containing metal compound layer, and the aluminum-containing metal compound layer at least covers the high-k gate dielectric layer and the side wall of the second-type gate trench.
9. The method according to claim 8, wherein the step of forming the aluminum-containing metal compound layer comprises:
and adjusting the work function value of the aluminum-containing metal compound layer by adjusting the aluminum content in the aluminizing agent, wherein the aluminum content of the aluminum-containing metal compound layer is inversely proportional to the work function value of the second work function layer.
10. A metal gate comprising a gate layer and a work function layer, wherein the work function layer is prepared by the method of any one of claims 1 to 9.
11. A semiconductor device, characterized in that the semiconductor device comprises:
the semiconductor device comprises a semiconductor substrate, wherein an insulating medium layer is arranged on the surface of one side of the semiconductor substrate, which is provided with a source drain region, and a first type gate groove and a second type gate groove which are arranged at intervals are arranged in the insulating medium layer;
the high-dielectric-constant material layer covers the bottoms of the first type gate groove and the second type gate groove;
the metal gate of claim 10, overlying the layer of high-k material, a gate layer in the metal gate being on a side of the work function layer in the metal gate away from the layer of high-k material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211037095.5A CN115132663A (en) | 2022-08-29 | 2022-08-29 | Manufacturing method of work function layer, metal gate and semiconductor device with metal gate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202211037095.5A CN115132663A (en) | 2022-08-29 | 2022-08-29 | Manufacturing method of work function layer, metal gate and semiconductor device with metal gate |
Publications (1)
Publication Number | Publication Date |
---|---|
CN115132663A true CN115132663A (en) | 2022-09-30 |
Family
ID=83387685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202211037095.5A Pending CN115132663A (en) | 2022-08-29 | 2022-08-29 | Manufacturing method of work function layer, metal gate and semiconductor device with metal gate |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN115132663A (en) |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060024892A1 (en) * | 2004-07-28 | 2006-02-02 | Brask Justin K | Compensating the workfunction of a metal gate transistor for abstraction by the gate dielectric layer |
US20060051924A1 (en) * | 2004-09-08 | 2006-03-09 | Doczy Mark L | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US20070054446A1 (en) * | 2005-09-07 | 2007-03-08 | Texas Instruments Incorporated | Work function control of metals |
US20090137090A1 (en) * | 2007-11-23 | 2009-05-28 | Inotera Memories, Inc. | Method for fabricating semiconductor device |
US20090134466A1 (en) * | 2007-10-24 | 2009-05-28 | Interuniversitair Mcroelektronica Centrum Vzw(Imec) | Dual work function semiconductor device and method for manufacturing the same |
US20120122309A1 (en) * | 2010-11-15 | 2012-05-17 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device using a work function control film |
US20120329261A1 (en) * | 2011-06-21 | 2012-12-27 | Wang shao-wei | Manufacturing method for metal gate |
US20130240996A1 (en) * | 2012-03-14 | 2013-09-19 | Huaxiang Yin | Semiconductor Device and Method of Manufacturing the Same |
CN104425522A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
US20160203988A1 (en) * | 2015-01-09 | 2016-07-14 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and fabrication method thereof |
US9698241B1 (en) * | 2016-03-16 | 2017-07-04 | GlobalFoundries, Inc. | Integrated circuits with replacement metal gates and methods for fabricating the same |
CN114695538A (en) * | 2022-02-21 | 2022-07-01 | 上海华力集成电路制造有限公司 | MOS transistor with HKMG and manufacturing method thereof |
-
2022
- 2022-08-29 CN CN202211037095.5A patent/CN115132663A/en active Pending
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060024892A1 (en) * | 2004-07-28 | 2006-02-02 | Brask Justin K | Compensating the workfunction of a metal gate transistor for abstraction by the gate dielectric layer |
US20060051924A1 (en) * | 2004-09-08 | 2006-03-09 | Doczy Mark L | Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode |
US20070054446A1 (en) * | 2005-09-07 | 2007-03-08 | Texas Instruments Incorporated | Work function control of metals |
US20090134466A1 (en) * | 2007-10-24 | 2009-05-28 | Interuniversitair Mcroelektronica Centrum Vzw(Imec) | Dual work function semiconductor device and method for manufacturing the same |
US20090137090A1 (en) * | 2007-11-23 | 2009-05-28 | Inotera Memories, Inc. | Method for fabricating semiconductor device |
US20120122309A1 (en) * | 2010-11-15 | 2012-05-17 | Samsung Electronics Co., Ltd. | Method of fabricating semiconductor device using a work function control film |
US20120329261A1 (en) * | 2011-06-21 | 2012-12-27 | Wang shao-wei | Manufacturing method for metal gate |
US20130240996A1 (en) * | 2012-03-14 | 2013-09-19 | Huaxiang Yin | Semiconductor Device and Method of Manufacturing the Same |
CN104425522A (en) * | 2013-09-10 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and preparation method thereof |
US20160203988A1 (en) * | 2015-01-09 | 2016-07-14 | Semiconductor Manufacturing International (Shanghai) Corporation | Semiconductor device and fabrication method thereof |
US9698241B1 (en) * | 2016-03-16 | 2017-07-04 | GlobalFoundries, Inc. | Integrated circuits with replacement metal gates and methods for fabricating the same |
CN114695538A (en) * | 2022-02-21 | 2022-07-01 | 上海华力集成电路制造有限公司 | MOS transistor with HKMG and manufacturing method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11804409B2 (en) | Semiconductor device with profiled work-function metal gate electrode and method of making | |
US20210257262A1 (en) | Selective Dual Silicide Formation Using A Maskless Fabrication Process Flow | |
JP4623006B2 (en) | Semiconductor device and manufacturing method thereof | |
US7772678B2 (en) | Metallic compound thin film that contains high-k dielectric metal, nitrogen, and oxygen | |
US7385265B2 (en) | High dielectric constant MOSFET device | |
CN100448008C (en) | Semiconductor device and method of manufacturing semiconductor device | |
TWI321832B (en) | Semiconductor device, and method for manufacturing the same | |
US7763945B2 (en) | Strained spacer design for protecting high-K gate dielectric | |
US20100052079A1 (en) | Semiconductor devices and fabrication process thereof | |
US7205186B2 (en) | System and method for suppressing oxide formation | |
JP5157450B2 (en) | Semiconductor device and manufacturing method thereof | |
US20090004881A1 (en) | Hybrid high-k gate dielectric film | |
JP2011524080A (en) | Selective formation of dielectric etch stop layer | |
WO2013159414A1 (en) | Dual metal gate cmos device and fabrication method thereof | |
US7723176B2 (en) | Method for manufacturing semiconductor device | |
WO2011057494A1 (en) | Method of manufacturing semiconductor device and a semiconductor device | |
US20060226470A1 (en) | Semiconductor device having metal gate patterns and related method of manufacture | |
US20090294877A1 (en) | Semiconductor device and manufacturing method thereof | |
KR100718835B1 (en) | semiconductor MOS transistor and method of manufacturing the same | |
US11837508B2 (en) | Method of forming high-k dielectric material | |
WO2007116470A1 (en) | Semiconductor device and process for producing the same | |
US7911004B2 (en) | Semiconductor device and manufacturing method of the same | |
US20090283836A1 (en) | Cmos structure including protective spacers and method of forming thereof | |
JP2012186259A (en) | Semiconductor device manufacturing method and semiconductor device | |
CN115132663A (en) | Manufacturing method of work function layer, metal gate and semiconductor device with metal gate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220930 |