CN115116871A - Bump packaging structure and preparation method thereof - Google Patents
Bump packaging structure and preparation method thereof Download PDFInfo
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- CN115116871A CN115116871A CN202210853382.7A CN202210853382A CN115116871A CN 115116871 A CN115116871 A CN 115116871A CN 202210853382 A CN202210853382 A CN 202210853382A CN 115116871 A CN115116871 A CN 115116871A
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- 238000004806 packaging method and process Methods 0.000 title abstract description 15
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims description 299
- 239000000758 substrate Substances 0.000 claims description 99
- 239000012790 adhesive layer Substances 0.000 claims description 74
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 42
- 230000004888 barrier function Effects 0.000 claims description 41
- 238000009736 wetting Methods 0.000 claims description 38
- 229910021389 graphene Inorganic materials 0.000 claims description 34
- 239000011241 protective layer Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 23
- 230000001681 protective effect Effects 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 4
- 230000017525 heat dissipation Effects 0.000 abstract description 9
- 230000007797 corrosion Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 26
- 229910052802 copper Inorganic materials 0.000 description 26
- 239000010949 copper Substances 0.000 description 26
- 239000000463 material Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000005012 migration Effects 0.000 description 6
- 238000013508 migration Methods 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052720 vanadium Inorganic materials 0.000 description 3
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13005—Structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13193—Material with a principal constituent of the material being a solid not provided for in groups H01L2224/131 - H01L2224/13191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
The embodiment of the invention provides a bump packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. Compared with the prior art, the bump packaging structure provided by the invention can avoid undercut openings formed by excessive corrosion, is more stable in structure, better in bottom structure binding force, better in heat dissipation and electric conductivity, and effectively relieves failure hidden dangers caused by electromigration and thermomigration.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a bump packaging structure and a preparation method of the bump packaging structure.
Background
With the rapid development of the semiconductor industry, the flip chip package structure is widely applied to the semiconductor industry, and the flip chip package utilizes the bumps to electrically connect the chip and the substrate. The bump comprises a copper column, a metal layer (UBM), a protective layer (Polyimide), and a tin Cap (Sn Cap), wherein after the UBM is manufactured, the redundant metal layer needs to be etched and removed. The bottom of the copper column lug is completely connected with the chip electrode in the prior art, and a flattening structure is usually adopted, so that stress on the copper column lug directly acts on the chip electrode, the chip electrode cracks, and the contact area among metal layers is small, and the binding force is poor. And under the condition that the copper column lug is subjected to current, due to joule heating effect, metal atoms at the connecting part at the bottom of the copper column bear the influence of an electric field and a thermal field at the same time, and the service life of the interconnection interface is remarkably shortened due to electromigration and thermomigration caused by abnormal activity, so that potential failure hidden trouble is caused.
Disclosure of Invention
The invention aims to provide a bump packaging structure and a manufacturing method of the bump packaging structure, which can avoid undercut openings formed by excessive corrosion, have more stable structure, better bonding force of a bottom structure, better heat dissipation and electrical conductivity and effectively relieve failure hidden troubles caused by electromigration and thermal migration.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a bump package structure, including:
the front surface of the chip is provided with a welding pad;
the protective layer is arranged on the front surface of the chip, and a protective opening corresponding to the welding pad is arranged on the protective layer;
a substrate bonding layer disposed within the protective opening;
a conductive composite layer disposed on the substrate bonding layer;
the electric convex column is arranged on the conductive combination layer;
the cap layer is arranged on the electric convex column;
the substrate bonding layer comprises a plurality of graphene layers, the top edge of the substrate bonding layer extends outwards to the protective layer and covers the edge of the protective opening, an arc-shaped groove is formed in the surface of one side, away from the chip, of the substrate bonding layer, and at least part of the conductive combination layer is accommodated in the arc-shaped groove.
In an alternative embodiment, the conductive composite layer includes a barrier layer overlying the substrate bonding layer and a wetting layer overlying the barrier layer.
In an alternative embodiment, the thickness H1 of the portion of the substrate adhesive layer extending to the protective layer is 4-8 μm; the thickness H2 of the barrier layer is 4-6 μm; the thickness H3 of the wetting layer was 2-4 μm.
In an alternative embodiment, the portions of the substrate adhesive layer extending to the protective layer, the barrier layer, and the wetting layer are the same thickness.
In an alternative embodiment, the width L1 of the portion of the substrate adhesive layer extending to the protective layer is 4-8 μm, and the projection of the substrate adhesive layer on the front side of the chip, the projection of the barrier layer on the front side of the chip, and the projection of the wetting layer on the front side of the chip overlap.
In an alternative embodiment, a side surface of the substrate adhesive layer away from the chip is at least partially concave, and the arc-shaped groove is formed, so that the barrier layer and the wetting layer are both arched toward the chip, and a side surface of the electrical pillar close to the chip is at least partially convex.
In an alternative embodiment, the arc-shaped groove extends to the edge of the substrate bonding layer, so that the surface of one side, away from the chip, of the substrate bonding layer is in an inward-concave arc surface.
In an optional implementation manner, a stop layer is further disposed on a side of the electrical pillar away from the chip, and the stop layer is disposed between the cap layer and the electrical pillar and is used for blocking diffusion atoms between the cap layer and the electrical pillar.
In an optional implementation manner, a conductive adhesive layer is further disposed on one side of the electric convex pillar away from the chip, the conductive adhesive layer is disposed between the stop layer and the electric convex pillar, and the conductive adhesive layer is a graphene layer.
In an optional embodiment, at least a portion of a side surface of the electrical pillar away from the chip is an inward-concave arc surface, so that the stopper layer and the conductive adhesive layer are both arched toward a direction close to the chip, and a side surface of the cap layer close to the chip is an outward-convex arc surface.
In a second aspect, the present invention provides a method for manufacturing a bump package structure, for manufacturing the bump package structure according to any one of the foregoing embodiments, including:
providing a chip with a welding pad on the front surface;
forming a protective layer on the front surface of the chip;
slotting the position, corresponding to the welding pad, on the protective layer to form a protective opening;
forming a substrate bonding layer in the protective opening;
forming a conductive combination layer on the substrate bonding layer;
forming an electrical convex column on the conductive combination layer;
forming a cap layer on the electric convex column;
the substrate bonding layer comprises a plurality of graphene layers, the top edge of the substrate bonding layer extends outwards to the protective layer and covers the edge of the protective opening, an arc-shaped groove is formed in the surface of one side, away from the chip, of the substrate bonding layer, and at least part of the conductive combination layer is accommodated in the arc-shaped groove.
The beneficial effects of the embodiment of the invention include, for example:
the embodiment of the invention provides a bump packaging structure, wherein a protection layer is arranged on the front surface of a chip, a protection opening is formed in the protection layer, a substrate bonding layer is arranged in the protection opening, a conductive combination layer is arranged on the substrate bonding layer, and an electric convex column and a cap layer are sequentially arranged on the conductive combination layer, wherein the substrate bonding layer comprises a plurality of graphene layers, the top edge of the substrate bonding layer extends outwards to the protection layer, and the stability and the hydrophobicity of a bottom structure can be enhanced by adopting the plurality of graphene layers. And the top edge of the substrate bonding layer extends outwards to the protective layer and covers the edge of the protective opening, so that when the micro-etching process is carried out, no matter a chemical etching mode or a plasma etching mode is adopted, the substrate bonding layer can avoid the undercut problem caused when the UBM layer is removed by the traditional micro-etching process. Moreover, the coefficient of thermal expansion CTE of the graphene material is only 1/10-1/20 of copper and aluminum, so that the UBM layer at the bottom of the conductive column can be better prevented from deforming, and the bonding pad at the bottom and the metal structure at the bottom of the conductive column can be protected. The electric conductivity of the graphene material is far higher than that of metal, the heat conductivity is superior, the heat conductivity and the heat conductivity of the multi-layer graphene structure formed along with the increase of the volume of graphene are further improved, the electric conductivity and the heat dissipation performance of the multi-layer graphene structure are greatly improved, the problem that the service life of a copper column lug is remarkably shortened due to abnormal activity of electromigration and heat migration, and potential failure hidden danger is caused is avoided. Meanwhile, the problem that a copper column in the traditional technology causes larger stress in a packaging body to cause damage of a brittle material layer is solved by utilizing the stability of graphene, for example, the chip bonding pad at the bottom of the copper column is broken, a UBM metal layer is layered or the fatigue life of a welding spot is reduced, so that the stability of the structure is ensured. In addition, the surface of basement adhesive linkage is provided with the arc recess, and the partial holding of electrically conductive combined layer can promote the area of contact between electrically conductive combined layer and the basement adhesive linkage in the arc recess to promote the cohesion of the two, further promote the stability of structure, avoid the electrical property projection post to drop. Compared with the prior art, the bump packaging structure provided by the invention can avoid undercut openings formed by excessive corrosion, is more stable in structure, better in bottom structure bonding force, better in heat dissipation and conductivity, and effectively relieves failure hidden troubles caused by electromigration and heat migration.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic view of a bump package structure according to a first embodiment of the invention;
FIG. 2 is an enlarged partial view of II in FIG. 1;
fig. 3 to fig. 8 are process flow diagrams of a method for manufacturing a bump package structure according to a first embodiment of the invention;
fig. 9 is a schematic view of a bump package structure according to a second embodiment of the invention;
fig. 10 is a schematic view of a bump package structure according to a third embodiment of the invention;
FIG. 11 is an enlarged view of a portion of XI in FIG. 10.
Icon: 100-bump package structure; 110-chip; 120-a protective layer; 121-a protection opening; 130-a substrate bonding layer; 140-a conductive combination layer; 141-a barrier layer; 143-a wetting layer; 150-electric convex columns; 160-cap layer; 170-a stopper layer; 180-conductive adhesive layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are only used to distinguish one description from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background, the following objective shortcomings exist in the prior art:
1. the protective layer adopts Polyimide material usually, because Polyimide material absorbs water extremely easily, leads to the etching solution to appear easily to remain in metal column bottom UBM lateral wall, and then leads to there being excessive corruption undercut opening copper post lug bottom, and the lug chip is when advancing the reliability test, and copper post lug has the problem that drops.
2. The bottom of a copper column lug in the existing unit is directly and completely connected with a chip electrode, so that the buffering capacity is poor, the stress on the copper column lug directly acts on the chip electrode, and the problem of chip electrode cracking exists.
In order to solve the above problems, the present invention provides a novel bump package structure and a method for manufacturing the bump package structure, and it should be noted that, in a non-conflicting manner, features in the embodiments of the present invention may be combined with each other.
First embodiment
Referring to fig. 1 and fig. 2, the present embodiment provides a bump package structure 100, which can avoid an undercut opening formed by excessive corrosion, and has a more stable structure, a better bonding force of a bottom structure, and better heat dissipation and electrical conductivity, thereby effectively alleviating potential failure caused by electromigration and thermal migration.
The bump package structure 100 provided in this embodiment includes a chip 110, a protection layer 120, a substrate adhesion layer 130, a conductive combination layer 140, an electrical pillar 150, and a cap layer 160, wherein a pad is disposed on a front surface of the chip 110, the protection layer 120 is disposed on the front surface of the chip 110, a protection opening 121 corresponding to the pad is disposed on the protection layer 120, and a size of the protection opening 121 is slightly smaller than a size of the pad, so that the pad can be exposed to the protection layer 120. The substrate adhesive layer 130 is disposed in the protection opening 121 and covers the protection opening 121, the conductive combination layer 140 is disposed on the substrate adhesive layer 130, the electrical pillar 150 is disposed on the conductive combination layer 140, and the cap layer 160 is disposed on the electrical pillar 150. The substrate adhesive layer 130 includes a plurality of graphene layers, the top edge of the substrate adhesive layer 130 extends outward onto the protection layer 120 and covers the edge of the protection opening 121, an arc-shaped groove is formed in a surface of the substrate adhesive layer 130, which is away from the chip 110, and at least a portion of the conductive combination layer 140 is accommodated in the arc-shaped groove.
In this embodiment, by disposing the protection layer 120 on the front surface of the chip 110, disposing the protection opening 121 on the protection layer 120, disposing the substrate adhesion layer 130 in the protection opening 121, disposing the conductive combination layer 140 on the substrate adhesion layer 130, and disposing the electrical pillar 150 and the cap layer 160 on the conductive combination layer 140 in sequence, wherein the substrate adhesion layer 130 includes multiple graphene layers, a top edge of the substrate adhesion layer 130 extends outward onto the protection layer 120, and by using the multiple graphene layers, stability and hydrophobicity of the bottom structure can be enhanced. The top edge of the substrate adhesive layer 130 extends outward to the protection layer 120 and covers the edge of the protection opening 121, so that when the micro-etching process is performed, no matter a chemical etching method or a plasma etching method is used, the substrate adhesive layer 130 can avoid an undercut problem caused when the UBM layer is removed by a conventional micro-etching process. Moreover, the coefficient of thermal expansion CTE of the graphene material is only 1/10-1/20 of copper and aluminum, so that deformation of the UBM layer at the bottom of the conductive pillar can be better avoided, and a bonding pad at the bottom and a metal structure at the bottom of the conductive pillar can be protected. The electric conductivity of the graphene material is far higher than that of metal, the heat conductivity is superior, the heat conductivity and the heat conductivity of the multi-layer graphene structure formed along with the increase of the volume of graphene are further improved, the electric conductivity and the heat dissipation performance of the multi-layer graphene structure are greatly improved, the problem that the service life of a copper column lug is remarkably shortened due to abnormal activity of electromigration and heat migration, and potential failure hidden danger is caused is avoided. Meanwhile, the problem that a brittle material layer is damaged due to larger stress caused by a copper column in a packaging body in the prior art is solved by utilizing the stability of the graphene, for example, a bonding pad of a chip 110 at the bottom of the copper column is broken, a UBM metal layer is layered or the fatigue life of a welding spot is reduced, so that the stability of the structure is ensured. In addition, the surface of the substrate bonding layer 130 is provided with an arc-shaped groove, and the conductive combination layer 140 is partially accommodated in the arc-shaped groove, so that the contact area between the conductive combination layer 140 and the substrate bonding layer 130 can be increased, the bonding force between the conductive combination layer and the substrate bonding layer is increased, the stability of the structure is further improved, and the electric convex column 150 is prevented from falling off.
In this embodiment, the depth of the arc-shaped groove is less than the thickness of the substrate adhesive layer 130, so that the arc-shaped groove does not penetrate through to the bonding pad, and the conductive combination layer 140 is laid on the substrate adhesive layer 130, so that the conductive combination layer 140 is accommodated in the arc-shaped groove and forms an arc shape toward the direction close to the chip 110, thereby further improving the structural strength.
In the present embodiment, the conductive combination layer 140 includes a barrier layer 141 and a wetting layer 143, the barrier layer 141 overlying the substrate adhesive layer 130, and the wetting layer 143 overlying the barrier layer 141. Specifically, the barrier layer 141 and the wetting layer 143 are both made of a conductive metal material, for example, the barrier layer 141 may be made of at least one of nickel, vanadium, and chromium, the wetting layer 143 and the conductive pillar are both made of a copper material, the barrier layer 141 can block atomic diffusion between the conductive pillar and the bottom substrate bonding layer 130, and the wetting layer 143 can improve wettability of the bottom of the conductive pillar, thereby improving bonding strength.
In the present embodiment, the thickness H1 of the portion of the base adhesive layer 130 extending to the protective layer 120 is 4 to 8 μm; the thickness H2 of the barrier layer 141 is 4-6 μm; the thickness H3 of the wetting layer 143 is 2-4 μm. Specifically, the thickness H1 of the substrate adhesive layer 130 above the protective layer 120 is 4-8 μm, preferably 4 μm, which can completely prevent the etching residue solution from entering the edge of the protective opening 121, thereby further avoiding the undercut phenomenon. Meanwhile, the barrier layer 141 is an equal thickness layer having a thickness of 4 μm, and the wetting layer 143 is also an equal thickness layer having a thickness of 4 μm. By properly setting the thicknesses of the substrate adhesive layer 130, the barrier layer 141, and the wetting layer 143, it is possible to ensure sufficient structural strength at the joint while ensuring the conductive performance.
In the present embodiment, the portions of the substrate adhesive layer 130 extending to the protective layer 120, the barrier layer 141, and the wetting layer 143 have the same thickness. That is, the thickness of the portion of the substrate adhesive layer 130 extending to the passivation layer 120, the barrier layer 141 and the wetting layer 143 is 4 μm, so that the height of the entire bump structure can be reduced as much as possible while the structural strength and the functional characteristics (such as conductivity, barrier property and wettability) are ensured, which is beneficial to reducing the height of the solder structure.
In the present embodiment, the width L1 of the portion of the substrate adhesive layer 130 extending to the protective layer 120 is 4-8 μm, and the projection of the substrate adhesive layer 130 on the front surface of the chip 110, the projection of the barrier layer 141 on the front surface of the chip 110, and the projection of the wetting layer 143 on the front surface of the chip 110 overlap. Preferably, the width L1 of the portion of the substrate adhesive layer 130 extending to the protective layer 120 is 6 μm, and the edge of the barrier layer 141, the edge of the wetting layer 143, and the edge of the substrate adhesive layer 130 are flush, so that the same mask can be used for etching together during the manufacturing process, thereby simplifying the process steps.
In this embodiment, a side surface of the substrate adhesive layer 130 away from the chip 110 is at least partially concave and forms an arc groove, so that the barrier layer 141 and the wetting layer 143 are both arched toward the chip 110, and a side surface of the electrical pillar 150 close to the chip 110 is at least partially convex and curved. Specifically, the edge of the substrate adhesive layer 130 is kept in a horizontal state and is overlapped on the protective layer 120, and the center of the substrate adhesive layer 130 is concave downward to form an inward concave arc surface, so as to form an arc groove, which can further increase the contact area between the barrier layer 141 and the substrate adhesive layer 130, and thus increase the bonding force.
In the present embodiment, the width of the arc-shaped groove is the same as the width of the protection opening 121, and specifically, the edge of the substrate adhesive layer 130 is horizontal and covers the surface of the protection layer 120, so that the edge of the substrate adhesive layer 130 is planarized and can completely cover the edge of the protection opening 121 to further prevent the occurrence of the undercut phenomenon, and the same thickness of the portion of the substrate adhesive layer 130 extending to the protection layer 120, the barrier layer 141, and the wetting layer 143 can be better achieved. Further, since the barrier layer 141 and the wetting layer 143 are both of an equal thickness layer, the middle portions of the barrier layer 141 and the wetting layer 143 are both arched toward the chip 110, thereby increasing the contact area between the layers to enhance the bonding force. Meanwhile, the edges of the barrier layer 141 and the wetting layer 143 are horizontal, so that the substrate bonding layer 130, the barrier layer 141 and the wetting layer 143 at the edges are more uniformly stressed.
In this embodiment, a stop layer 170 is further disposed on a side of the electrical pillar 150 away from the chip 110, and the stop layer 170 is disposed between the cap layer 160 and the electrical pillar 150 for blocking diffusion atoms between the cap layer 160 and the electrical pillar 150. Specifically, the stop layer 170 may be at least one of nickel, vanadium, and chromium, and an end surface of the electrical pillar 150 away from the chip 110 is horizontal, so that the stop layer 170 is horizontally laid on the end surface of the electrical pillar 150, and the cap layer 160 is laid on the stop layer 170.
The embodiment further provides a method for manufacturing the bump package structure 100, which is used for manufacturing the bump package structure 100, wherein the method includes the following steps:
s1: a chip 110 with pads on its front surface is provided.
Referring to fig. 3, specifically, a chip 110 having pads on a front surface thereof is provided, the chip 110 has a wiring layer therein, and the pads are electrically connected to the wiring layer.
S2: a protective layer 120 is formed on the front surface of the chip 110.
Referring to fig. 4, specifically, a liquid protective material, such as polyimide, may be uniformly spin-coated on the front surface of the chip 110, and then soft-baked by a hot plate, and shaped to form a film and a protective layer 120.
S3: a groove is formed on the passivation layer 120 at a position corresponding to the pad to form a passivation opening 121.
Referring to fig. 5, specifically, the position of the predetermined opening of the protective layer 120 may be masked by a mask on the protective layer 120, and then the unexposed area is removed by spraying a developing solution in a developing manner to leak out the aluminum pad opening position, and then the protective layer 120 is cured to a stable state by using oven heating again. And using a plasma glue residue remover to remove the contaminants or residues on the surface of the passivation layer 120. Of course, the protection layer 120 may be a silicon nitride material.
S4: a base adhesive layer 130 is formed within the protective opening 121.
Referring to fig. 6, specifically, the substrate adhesive layer 130 includes a plurality of graphene layers, a top edge of the substrate adhesive layer 130 extends outward onto the protective layer 120 and covers an edge of the protective opening 121, and a side surface of the substrate adhesive layer 130 away from the chip 110 is provided with an arc-shaped groove.
After the preparation of the protection opening 121 is completed, a graphene material is coated on the protection layer 120, thereby forming a multi-layered graphene structure, in which the graphene material fills the protection opening 121 and covers the surface of the protection layer 120 to a thickness of 4-8 μm, and then the graphene material is accelerated to be cured to a stable state by using oven heating again, thereby forming the substrate bonding layer 130. Then, an etching process is used to etch the graphene in the protection opening 121, so as to form an inner concave arc surface on the substrate bonding layer 130 and form an arc-shaped groove.
S5: a conductive composite layer 140 is formed on the base adhesive layer 130.
Referring to fig. 7, specifically, after the preparation of the arc-shaped groove is completed, a barrier layer 141 may be electroplated on the inner concave arc surface, the material of the barrier layer 141 may be at least one of nickel, vanadium and chromium, and the thickness is between 4 and 6 μm, and then a wetting layer 143 may be electroplated again, and the wetting layer 143 may be a copper layer, and the thickness is between 2 and 4 μm.
S6: the electrical pillars 150 are formed on the conductive combination layer 140.
Referring to fig. 8, specifically, after the wetting layer 143 is formed, a protective adhesive is coated on the surface, a copper pillar opening is opened by using a photolithography process, a copper layer is sputtered on the arc-shaped wetting layer 143 by using an electroplating process again, so as to form a copper pillar, that is, the electrical convex pillar 150 is formed, and the bottom of the electrical convex pillar 150 is in an arc-shaped convex block shape, so that the bonding force between the electrical convex pillar and the lower structure can be improved.
After forming the cell pillars, a stopper layer 170 may be formed on the electrical pillars 150.
S7: cap layer 160 is formed on electrical posts 150.
With continued reference to fig. 1, specifically, a solder layer may be formed on the stop layer 170 by electroplating or ball-planting process, and the cap layer 160 may be formed after reflow. Wherein the cap layer 160 can be a tin cap layer 160.
In summary, in the bump package structure 100 and the method for manufacturing the bump package structure 100 provided in this embodiment, the protection layer 120 is disposed on the front surface of the chip 110, the protection opening 121 is disposed on the protection layer 120, the substrate adhesion layer 130 is disposed in the protection opening 121, the conductive combination layer 140 is disposed on the substrate adhesion layer 130, and the conductive combination layer 140 is sequentially disposed with the electric pillar 150 and the cap layer 160, wherein the substrate adhesion layer 130 includes multiple graphene layers, and the top edge of the substrate adhesion layer 130 extends outward onto the protection layer 120. The top edge of the substrate adhesive layer 130 extends outward to the protection layer 120 and covers the edge of the protection opening 121, so that when the micro-etching process is performed, no matter a chemical etching method or a plasma etching method is used, the substrate adhesive layer 130 can avoid an undercut problem caused when the UBM layer is removed by a conventional micro-etching process. Moreover, the coefficient of thermal expansion CTE of the graphene material is only 1/10-1/20 of copper and aluminum, so that deformation of the UBM layer at the bottom of the conductive pillar can be better avoided, and a bonding pad at the bottom and a metal structure at the bottom of the conductive pillar can be protected. The electric conductivity of the graphene material is far higher than that of metal, the heat conductivity is superior, the heat conductivity and the heat conductivity of the multi-layer graphene structure formed along with the increase of the volume of graphene are further improved, the electric conductivity and the heat dissipation performance of the multi-layer graphene structure are greatly improved, the problem that the service life of a copper column lug is remarkably shortened due to abnormal activity of electromigration and heat migration, and potential failure hidden danger is caused is avoided. Meanwhile, the problem that a brittle material layer is damaged due to larger stress caused by a copper column in a packaging body in the prior art is solved by utilizing the stability of the graphene, for example, a bonding pad of a chip 110 at the bottom of the copper column is broken, a UBM metal layer is layered or the fatigue life of a welding spot is reduced, so that the stability of the structure is ensured. In addition, the surface of the substrate bonding layer 130 is provided with an arc-shaped groove, and the conductive combination layer 140 is partially accommodated in the arc-shaped groove, so that the contact area between the conductive combination layer 140 and the substrate bonding layer 130 can be increased, the bonding force between the conductive combination layer and the substrate bonding layer is increased, the stability of the structure is further improved, and the electric convex column 150 is prevented from falling off.
Second embodiment
Referring to fig. 9, the basic structure and principle of the bump package structure 100 and the technical effects thereof are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents of the first embodiment for the sake of brevity.
In this embodiment, a stop layer 170 is further disposed on a side of the electrical pillar 150 away from the chip 110, the stop layer 170 is disposed between the cap layer 160 and the electrical pillar 150 for blocking diffusion atoms between the cap layer 160 and the electrical pillar 150, further, a conductive adhesive layer 180 is further disposed on a side of the electrical pillar 150 away from the chip 110, the conductive adhesive layer 180 is disposed between the stop layer 170 and the electrical pillar 150, and the conductive adhesive layer 180 is a graphene layer.
Here, the conductive adhesive layer 180 is made of graphene, so that heat dissipation and electrical conduction can be achieved better.
In this embodiment, a side surface of the electrical pillar 150 away from the chip 110 is at least partially concave, so that the stopper layer 170 and the conductive adhesive layer 180 are both arched toward the chip 110, and a side surface of the cap layer 160 close to the chip 110 is at least partially convex. Specifically, the end surface of the electrical convex column 150, which is far away from the chip 110, is an inward concave arc surface, and can form an arc-shaped structure by etching, and the arc-shaped groove at the lower part is matched to form a modified double-arc structure, so that the top end of the electrical convex column 150 is formed into a groove shape, and the bottom of the electrical convex column 150 is a structure with a convex edge and a flat edge, so that the bottom of the electrical convex column 150 can play a better supporting role. Meanwhile, the conductive adhesive layer 180 and the stopper layer 170 are equal-thickness layers, and can form an arch structure protruding towards the chip 110, so that the contact area is increased, and the bonding force is improved.
In the bump package structure 100 provided in this embodiment, the conductive adhesive layer 180 made of graphene is further disposed between the stop layer 170 and the electrical pillar 150, and the substrate adhesive layer 130 below the conductive adhesive layer is used to realize a dual-layer graphene structure, so as to achieve better heat dissipation and conductive properties. Moreover, the arc structure is adopted, so that the contact areas between the conductive bonding layer 180 and the electric convex column 150, between the stopping layer 170 and the conductive bonding layer 180 and between the cap layer 160 and the stopping layer 170 can be increased, the bonding force is increased, and the integral structural strength is ensured. Meanwhile, the stopper layer 170 can well prevent the problem of atomic diffusion downward of the cap layer 160. Moreover, a downward-concave arc structure is adopted, so that the solder can be better locked at the end of the electric convex column 150 far away from the chip 110, and the solder is prevented from overflowing. Meanwhile, the double-layer arc structure is adopted, the sinking directions of the double-layer arc structure are the same, and better stress release can be realized, so that the stress of the structure is buffered, and the electrode is prevented from cracking.
Third embodiment
Referring to fig. 10 and fig. 11, the present embodiment provides a bump package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment for parts not mentioned in the present embodiment.
In the embodiment, the arc groove extends to the edge of the substrate adhesive layer 130, so that a side surface of the substrate adhesive layer 130 away from the chip 110 is an inward concave arc surface. Specifically, the width of the arc groove is greater than the width of the protection opening 121, so that there is no flat structure at the edge of the substrate adhesive layer 130, and the concave arc surface extends directly to the edge of the substrate adhesive layer 130.
In this embodiment, the barrier layer 141 and the wetting layer 143 are also blanket layers, so the edges of the barrier layer 141 and the wetting layer 143 are also formed with a planar structure, and the barrier layer 141 and the wetting layer 143 are arched as a whole in a direction approaching the chip 110.
In this embodiment, a stop layer 170 is further disposed on a side of the electrical pillar 150 away from the chip 110, the stop layer 170 is disposed between the cap layer 160 and the electrical pillar 150 for blocking diffusion atoms between the cap layer 160 and the electrical pillar 150, further, a conductive adhesive layer 180 is further disposed on a side of the electrical pillar 150 away from the chip 110, the conductive adhesive layer 180 is disposed between the stop layer 170 and the electrical pillar 150, and the conductive adhesive layer 180 is a graphene layer. The conductive adhesive layer 180 and the stopper layer 170 are both planar structures, that is, the end surface of the electrical pillar 150 away from the chip 110 is a plane.
In the embodiment, the edge thickness H1 of the substrate adhesive layer 130 may be the sum of the thickness H2 of the barrier layer 141 and the thickness H3 of the wetting layer 143, i.e., H1 — H2+ H3, so as to prevent the chemical agent remaining after etching from wicking to the barrier layer 141, the wetting layer 143 and the electrically conductive pillars. The substrate adhesive layer 130 is made of graphene, and the undercut problem can be prevented by using the hydrophobicity and stability of graphene.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A bump package structure, comprising:
the front surface of the chip is provided with a welding pad;
the protective layer is arranged on the front surface of the chip, and a protective opening corresponding to the welding pad is arranged on the protective layer;
a substrate bonding layer disposed within the protective opening;
a conductive composite layer disposed on the substrate bonding layer;
the electric convex column is arranged on the conductive combination layer;
the cap layer is arranged on the electric convex column;
the substrate bonding layer comprises a plurality of graphene layers, the top edge of the substrate bonding layer extends outwards to the protective layer and covers the edge of the protective opening, an arc-shaped groove is formed in the surface of one side, away from the chip, of the substrate bonding layer, and at least part of the conductive combination layer is accommodated in the arc-shaped groove.
2. The bump package structure of claim 1, wherein the conductive combination layer includes a barrier layer overlying the substrate adhesive layer and a wetting layer overlying the barrier layer.
3. The bump package structure according to claim 2, wherein a thickness H1 of a portion of the substrate adhesive layer extending to the protective layer is 4-8 μm; the thickness H2 of the barrier layer is 4-6 μm; the thickness H3 of the wetting layer was 2-4 μm.
4. The bump package structure according to claim 2, wherein the thickness of the portion of the substrate adhesive layer extending to the protection layer, the barrier layer and the wetting layer is the same.
5. The bump package structure according to claim 2, wherein a width L1 of a portion of the substrate adhesive layer extending to the protection layer is 4-8 μm, and a projection of the substrate adhesive layer on the front surface of the chip, a projection of the barrier layer on the front surface of the chip, and a projection of the wetting layer on the front surface of the chip overlap.
6. The bump package structure according to claim 2, wherein a side surface of the substrate adhesive layer away from the chip is at least partially concave and forms the arc-shaped groove, so that the barrier layer and the wetting layer are both arched toward the chip, and a side surface of the electrical pillar near the chip is at least partially convex and forms a convex arc.
7. The bump package structure according to claim 6, wherein the arc-shaped groove extends to an edge of the substrate adhesive layer, so that a side surface of the substrate adhesive layer away from the chip is an inward-concave arc surface.
8. The bump package structure according to claim 6 or 7, wherein a stopper layer is further disposed on a side of the electrical pillar away from the chip, and the stopper layer is disposed between the cap layer and the electrical pillar for blocking diffusion atoms between the cap layer and the electrical pillar.
9. The bump package structure according to claim 8, wherein a conductive adhesive layer is further disposed on a side of the electrical pillar away from the chip, the conductive adhesive layer is disposed between the stopper layer and the electrical pillar, and the conductive adhesive layer is a graphene layer.
10. The bump package structure of claim 9, wherein at least a portion of a side surface of the electrical pillar away from the chip is an inner concave surface, so that the stopper layer and the conductive adhesive layer are both arched toward the chip, and at least a portion of a side surface of the cap layer close to the chip is an outer convex surface.
11. A method for manufacturing a bump package structure according to any one of claims 1 to 10, comprising:
providing a chip with a welding pad on the front surface;
forming a protective layer on the front side of the chip;
slotting the position, corresponding to the welding pad, on the protective layer to form a protective opening;
forming a substrate bonding layer in the protective opening;
etching the substrate bonding layer to form an arc-shaped groove;
forming a conductive combination layer on the substrate bonding layer;
forming an electric convex column on the conductive combination layer;
forming a cap layer on the electric convex column;
the top edge of the substrate bonding layer extends outwards to the protective layer and covers the edge of the protective opening, and at least part of the conductive combination layer is accommodated in the arc-shaped groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210853382.7A CN115116871A (en) | 2022-07-08 | 2022-07-08 | Bump packaging structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210853382.7A CN115116871A (en) | 2022-07-08 | 2022-07-08 | Bump packaging structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN115116871A true CN115116871A (en) | 2022-09-27 |
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|---|---|---|---|
| CN202210853382.7A Pending CN115116871A (en) | 2022-07-08 | 2022-07-08 | Bump packaging structure and preparation method thereof |
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| Country | Link |
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| CN (1) | CN115116871A (en) |
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- 2022-07-08 CN CN202210853382.7A patent/CN115116871A/en active Pending
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