CN114968151B - Multi-screen display system - Google Patents
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- CN114968151B CN114968151B CN202210127133.XA CN202210127133A CN114968151B CN 114968151 B CN114968151 B CN 114968151B CN 202210127133 A CN202210127133 A CN 202210127133A CN 114968151 B CN114968151 B CN 114968151B
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1431—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using a single graphics controller
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Abstract
The application discloses a multi-screen display system which comprises N display devices and a processor, wherein N is a positive integer greater than or equal to two. The processor comprises a plurality of system data pins, the plurality of system data pins are divided into N groups of data pin groups, the pin number of the N group of data pin groups corresponds to the display color gradation number of the N display device, and the N group of data pin groups are used for outputting horizontal image data and vertical image data of the N display device. The N display device captures the horizontal image data output by the N data pin group in the horizontal effective time section, and captures the vertical image data output by the N data pin group in the vertical effective time section. Therefore, the number of processors in the current product with the multi-screen display function can be saved, and the cost is reduced.
Description
Technical Field
The present application relates to a display system, and more particularly, to a multi-screen display system.
Background
With rapid development of technology, devices having multiple display interfaces, such as a folding mobile phone provided with a dual screen, a stereoscopic display device provided with multiple display surfaces, etc., are increasingly developed as spring bamboo shoots after raining. That is, a single screen product cannot meet the consumer demand, and therefore, a product having a multi-screen display function is a future development trend.
In general, each display device needs to be matched with a processor, and a set of timing control signals are sent by the processor to control the display screen of the display device. For example, when two display devices are provided in a product with a multi-screen display function, the two display devices respectively receive image data sent by different processors (one display device corresponds to each processor), and in this case, the two display devices can respectively capture the image data according to different effective data time.
However, the number of processors increases with the number of display devices, so that the cost of the product increases, and the volume of the product is difficult to develop towards thinness and shortness. Therefore, how to reduce the number of processors used in a product with multi-screen display function is a challenge to be solved.
Disclosure of Invention
The main purpose of the present application is to provide a multi-screen display system, which solves the problems of high cost and difficult development of size towards light, thin and small size caused by that each display device of a product with multi-screen display function needs to be correspondingly connected with a processor to control a display picture in the prior art.
In order to achieve the above object, the present application is achieved by:
The application provides a multi-screen display system which comprises N display devices and a processor, wherein N is a positive integer greater than or equal to two. The processor comprises a plurality of system data pins, the plurality of system data pins are divided into N groups of data pin groups, the pin number of the N group of data pin groups corresponds to the display color gradation number of the N display device, and the N group of data pin groups are used for outputting horizontal image data and vertical image data of the N display device. The N display device captures the horizontal image data output by the N data pin group in the horizontal effective time section, and captures the vertical image data output by the N data pin group in the vertical effective time section.
In the embodiment of the application, the hardware wiring mode of a plurality of display devices is controlled by one processor (the plurality of display devices share a plurality of system data pins of one processor), so that the use amount of the processor and peripheral devices of a product with a multi-screen display function of the multi-screen display system are reduced, the cost of the product with the multi-screen display function is reduced, and the volume of the product with the multi-screen display function is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a block diagram of one embodiment of a multi-screen display system according to the present application;
FIG. 2 is a schematic diagram illustrating a control scheme of one horizontal scanning period of an embodiment of the multi-screen display system of FIG. 1;
FIG. 3 is a schematic diagram illustrating a control scheme of one vertical scanning period of an embodiment of the multi-screen display system of FIG. 1;
FIG. 4 is a schematic diagram illustrating a control scheme of one horizontal scanning period of another embodiment of the multi-screen display system of FIG. 1;
FIG. 5 is a schematic diagram illustrating a control scheme of one vertical scanning period of another embodiment of the multi-screen display system of FIG. 1;
FIG. 6 is a block diagram of another embodiment of a multi-screen display system of the present application;
FIG. 7 is a diagram of an embodiment of image data according to the present application;
FIG. 8 is a schematic view of an embodiment of image data segmentation according to the present application;
FIG. 9 is a schematic diagram of an embodiment of a control method according to the present application;
FIG. 10 is a schematic diagram of another embodiment of image data of the present application;
FIG. 11 is a schematic view of another embodiment of image data segmentation according to the present application;
FIG. 12 is a schematic diagram of another embodiment of the control scheme of the present application;
FIG. 13 is a block diagram of yet another embodiment of a multi-screen display system of the present application;
FIG. 14 is a schematic view of still another embodiment of image data of the present application;
FIG. 15 is a schematic view of still another embodiment of image data of the present application, and
Fig. 16 is a schematic view of a control method according to still another embodiment of the present application.
Detailed Description
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.
It should be appreciated that the use of the terms "comprising," "including," and the like in this specification are intended to specify the presence of stated features, values, method steps, operation processes, components, and/or groups thereof, but do not preclude the addition of further features, values, method steps, operation processes, components, groups thereof, or groups thereof.
It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Referring to fig. 1, a block diagram of a multi-screen display system according to an embodiment of the application is shown. As shown in FIG. 1, the multi-screen display system 100 includes two display devices (i.e., display device 110a and display device 110 b) and a processor 120. In the present embodiment, the number of the display devices is two, but the present embodiment is not limited to the present application, and for example, the number of the display devices may be a positive integer greater than two.
In this embodiment, the processor 120 includes a system data pin 122a, a system data pin 122b, a system data pin 122c, a system data pin 122d, a system data pin 122e, a system data pin 122f, a system data pin 122g and a system data pin 122h (i.e., the processor 120 includes a plurality of system data pins), wherein the system data pin 122a, the system data pin 122b, the system data pin 122c and the system data pin 122d are the first data pin group 50a, the system data pin 122e, the system data pin 122f, the system data pin 122g and the system data pin 122h are the second data pin group 50b (i.e., the plurality of system data pins are divided into two data pin groups), the first data pin set 50a corresponds to the display color level of the first display device 110a, the second data pin set 50b corresponds to the display color level of the second display device 110b (i.e., the pin number of the nth data pin set corresponds to the display color level of the nth display device), the first data pin set 50a is used for outputting the horizontal image data 81 and the vertical image data 91 of the first display device 110a, and the second data pin set 50b is used for outputting the horizontal image data 82 and the vertical image data 92 of the second display device 110b (i.e., the nth data pin set is used for outputting the horizontal image data and the vertical image data of the nth display device).
In more detail, the system data pins 122a, 122b, 122c, 122d, 122e, 122f, 122g and 122h are eight-bit data buses (8-bits data buses) of the processor 120, the display device 110a includes a driving circuit 112a, the driving circuit 112a includes a display pin set 114a, the display device 110b includes a driving circuit 112b, the driving circuit 112b includes a display pin set 114b, and when the display device 110a and the display device 110b respectively display four bits (16-bit) of tone-scale data (i.e., the display device 110a and the display device 110b do not need to display eight bits (256-bit) of tone-scale data), the display device 110a and the display device 110b can share the eight-bit data buses (i.e., the display device includes the system data pins 122a, 122b, the system data pins 122c and the first set 50a of the system data pins 122d are connected to the display pin set 110a of the display device 110a, the system data pins 122b include the second set 122e and the system data pins 122b are connected to the display device 110b and the display device 110 b. That is, the plurality of display devices may share the data bus of the processor 120 having a complex bit width according to the number of gradation levels displayed by themselves, and in one embodiment, when the display device 110a displays three bits (8 gradation levels) of gradation data and the display device 110b displays six bits (32 gradation levels) of gradation data, the display device 110a and the display device 110b may share the nine-bit data bus of the processor 120. It should be noted that each display device included in the multi-screen display system 100 may display odd-bit tone scale data, or even-bit tone scale data.
In this embodiment, referring to fig. 1 to 3, fig. 2 is a schematic diagram illustrating a control manner of one horizontal scanning period in an embodiment of the multi-screen display system of fig. 1, fig. 3 is a schematic diagram illustrating a control manner of one vertical scanning period in an embodiment of the multi-screen display system of fig. 1, wherein fig. 2 includes a waveform timing chart of signals output from the data pin group 50a and the data pin group 50b and a waveform timing chart of signals received from the display pin group 114a and the display pin group 114b in one horizontal scanning period, and fig. 3 includes a waveform timing chart of signals output from the data pin group 50a and the data pin group 50b and a waveform timing chart of signals received from the display pin group 114a and the display pin group 114b in one vertical horizontal scanning period. As shown in fig. 1 to 3, since the first data pin set 50a is used for outputting the horizontal image data 81 and the vertical image data 91 of the first display device 110a, the first display device 110a captures the horizontal image data 81 output by the first data pin set 50a in the horizontal effective time period t HACT and the vertical image data 91 output by the first data pin set 50a in the vertical effective time period t VACT, and the second display device 110b captures the horizontal image data 82 output by the second data pin set 50b in the horizontal effective time period t HACT and the vertical image data 92 output by the second data pin set 50b in the vertical effective time period t VACT, respectively, because the second data pin set 50b is used for outputting the horizontal image data 82 and the vertical image data 92 of the second display device 110 b.
It should be noted that the horizontal image data output by each data pin group includes horizontal blank (blanking) data and horizontal effective data, the horizontal effective data is data output by each data pin group in the horizontal effective time section t HACT, and is pixel data of each row of effective pixels displayed by the corresponding connected display device, the vertical image data output by each data pin group includes vertical blank data and vertical effective data, the vertical effective data is data output by each data pin group in the vertical effective time section t VACT, and is line data of effective pixels of each frame (frame) displayed by the corresponding connected display device, so that each display device in the multi-screen display system 100 captures the horizontal image data output by the corresponding connected data pin group in the horizontal effective time section t HACT, and captures the vertical image data output by the corresponding connected data pin group in the vertical effective time section t VACT, so as to display a picture data. In fig. 2 and 3, the horizontal blank data and the vertical blank data outputted from the data pin set 50a and the data pin set 50b are invalid data for the display device 110a and the display device 110b, and are not drawn in the diagrams of fig. 2 and 3.
In an embodiment, when the pin numbers of any two sets of data pin groups are the same, the resolutions of the display devices correspondingly connected to any two sets of data pin groups are the same. In more detail, since the pin numbers of any two sets of data pin groups are the same, the bit numbers representing the data received by the display device to which the any two sets of data pin groups are correspondingly connected are also the same, and therefore the resolutions of the display devices to which the any two sets of data pin groups are correspondingly connected are the same.
Referring to fig. 1 to 3, in this embodiment, the processor 120 further includes a vertical synchronization pin 124, a horizontal synchronization pin 126 and a clock pin 128, wherein the vertical synchronization pin 124 is used for outputting a vertical synchronization signal VS to the display device 110a and the display device 110b, the horizontal synchronization pin 126 is used for outputting a horizontal synchronization signal HS to the display device 110a and the display device 110b, the clock pin 128 is used for outputting a clock signal DCLK to the display device 110a and the display device 110b, the driving mode of the display device 110a and the display device 110b can be the driving mode of the synchronization signals, the clock signal DCLK is used for indicating the transmission frequency of the horizontal image data 81, 82, that is, the display device 110a and the display device 110b can be driven by the horizontal synchronization signal HS and the vertical synchronization signal VS. Fig. 2 further includes a waveform timing diagram of signals output from the horizontal sync pin 126 and the clock pin 128 in one horizontal scan period, and fig. 3 further includes a waveform timing diagram of signals output from the vertical sync pin 124 and the horizontal sync pin 126 in one vertical horizontal scan period.
Specifically, the horizontal image data outputted from each data pin set includes horizontal blank data and horizontal valid data, the vertical image data outputted from each data pin set includes vertical blank data and vertical valid data, the display device 110a captures the horizontal image data 81 outputted from the data pin set 50a in the horizontal valid time section t HACT according to the clock signal DCLK and the horizontal synchronization signal HS (i.e. the data pin set 50a outputs the horizontal valid data in the horizontal valid time section t HACT), and captures the vertical image data 91 outputted from the data pin set 50a in the vertical valid time section t VACT according to the horizontal synchronization signal HS and the vertical synchronization signal VS (i.e. the data pin set 50a outputs the vertical valid data in the vertical valid time section t VACT), so as to display a frame data. The driving circuits 112a and 112b can calculate the horizontal trailing edge time period t HBP and the horizontal leading edge time period t HFP of the output horizontal blank data and the horizontal effective time period t HACT of the output horizontal effective data by the pulse of the horizontal synchronizing signal HS and the leading edge (front porch) period and the trailing edge (back porch) period thereof, and the driving circuits 112a and 112b can calculate the vertical trailing edge time period t VBP and the vertical leading edge time period t VFP of the output vertical blank data and the vertical effective time period t VACT of the output vertical effective data by the pulse of the vertical synchronizing signal VS and the leading edge period and the trailing edge period thereof.
Similarly, the display device 110b captures the horizontal image data 82 outputted from the data pin set 50b in the horizontal effective time period t HACT according to the clock signal DCLK and the horizontal synchronization signal HS (i.e. the data pin set 50b outputs the horizontal effective data in the horizontal effective time period t HACT), and captures the vertical image data 92 outputted from the data pin set 50b in the vertical effective time period t VACT according to the horizontal synchronization signal HS and the vertical synchronization signal VS (i.e. the data pin set 50b outputs the vertical effective data in the vertical effective time period t VACT), so as to display a frame data.
In addition, since the data pin set 50a outputs the horizontal blank data in the horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP, the display device 110a does not capture the horizontal image data 81 outputted by the data pin set 50a in the horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP according to the clock signal DCLK and the horizontal synchronization signal HS. The horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP correspond to a time section between the data pin group 50a outputting the pixel data of the valid pixels of different rows (i.e., two adjacent horizontal valid data), that is, a preparation time required for the data pin group 50a to output one horizontal valid data in the horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP. The horizontal effective time section t HACT is located between the horizontal trailing time section t HBP and the horizontal leading time section t HFP, and the sum of the horizontal effective time section t HACT, the horizontal trailing time section t HBP and the horizontal leading time section t HFP is one horizontal scanning period.
Similarly, since the data pin set 50b outputs the horizontal blank data in the horizontal back-porch time period t HBP and the horizontal front-porch time period t HFP, the display device 110b does not capture the horizontal image data 82 outputted by the data pin set 50b in the horizontal back-porch time period t HBP and the horizontal front-porch time period t HFP according to the clock signal DCLK and the horizontal synchronization signal HS. The horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP correspond to a time section between the output of the pixel data of the different rows of the effective pixels (i.e., two adjacent horizontal effective data) by the data pin group 50b, that is, a preparation time required for the output of one horizontal effective data by the data pin group 50b by the horizontal back-porch time section t HBP and the horizontal front-porch time section t HFP.
In addition, since the data pin set 50a outputs the vertical blank data in the vertical back-porch time section t VBP and the vertical front-porch time section t VFP, the display device 110a does not capture the vertical image data outputted by the data pin set 50a in the vertical back-porch time section t VBP and the vertical front-porch time section t VFP according to the vertical synchronization signal VS and the horizontal synchronization signal HS. The vertical back-porch time period t VBP and the vertical front-porch time period t VFP correspond to a time period between the output of the line data (i.e., two adjacent vertical valid data) of the valid pixels of different frames by the data pin group 50a, that is, a preparation time required for the output of one vertical valid data by the data pin group 50a by the vertical back-porch time period t VBP and the vertical front-porch time period t VFP. The vertical effective time section t VACT is located between the vertical trailing time section t VBP and the vertical leading time section t VFP, and the sum of the vertical effective time section t VACT, the vertical trailing time section t VBP and the vertical leading time section t VFP is a vertical scanning period.
Similarly, since the data pin set 50b outputs the vertical blank data in the vertical back-porch time section t VBP and the vertical front-porch time section t VFP, the display device 110b does not capture the vertical image data outputted from the data pin set 50b in the vertical back-porch time section t VBP and the vertical front-porch time section tVFP according to the vertical synchronization signal VS and the horizontal synchronization signal HS. The vertical back-porch time section t VBP and the vertical front-porch time section t VFP correspond to a time section between the output of the line data (i.e., two adjacent vertical valid data) of the valid pixels of the different frames by the data pin group 50b, that is, a preparation time required for the output of one vertical valid data by the data pin group 50b by the vertical back-porch time section t VBP and the vertical front-porch time section t VFP.
In an embodiment, referring to fig. 1, fig. 4 and fig. 5, fig. 4 is a schematic diagram illustrating a control manner of one horizontal scanning period in another embodiment of the multi-screen display system of fig. 1, and fig. 5 is a schematic diagram illustrating a control manner of one vertical scanning period in another embodiment of the multi-screen display system of fig. 1. As shown in fig. 1,4 and 5, the processor 120 further includes a clock pin 128 and a data enable pin 129, the clock pin 128 is configured to output a clock signal DCLK to the display device 110a and the display device 110b, the data enable pin 129 is configured to output a data enable signal DE to the display device 110a and the display device 110b, the driving modes of the display device 110a and the display device 110b can be data enable driving modes, and the clock signal DCLK is configured to indicate a transmission frequency of horizontal image data, that is, the display device 110a and the display device 110b can be display driven by the data enable signal DE. Wherein, fig. 4 includes a waveform timing diagram of the output signals of the clock pin 128, the data enable pin 129, the data pin set 50a and the data pin set 50b and a waveform timing diagram of the received signals of the display pin set 114a and the display pin set 114b in one horizontal scan period, and fig. 5 includes a waveform timing diagram of the output signals of the data enable pin 129, the data pin set 50a and the data pin set 50b and a waveform timing diagram of the received signals of the display pin set 114a and the display pin set 114b in one vertical scan period.
Specifically, the horizontal image data outputted from each data pin group includes horizontal blank data and horizontal valid data, the vertical image data outputted from each data pin group includes vertical blank data and vertical valid data, the display device 110a captures the horizontal image data 81 outputted from the data pin group 50a in the horizontal valid time section t HACT according to the data enable signal DE and the clock signal DCLK (i.e. the data pin group 50a outputs the horizontal valid data in the horizontal valid time section t HACT), and captures the vertical image data 91 outputted from the data pin group 50a in the vertical valid time section t VACT according to the data enable signal DE (i.e. the data pin group 50a outputs the vertical valid data in the vertical valid time section t VACT), so as to display a frame data. The driving circuits 112a and 112b may acquire the horizontal blank time section t HBL for outputting the horizontal blank data, the horizontal effective time section t HACT for outputting the horizontal effective data, the vertical blank time section t VBL for outputting the vertical blank data, and the vertical effective time section t VACT for outputting the vertical effective data by the pulses of the data enable signal DE.
Similarly, the display device 110b captures the horizontal image data 82 outputted from the data pin set 50b in the horizontal effective time period t HACT (i.e. the data pin set 50b outputs the horizontal effective data in the horizontal effective time period t HACT) according to the data enable signal DE and the clock signal DCLK, and captures the vertical image data 92 outputted from the data pin set 50b in the vertical effective time period t VACT according to the data enable signal DE (i.e. the data pin set 50b outputs the vertical effective data in the vertical effective time period t VACT) to display a frame data.
It should be noted that, in fig. 4 and fig. 5, the horizontal blank data and the vertical blank data outputted from the data pin set 50a and the data pin set 50b are invalid data for the display device 110a and the display device 110b, and are therefore not drawn in the diagrams of fig. 4 and fig. 5.
In addition, since the data pin set 50a outputs the horizontal blank data in the horizontal blank time section t HBL, the display device 110a does not capture the horizontal image data 81 outputted from the data pin set 50a in the horizontal blank time section t HBL according to the data enable signal DE and the clock signal DCLK. The horizontal blanking period t HBL corresponds to a period between the data pin group 50a outputting the pixel data of the valid pixels of different rows (i.e., two adjacent horizontal blanking periods), that is, the horizontal blanking period t HBL is a preparation time required for outputting one horizontal blanking period for the data pin group 50a, and the sum of the horizontal blanking period t HACT and the horizontal blanking period t HBL is one horizontal scanning period.
Similarly, since the data pin set 50b outputs the horizontal blank data in the horizontal blank time period t HBL, the display device 110b does not capture the horizontal image data 82 outputted by the data pin set 50b in the horizontal blank time period t HBL according to the data enable signal DE and the clock signal DCLK. The horizontal blanking period t HBL corresponds to a period between the data pin group 50b outputting the pixel data of the valid pixels of different rows (i.e., two adjacent horizontal valid data), that is, the horizontal blanking period t HBL is a preparation time required for the data pin group 50b to output one horizontal valid data.
In addition, since the data pin set 50a outputs the vertical blank data in the vertical blank time period t VBL, the display device 110a does not capture the vertical image data 91 outputted from the data pin set 50a in the vertical blank time period t VBL according to the data enable signal DE. The vertical blanking period t VBL corresponds to a period between the data pin group 50a outputting the line data of the effective pixels of different frames (i.e., two adjacent vertical effective data), that is, the vertical blanking period t VBL is a preparation time required for outputting one vertical effective data for the data pin group 50a, and the sum of the vertical effective period t VACT and the vertical blanking period t VBL is one vertical scanning period.
Similarly, since the data pin set 50b outputs the vertical blank data in the vertical blank time period t VBL, the display device 110b does not capture the vertical image data 92 outputted by the data pin set 50b in the vertical blank time period t VBL according to the data enable signal DE. The vertical blanking period t VBL corresponds to a period between the data pin group 50b outputting the line number data of the effective pixels of different frames (i.e., two adjacent vertical effective data), that is, the vertical blanking period t VBL is a preparation time required for outputting one vertical effective data for the data pin group 50 b.
Fig. 6 to 9 are block diagrams of another embodiment of the multi-screen display system, an embodiment of image data splitting schematic diagram, and an embodiment of control mode according to the present application. As shown, the multi-screen display system 1 includes a processor 10, a1 st display device 11, and a 2 nd display device 12. In other words, in the present embodiment, the number of displays is 2, that is, n=2. The processor 10 outputs a data enable signal DE, image data D, and valid data time t.
In the present embodiment, the data size of the image data D output by the processor 10 is mxn. Specifically, the image data D is composed of horizontal image data hd_mcu (TX) and vertical image data vd_mcu (TX) corresponding to the data enable signal DE. The size of the horizontal image data hd_mcu (TX) is M, and the size of the vertical image data vd_mcu (TX) is N. In order for the 1 st display device 11 and the 2 nd display device 12 to display different pictures, the image data D is further divided into image data of size mxn 1 and image data of size mxn 2, wherein the image data of size mxn 1 corresponds to the 1 st display device 11 and the image data of size mxn 2 corresponds to the 2 nd display device 12. That is, among the image data D, the horizontal image data hd_lcds 1 (RX) of the 1 st display device 11 and the horizontal image data hd_lcds 2 (RX) of the 2 nd display device 12 are the same in size (all are M), but the vertical image data vd_lcds 1 (RX) of the 1 st display device 11 and the vertical image data vd_lcds 2 (RX) of the 2 nd display device 12 are different in size (N1, N2, respectively), so that the 1 st display device 11 and the 2 nd display device 12 have different image data to display different pictures. The valid data time t includes a 1 st vertical valid data time interval t VD1_delay, a2 nd vertical valid data time interval t VD2_delay, a 1 st vertical valid data time t VD1, a2 nd vertical valid data time t VD2, a 1 st horizontal valid data time interval t HD1_delay, a2 nd horizontal valid data time interval t HD2_delay, a 1 st horizontal valid data time t HD1, and a2 nd horizontal valid data time t HD2.
In addition, in fig. 9, for ease of understanding, the data enable signal DE may be divided into a data enable signal de_mcu (TX) issued by the processor 10, a data enable signal de_lcds 1 (RX) corresponding to the 1 st display device 11, and a data enable signal de_lcds 2 (RX) corresponding to the 2 nd display device 12. Among them, the 1 st display device 11 displays an image by a high level of the data enable signal de_lcds 1 (RX), and the 2 nd display device 12 displays an image by a high level of the data enable signal de_lcds 2 (RX).
The 1 st display device 11 includes a 1 st driving circuit 111, and the 1 st display device 11 receives the data enable signal DE, the image data D, and the valid data time t from the processor 10. The 1 st driving circuit 111 captures the vertical image data vd_mcu (TX) in the image data D according to the 1 st vertical effective data time t VD1, and captures the horizontal image data hd_mcu (TX) in the image data D according to the 1 st horizontal effective data time t HD1. Since the vertical image data vd_mcus (TX) include both the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 and the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12, the 1 st driving circuit 111 needs to capture the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 from among the vertical image data vd_mcus (TX) according to the 1 st vertical effective data time t VD1, and cannot capture the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 from among the vertical image data vd_mcus (TX). On the other hand, the 1 st driving circuit 111 needs to capture the horizontal image data hd_lcds 1 (RX) corresponding to the 1 st display device 11 in the horizontal image data hd_mcus (TX) according to the 1 st horizontal effective data time t HD1. In the present embodiment, since the horizontal image data hd_lcds 1 (RX) of the 1 st display device 11 and the horizontal image data hd_lcds 2 (RX) of the 2 nd display device 12 are the same in size, the 1 st horizontal effective data time t HD1 and the 2 nd horizontal effective data time t HD2 are the same. In other words, the horizontal image data hd_mcu (TX) is equal to the horizontal image data hd_lcds 1 (RX) and the horizontal image data hd_lcds 2 (RX).
More specifically, for the 1 st display device 11, one vertical synchronization signal VS (or a frame) may be divided into two sections, which are the 1 st vertical valid data time interval t VD1_delay and the 1 st vertical valid data time t VD1, respectively. First, the 1 st driving circuit 111 controls the 1 st display device 11 to start accessing the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time interval t VD1_delay, and the 1 st vertical effective data time interval t VD1_delay in the present embodiment is 0. Next, the 1 st display device 11 captures the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time t VD1, and stops capturing the vertical image data vd_mcu (TX) after the 1 st vertical effective data time t VD1 is completed. In this way, the 1 st display device 11 only accesses the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 among the vertical image data vd_mcus (TX), and does not access the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 among the vertical image data vd_mcus (TX).
On the other hand, a Horizontal synchronization signal HS (or a Horizontal line) may be divided into two sections, which are the 1st Horizontal valid data time interval t HD1_delay and the 1st Horizontal valid data time t HD1, respectively. First, the 1st driving circuit 111 controls the 1st display device 11 to start accessing the horizontal image data hd_mcu (TX) according to the 1st horizontal valid data time interval t HD1_delay. Next, the 1st display device 11 captures the horizontal image data hd_mcu (TX) according to the 1st horizontal effective data time t HD1, and stops capturing the horizontal image data hd_mcu (TX) after the 1st horizontal effective data time t HD1 is completed. In the present embodiment, the 1st display device 11 accesses the complete horizontal image data hd_mcu (TX).
The 2 nd display device 12 includes a2 nd driving circuit 121, and the 2 nd display device 12 receives the data enable signal DE, the image data D, and the valid data time t from the processor 10. The 2 nd driving circuit 121 captures the vertical image data vd_mcu (TX) in the image data D according to the 2 nd vertical effective data time t VD2, and captures the horizontal image data hd_mcu (TX) in the image data D according to the 2 nd horizontal effective data time t HD2. Since the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 and the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 are included in the vertical image data vd_mcus (TX), the 2 nd driving circuit 121 needs to extract the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 from the vertical image data vd_mcus (TX) according to the 2 nd vertical effective data time t VD2, and cannot extract the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 from the vertical image data vd_mcus (TX). On the other hand, the 2 nd driving circuit 121 needs to capture the horizontal image data hd_lcds 2 (RX) corresponding to the 2 nd display device 12 in the horizontal image data hd_mcus (TX) according to the 2 nd horizontal valid data time t HD2. In the present embodiment, the horizontal image data hd_mcu (TX) is equal to the horizontal image data hd_lcds 1 (RX) and the horizontal image data hd_lcds 2 (RX).
More specifically, for the 2 nd display device 12, one vertical synchronization signal VS (or one frame) may be divided into two sections, which are the 2 nd vertical valid data time interval t VD2 _delay, and the 2 nd vertical valid data time t VD2, respectively. First, the 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time interval t VD2 _delay, and the 2 nd vertical effective data time interval t VD2 _delay is equal to the sum of the 1 st vertical effective data time interval t VD1_delay and the 1 st vertical effective data time t VD1. Next, the 2 nd display device 12 captures the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time t VD2, and stops capturing the vertical image data vd_mcu (TX) after the 2 nd vertical effective data time t VD2 is completed. In this way, the 2 nd display device 12 only accesses the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 in the vertical image data vd_mcus (TX), but does not access the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 in the vertical image data vd_mcus (TX).
On the other hand, a horizontal synchronization signal HS (or a horizontal line) may be divided into two sections, which are the 2 nd horizontal valid data time interval t HD2_delay and the 2 nd horizontal valid data time t HD2, respectively. First, the 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time interval t HD2_delay. Next, the 2 nd display device 12 captures the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time t HD2, and stops capturing the horizontal image data hd_mcu (TX) after the 2 nd horizontal valid data time t HD2 is completed. In the present embodiment, the 2 nd display device 12 accesses the complete horizontal image data hd_mcu (TX).
Please refer to fig. 6 and fig. 10 to fig. 12. Fig. 10 to 12 are diagrams illustrating another embodiment of image data, another embodiment of segmentation schematic of image data, and another embodiment of control mode of the multi-screen display system of the present application, respectively. As shown, the multi-screen display system 1 includes a processor 10, a1 st display device 11, and a 2 nd display device 12. In the first embodiment and the second embodiment, the same reference numerals denote similar or identical elements, and thus a detailed description thereof will be omitted. In the present embodiment, the data size of the image data D output by the processor 10 is mxn. The image data D is further divided into image data of size M1 x N and image data of size M2 x N, wherein the image data of size M1 x N corresponds to the 1 st display device 11 and the image data of size M2 x N corresponds to the 2 nd display device 12. That is, among this image data D, the horizontal image data hd_lcds 1 (RX) of the 1 st display device 11 and the horizontal image data hd_lcds 2 (RX) of the 2 nd display device 12 are different in size (M1, M2, respectively), and the vertical image data vd_lcds 1 (RX) of the 1 st display device 11 and the vertical image data vd_lcds 2 (RX) of the 2 nd display device 12 are the same in size (both are N), so that the 1 st display device 11 and the 2 nd display device 12 have different image data to display different pictures.
The 1 st driving circuit 111 controls the 1 st display device 11 to start accessing the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time interval t VD1_delay. Next, the 1 st display device 11 captures the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time t VD1, and stops capturing the vertical image data vd_mcu (TX) after the 1 st vertical effective data time t VD1 is completed. In the present embodiment, the 1 st display device 11 accesses the complete vertical image data vd_mcu (TX).
On the other hand, the 1 st driving circuit 111 controls the 1 st display device 11 to start accessing the horizontal image data hd_mcu (TX) according to the 1 st horizontal effective data time interval t HD1_delay, and the 1 st horizontal effective data time interval t HD1_delay in the present embodiment is 0. Next, the 1 st display device 11 captures the horizontal image data hd_mcu (TX) according to the 1 st vertical effective data time t VD1, and stops capturing the horizontal image data hd_mcu (TX) after the 1 st horizontal effective data time t HD1 is completed. In this way, the 1 st display device 11 accesses only the horizontal image data hd_lcd1 (RX) corresponding to the 1 st display device 11 among the horizontal image data hd_mcus (TX), and does not access the horizontal image data hd_lcd2 (RX) corresponding to the 2 nd display device 12 among the horizontal image data hd_mcus (TX).
The 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time interval t VD2_delay. Next, the 2 nd display device 12 captures the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time t VD2, and stops capturing the vertical image data vd_mcu (TX) after the 2 nd vertical effective data time t VD2 is completed. In the present embodiment, the 2 nd display device 12 accesses the complete vertical image data vd_mcu (TX).
On the other hand, the 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time interval t HD2_delay, and the 2 nd horizontal valid data time interval t HD2_delay in the present embodiment is the sum of the 1 st horizontal valid data time interval t HD1_delay and the 1 st horizontal valid data time t HD1. Next, the 2 nd display device 12 captures the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time t HD2, and stops capturing the horizontal image data hd_mcu (TX) after the 2 nd horizontal valid data time t HD2 is completed. In this way, the 2 nd display device 12 only accesses the horizontal image data hd_lcd2 (RX) corresponding to the 2 nd display device 12 in the horizontal image data hd_mcu (TX), and does not access the horizontal image data hd_lcd1 (RX) corresponding to the 1 st display device 11 in the horizontal image data hd_mcu (TX).
Please refer to fig. 13-16. Fig. 13 to 16 are block diagrams of still another embodiment of the multi-screen display system, a further embodiment of image data division schematic, and a further embodiment of control means of the present application, respectively. As shown, the multi-screen display system 2 includes a processor 10, a1 st display device 11, a2 nd display device 12, and a3 rd display device 13. In this embodiment, the number of displays is 3, i.e., n=3. In the first embodiment and the third embodiment, the same reference numerals denote similar or identical elements, and thus a detailed description thereof will be omitted. In the present embodiment, the data size of the image data D output by the processor 10 is mxn. The image data D is further divided into image data of size mxn 1, image data of size mxn 2, and image data of size mxn 3, wherein the image data of size mxn 1 corresponds to the 1 st display device 11, the image data of size mxn 2 corresponds to the 2 nd display device 12, and the image data of size mxn 3 corresponds to the 3 rd display device 13. That is, among this image data D, the vertical image data vd_lcds 1 (RX) of the 1 st display device 11, the vertical image data vd_lcds 2 (RX) of the 2 nd display device 12, and the vertical image data vd_lcds 3 (RX) of the 3 rd display device 13 are different in size from each other (N1, N2, and N3, respectively), and the horizontal image data hd_lcds 1 (RX) of the 1 st display device 11, the horizontal image data hd_lcds 2 (RX) of the 2 nd display device 12, and the horizontal image data hd_lcds 1 (RX) of the 3 rd display device 13 are the same in size (all are M), so that the 1 st display device 11, the 2 nd display device 12, and the 3 rd display device 13 have different image data to display different pictures.
First, the 1 st driving circuit 111 controls the 1 st display device 11 to start accessing the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time interval t VD1_delay, and the 1 st vertical effective data time interval t VD1_delay in the present embodiment is 0. Next, the 1 st display device 11 captures the vertical image data vd_mcu (TX) according to the 1 st vertical effective data time t VD1, and stops capturing the vertical image data vd_mcu (TX) after the 1 st vertical effective data time t VD1 is completed. In this way, the 1 st display device 11 accesses only the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 among the vertical image data vd_mcus (TX), and does not access the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 among the vertical image data vd_mcus (TX) and the vertical image data vd_lcds 3 (RX) corresponding to the 3 rd display device 13.
On the other hand, the 1 st driving circuit 111 controls the 1 st display device 11 to start accessing the horizontal image data hd_mcu (TX) according to the 1 st horizontal effective data time interval t HD1_delay. Next, the 1 st display device 11 captures the horizontal image data hd_mcu (TX) according to the 1 st horizontal effective data time t HD1, and stops capturing the horizontal image data hd_mcu (TX) after the 1 st horizontal effective data time t HD1 is completed. In the present embodiment, the 1 st display device 11 accesses the complete horizontal image data hd_mcu (TX).
The 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time interval t VD2 _delay, and the 2 nd vertical effective data time interval t VD2 _delay is equal to the sum of the 1 st vertical effective data time interval t VD1_delay and the 1 st vertical effective data time t VD1. Next, the 2 nd display device 12 captures the vertical image data vd_mcu (TX) according to the 2 nd vertical effective data time t VD2, and stops capturing the vertical image data vd_mcu (TX) after the 2 nd vertical effective data time t VD2 is completed. In this way, the 2 nd display device 12 only accesses the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12 among the vertical image data vd_mcus (TX), but does not access the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 among the vertical image data vd_mcus (TX) and the vertical image data vd_lcds 3 (RX) corresponding to the 3 rd display device 13.
On the other hand, the 2 nd driving circuit 121 controls the 2 nd display device 12 to start accessing the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time interval t HD2_delay. Next, the 2 nd display device 12 captures the horizontal image data hd_mcu (TX) according to the 2 nd horizontal valid data time t HD2, and stops capturing the horizontal image data hd_mcu (TX) after the 2 nd horizontal valid data time t HD2 is completed. In the present embodiment, the 2 nd display device 12 accesses the complete horizontal image data hd_mcu (TX).
The 3 rd driving circuit 131 controls the 3 rd display device 13 to start accessing the vertical image data vd_mcu (TX) according to the 3 rd vertical valid data time interval t VD3_delay, and the 3 rd vertical valid data time interval t VD3_delay is equal to the sum of the 1 st vertical valid data time interval t VD1_delay, the 1 st vertical valid data time t VD1 and the 2 nd vertical valid data time t VD2. Next, the 3 rd display device 13 captures the vertical image data vd_mcu (TX) according to the 3 rd vertical effective data time t VD3, and stops capturing the vertical image data vd_mcu (TX) after the 3 rd vertical effective data time t VD3 is completed. In this way, the 3 rd display device 13 only accesses the vertical image data vd_lcds 3 (RX) corresponding to the 3 rd display device 13 among the vertical image data vd_mcus (TX), but does not access the vertical image data vd_lcds 1 (RX) corresponding to the 1 st display device 11 among the vertical image data vd_mcus (TX).
On the other hand, the 3 rd driving circuit 131 controls the 3 rd display device 13 to start accessing the horizontal image data hd_mcu (TX) according to the 3 rd horizontal valid data time interval t HD3_delay. Next, the 3 rd display device 13 captures the horizontal image data hd_mcu (TX) according to the 3 rd horizontal valid data time t HD3, and stops capturing the horizontal image data hd_mcu (TX) after the 3 rd horizontal valid data time t HD3 is completed. In the present embodiment, the 1 st display device 11 accesses the complete horizontal image data hd_mcu (TX) and the vertical image data vd_lcds 2 (RX) corresponding to the 2 nd display device 12.
It should be noted that in the embodiments of fig. 6 to 16 of the present application, the display device may control the display effect by the data enable signal DE, but the present application is not limited thereto. In the three embodiments shown in fig. 6 to 16 or other embodiments, the processor 10 may further output the pixel clock signal DCLK, the vertical synchronization signal VS and the horizontal synchronization signal HS to correspond to the display devices with different operation modes.
In summary, the multi-screen display system according to the embodiment of the present application controls the hardware connection mode of the multiple display devices through one processor (the multiple display devices share multiple system data pins of one processor), so as to reduce the usage of the processor and the peripheral devices of the product with multi-screen display function applying the multi-screen display system according to the present application, thereby reducing the cost of the product with multi-screen display function and reducing the volume of the product with multi-screen display function. In addition, the multi-screen display system can also send the effective data time including the 1 st vertical effective data time to the n th vertical effective data time and the 1 st horizontal effective data time and the n th horizontal effective data time through the processor, so that each of the n display devices can respectively capture the corresponding vertical image data and the horizontal image data through the effective data time corresponding to the data enabling signal, thereby realizing the technical effect that one processor controls a plurality of display devices.
Although the drawings of the present application include the above-described components, it is not excluded that many other additional components may be used to achieve the best technical result without violating the spirit of the present application.
While the invention has been illustrated by the above examples, it should be noted that the description is not intended to limit the invention. On the contrary, this invention covers modifications and similar arrangements apparent to those skilled in the art. Therefore, the scope of the claims is to be accorded the broadest interpretation so as to encompass all such obvious modifications and similar arrangements.
Claims (4)
1. A multi-screen display system, comprising:
n display devices, wherein N is a positive integer greater than or equal to two, and
The processor comprises a plurality of system data pins, wherein the system data pins are divided into N groups of data pin groups, one pin number of the N group of data pin groups corresponds to the display color gradation number of the N display device, and the N group of data pin groups are used for outputting horizontal image data and vertical image data of the N display device;
The N display device captures the horizontal image data output by the N group of data pin groups in a horizontal effective time section, and captures the vertical image data output by the N group of data pin groups in a vertical effective time section;
the processor is configured to output a vertical synchronization signal, a horizontal synchronization signal, and a clock signal to the N display devices, so that the N display device captures the horizontal image data output by the N data pin group in the horizontal effective time zone according to the clock signal and the horizontal synchronization signal, and captures the vertical image data output by the N data pin group in the vertical effective time zone according to the horizontal synchronization signal and the vertical synchronization signal.
2. The system of claim 1, wherein the nth display device does not capture the horizontal image data output by the nth set of data pins according to the clock signal and the horizontal synchronization signal in a horizontal back-porch time segment and a horizontal front-porch time segment, the horizontal effective time segment being between the horizontal back-porch time segment and the horizontal front-porch time segment, a sum of the horizontal effective time segment, the horizontal back-porch time segment and the horizontal front-porch time segment being one horizontal scan period, the horizontal back-porch time segment being a time segment between a trailing edge of a last pulse of the horizontal synchronization signal and a beginning of outputting horizontal effective data, the horizontal front-porch time segment being a time segment between a trailing edge of a current pulse of the horizontal synchronization signal from an ending of the horizontal effective data, the horizontal effective data being data output by each set of data pins in the horizontal effective time segment.
3. The system of claim 1, wherein the nth display device does not capture the vertical image data output by the nth group of data pins according to the horizontal synchronization signal and the vertical synchronization signal in a vertical back-porch time section and a vertical front-porch time section, the vertical effective time section is located between the vertical back-porch time section and the vertical front-porch time section, the sum of the vertical effective time section, the vertical back-porch time section and the vertical front-porch time section is one vertical scanning period, and the vertical back-porch time section is a time section from a back edge of a last pulse of the horizontal synchronization signal to a start of outputting vertical effective data, the vertical front-porch time section is a time section between a back edge of a current pulse of the horizontal synchronization signal from an end of the vertical effective data, and the vertical effective data is data output by each group of data pins in the vertical effective time section.
4. The multi-screen display system of claim 1, wherein when the pin numbers of any two of the N sets of data pin groups are the same, the resolutions of the display devices to which the any two sets of data pin groups are correspondingly connected are the same.
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