CN114744011A - Spliced display screen - Google Patents
Spliced display screen Download PDFInfo
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- CN114744011A CN114744011A CN202210315035.9A CN202210315035A CN114744011A CN 114744011 A CN114744011 A CN 114744011A CN 202210315035 A CN202210315035 A CN 202210315035A CN 114744011 A CN114744011 A CN 114744011A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
- G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/18—Tiled displays
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the application discloses tiled display screen includes: the display panel comprises a substrate, a wiring layer and a thin film transistor array layer, wherein the wiring layer is arranged on the substrate, the thin film transistor array layer is arranged on the substrate and the wiring layer, the wiring layer comprises a first bonding pad and a second bonding pad arranged at an interval with the first bonding pad, the first bonding pad protrudes out of the thin film transistor array layer and the second bonding pad protrudes out of the substrate in the lateral direction of the display panel, the binding surface of the first bonding pad and the binding surface of the second bonding pad face opposite in direction, and the first bonding pad and the second bonding pad are bound and connected in two adjacent display panels; the structures of the first bonding pad and the second bonding pad are matched with each other, so that the height difference when the display panel is spliced can be reduced, the thickness of the spliced display screen is further reduced, and gaps among the spliced display screens can also be reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to a spliced display screen.
Background
In the prior art, for large-size OLED splicing display, splicing screens are spliced in a stacking mode, and height difference exists among the screens. Or the mother-son boards are spliced, so that the structure is more complex.
Disclosure of Invention
The embodiment of the application provides a tiled display screen, and in display panel's side orientation, first pad salient thin film transistor array layer, second pad protrusion the orientation of basement, the binding face of first pad and the binding face of second pad is opposite, and the structure of first pad and second pad is mutually supported, height drop when reducing the display panel concatenation, and then reduces tiled display screen thickness.
The embodiment of the application provides a tiled display screen, include: the display panel comprises at least two display panels, wherein the two display panels are spliced; the display panel comprises a substrate, a wiring layer and a thin film transistor array layer, wherein the wiring layer is arranged on the substrate, and the thin film transistor array layer is arranged on the substrate and the wiring layer; the wiring layer comprises a first bonding pad and a second bonding pad arranged at an interval with the first bonding pad;
in a side direction of the display panel, the first pad protrudes out of the thin film transistor array layer, the second pad protrudes out of the substrate, and a binding face of the first pad is opposite to a binding face of the second pad in orientation;
in two adjacent display panels, the first bonding pad is bonded and connected with the second bonding pad.
Optionally, in some embodiments of the present application, in a peripheral side direction of the display panel, the first pad is connected to the substrate and protrudes from the thin film transistor array layer, and the second pad is connected to the thin film crystal layer and protrudes from the substrate.
Optionally, in some embodiments of the present application, the thin film transistor array layer includes a signal line connected to the first pad and the second pad.
Optionally, in some embodiments of the present application, the signal line includes at least one of a scan line, a data line, a power signal line, and a clock signal line.
Optionally, in some embodiments of the present application, the first pad and the second pad are bonded and connected through a conductive material.
Optionally, in some embodiments of the present application, the first pad and the second pad are physically overlapped.
Optionally, in some embodiments of the present application, two adjacent display panels are spliced to form a seam, and a sealant is filled in the seam.
Optionally, in some embodiments of the present application, the refractive index of the sealant is greater than the refractive index of the transparent film layer in the thin film transistor array layer.
Optionally, in some embodiments of the present application, the display panel further includes a light emitting device disposed on and electrically connected to the thin film transistor array layer; the thin film transistor array layer further includes:
a buffer layer disposed on the substrate;
a first insulating layer disposed on the buffer layer;
a semiconductor layer disposed on the first insulating layer;
a second insulating layer disposed on the first insulating layer and covering the semiconductor layer;
a gate metal layer disposed on the second insulating layer; the grid metal layer comprises a scanning line and a grid;
a third insulating layer disposed on the second insulating layer and covering the gate electrode;
an interlayer dielectric layer disposed on the third insulating layer;
the source and drain metal layer is arranged on the interlayer dielectric layer and comprises a data line and a source and drain electrode;
a planarization layer disposed on the interlayer dielectric layer;
the light emitting device is disposed on the planarization layer.
Optionally, in some embodiments of the present application, the routing layer includes a power signal line; the power signal line is connected to the first pad and the second pad, and a portion of the power signal line blocks the semiconductor layer.
This application embodiment, through the side at display panel upwards, first pad salient thin film transistor array layer, the second pad is salient the orientation of the face of binding of base, first pad and second pad is opposite, and the structure of first pad and second pad is mutually supported, and the height drop when both can reducing the display panel concatenation reduces tiled display screen thickness, also can reduce the gap between the tiled display screen.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a tiled display screen according to an embodiment of the present application;
FIG. 2 is a schematic top view of a display panel provided in the present application;
FIG. 3 is a schematic top view of a tiled display screen provided herein;
fig. 4 is a schematic structural diagram of a display panel and a first pad provided in the present application;
fig. 5 is a schematic structural diagram of a display panel and a second pad provided in the present application;
fig. 6 is a schematic structural diagram of a tiled display screen according to a second embodiment of the present application.
Description of reference numerals: the display panel comprises a tiled display screen 200, a display panel 100, a substrate 10, a wiring layer 20, a first bonding pad 201, a second bonding pad 202, a thin film transistor array layer 30, a buffer layer 301, a first insulating layer 302, a semiconductor layer 303, a second insulating layer 304, a gate metal layer 305, a gate 305a, a third insulating layer 306, an interlayer dielectric layer 307, a source-drain metal layer 308, a source-drain 308a, a planarization layer 309, a light-emitting device 40, an anode 401, a light-emitting layer 402, a cathode 403, a pixel definition layer 404, a sealant 50, a seam 60 and a conductive material 70.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides a display panel and a spliced display screen, which are explained in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
The first embodiment,
Referring to fig. 1, fig. 2 and fig. 3, an embodiment of the present application provides a tiled display screen 200, including: at least two display panels 100, the two display panels 100 are arranged in a splicing manner. The display panel 100 includes a substrate 10, a routing layer 20, and a thin film transistor array layer 30, the routing layer 20 being disposed on the substrate 10, and the thin film transistor array layer 30 being disposed on the substrate 10 and the routing layer 20. The routing layer 20 includes a first pad 201 and a second pad 202 spaced apart from the first pad 201. In the lateral direction of the display panel 100, the first pad 201 protrudes from the thin film transistor array layer 30, the second pad 202 protrudes from the substrate 10, and the bonding face of the first pad 201 is opposite to the bonding face of the second pad 202. In two adjacent display panels 100, the first bonding pad 201 of one display panel 100 is connected to the second bonding pad 202 of the other display panel 100 in a bonding manner.
It can be understood that, in this embodiment, in the lateral direction of the display panel 100, the first pad 201 protrudes from the thin film transistor array layer 30, the second pad 202 protrudes from the substrate 10, the binding surface of the first pad 201 and the binding surface of the second pad 202 face opposite directions, and the structures of the first pad 201 and the second pad 202 are matched with each other, so that the height difference when the display panel 100 is spliced can be reduced, the thickness of the tiled display screen 200 can be reduced, and the gap between the tiled display screens 200 can also be reduced.
Referring to fig. 1, in the circumferential direction of the display panel 100, a first pad 201 is connected to the substrate 10 and protrudes from the thin film transistor array layer 30, and a second pad 202 is connected to the thin film transistor array layer and protrudes from the substrate 10.
It can be understood that, in this embodiment, by designing the first pad 201 to be connected to the substrate 10 and the protruding tft array layer 30 and the second pad 202 to be connected to the thin film transistor array layer and protrude from the substrate 10, a mutually-matched splicing structure is formed between the two display panels 100, so that the first pad 201 and the second pad 202 are both located in the display area of the spliced display panel 200 after the display panels 100 are spliced, and the display effect is improved.
The thin film transistor array layer 30 includes signal lines (not shown in the drawings) connected to the first pad 201 and the second pad 202.
It is understood that in the present embodiment, the signal line is electrically connected to the first pad 201 and the second pad 202, and the thin film transistor array layer 30 controls the display effect of the display panel 100 through the first pad 201 and the second pad 202.
The signal lines include at least one of a scan line, a data line, a power signal line 203, and a clock signal line.
It can be understood that, in the present embodiment, the tiled display screen 200 implements the scanning, data communication, power supply and timing control functions through the scanning lines, the data lines, the power signal lines 203 and the clock signal lines.
Referring to fig. 1, the first pad 201 and the second pad 202 are bonded and connected by the conductive material 70.
It is understood that the first pad 201 and the second pad 202 are bound and connected by the conductive material 70, and optionally, the conductive material 70 includes conductive paste, solder paste, and the like. The bonding of the first pad 201 and the second pad 202 is realized by the conductive material 70, and the stability between the first pad 201 and the second pad 202 is ensured.
In some embodiments, the first pad 201 and the second pad 202 may also be bond bindings.
Referring to fig. 1, two adjacent display panels 100 are spliced to form a seam 60, and the seam 60 is filled with a sealant 50.
It can be understood that, because the joints 60 inevitably occur in the joints between the display panels 100, the display effect is affected, and the sealant 50 is filled between the joints 60, on one hand, the firmness of the joints of the display panels 100 can be improved, and on the other hand, the effect of sealing the display panels 100 can be achieved. Optionally, a desiccant is doped in the sealant 50 to improve the water and oxygen resistance of the display panel 100. Optionally, the desiccant comprises anhydrous calcium chloride, magnesium chloride or silica gel.
The refractive index of the sealant 50 is greater than the refractive index of the transparent film layer in the thin film transistor array layer 30.
It is understood that, in the present embodiment, due to the existence of the seam 60, it is inevitable that light is exposed from the seam 60 of the display panel 100. When light enters from the light-sparse medium to the light-dense medium, two phenomena of refraction and reflection occur in the medium layer. Therefore, the refractive index of the sealant 50 is set to be greater than that of the transparent film layer in the thin film transistor array layer 30, so that the reflection effect of the sealant 50 is improved, and more light rays are prevented from being exposed from the abutted seams 60. It is understood that the transparent film layers in the thin film transistor array layer 30 include: a first insulating layer 302, a second insulating layer 304, a third insulating layer 306, or a planarization layer 309.
Referring to fig. 4 and 5, the display panel 100 further includes a light emitting device 40, and the light emitting device 40 is disposed on the thin film transistor array layer 30 and electrically connected to the thin film transistor array layer 30. The thin film transistor array layer 30 further includes: a buffer layer 301, a first insulating layer 302, a semiconductor layer 303, a second insulating layer, a gate metal layer 305, a third insulating layer 306, an interlayer dielectric layer 307, a source/drain metal layer 308, and a planarization layer 309. The buffer layer 301 is disposed on the substrate 10. The first insulating layer 302 is disposed on the buffer layer 301. A semiconductor layer 303 is provided on the first insulating layer 302. The second insulating layer is provided over the first insulating layer 302 and covers the semiconductor layer 303. A gate metal layer 305 is disposed on the second insulating layer. The gate metal layer 305 includes a scan line (not shown in the drawing) and a gate 305 a. A third insulating layer 306 is disposed on the second insulating layer and covers the gate 305 a. An interlayer dielectric layer 307 is disposed on the third insulating layer 306. A source-drain metal layer 308 is disposed on the interlayer dielectric layer 307, and the source-drain metal layer 308 includes a data line (not shown in the drawing) and a source-drain 308 a. A planarization layer 309 is disposed on the interlayer dielectric layer 307. The light emitting device 40 is disposed on the planarization layer 309.
It is to be understood that, in the present embodiment, the light emitting device 40 includes an anode 401, a light emitting layer 402, a cathode 403, and a pixel defining layer 404. The anode 401 is disposed on the planarization layer 309 and electrically connected to the thin film transistor array layer 30. A light emitting layer 402 is disposed on the anode 401. The cathode 403 is disposed on the light emitting functional layer. The pixel defining layer 404 is disposed on the planarization layer 309, and surrounds the anode 401, the light emitting layer 402, and the cathode 403. The light emitting device 40 may be a submillimeter-scale light emitting diode or a micro light emitting diode.
Referring to fig. 4 and 5, the wiring layer 20 includes a power signal line 203. The power supply signal line 203 is connected to the first pad 201 and the second pad 202, and a portion of the power supply signal line 203 shields the semiconductor layer 303.
It is to be understood that, in the present embodiment, the power signal line 203 is made of a light-impermeable conductive material. Optionally, the opaque metal comprises copper, aluminum, iron, or an alloy.
Example II,
Referring to fig. 2, fig. 3 and fig. 6, an embodiment of the present application provides a tiled display screen 200, including: at least two display panels 100, the two display panels 100 are arranged in a splicing manner. The display panel 100 includes a substrate 10, a routing layer 20, and a thin film transistor array layer 30, the routing layer 20 being disposed on the substrate 10, and the thin film transistor array layer 30 being disposed on the substrate 10 and the routing layer 20. The wiring layer 20 includes a first pad 201 and a second pad 202 disposed spaced apart from the first pad 201. In the side direction of the display panel 100, the first pad 201 protrudes from the thin film transistor array layer 30, the second pad 202 protrudes from the substrate 10, and the binding face of the first pad 201 is opposite to the binding face of the second pad 202. In two adjacent display panels 100, the first pad 201 of one display panel 100 is connected to the second pad 202 of the other display panel 100 in a bonding manner.
It can be understood that, in this embodiment, in the lateral direction of the display panel 100, the first pad 201 protrudes from the thin film transistor array layer 30, the second pad 202 protrudes from the substrate 10, the binding surface of the first pad 201 and the binding surface of the second pad 202 face opposite directions, and the structures of the first pad 201 and the second pad 202 are matched with each other, so that the height difference when the display panel 100 is spliced can be reduced, the thickness of the tiled display screen 200 can be reduced, and the gap between the tiled display screens 200 can also be reduced.
Referring to fig. 6, in the circumferential direction of the display panel 100, a first pad 201 is connected to the substrate 10 and protrudes from the thin film transistor array layer 30, and a second pad 202 is connected to the thin film transistor array layer and protrudes from the substrate 10.
It can be understood that, in this embodiment, by designing the first pad 201 to be connected to the substrate 10 and the protruding tft array layer 30 and the second pad 202 to be connected to the thin film transistor array layer and protrude from the substrate 10, a mutually-matched splicing structure is formed between the two display panels 100, so that the first pad 201 and the second pad 202 are both located in the display area of the spliced display panel 200 after the display panels 100 are spliced, and the display effect is improved.
The thin film transistor array layer 30 includes signal lines (not shown in the drawings) connected to the first pad 201 and the second pad 202.
It is understood that in the present embodiment, the signal line is electrically connected to the first pad 201 and the second pad 202, and the thin film transistor array layer 30 controls the display effect of the display panel 100 through the first pad 201 and the second pad 202.
The signal lines include at least one of a scan line, a data line, a power supply signal line 203, and a clock signal line.
It can be understood that, in the present embodiment, the tiled display screen 200 implements the scanning, data communication, power supply and timing control functions through the scanning lines, the data lines, the power signal lines 203 and the clock signal lines.
Referring to fig. 6, the first pad 201 and the second pad 202 are physically overlapped.
It is understood that in the present embodiment, the bonding is achieved by physically overlapping the first pad 201 and the second pad 202. The adhesion between the first pads 201 and the second pads 202 is relatively small, and when a problem occurs in the single display panel 100, the single display panel 100 can be replaced by cutting along the seams 60 between the display panels 100. In this way, when the display panel 100 is replaced, the structures of the first bonding pad 201 and the second bonding pad 202 are not damaged.
In some embodiments, the first pad 201 and the second pad 202 may also be bond bindings.
Referring to fig. 6, two adjacent display panels 100 are spliced to form a seam 60, and the seam 60 is filled with a sealant 50.
It can be understood that, because the joints 60 inevitably occur in the joints between the display panels 100, the display effect is affected, and the sealant 50 is filled between the joints 60, on one hand, the firmness of the joints of the display panels 100 can be improved, and on the other hand, the effect of sealing the display panels 100 can be achieved. Optionally, a desiccant is doped in the sealant 50 to improve the water and oxygen resistance of the display panel 100. Optionally, the desiccant comprises anhydrous calcium chloride, magnesium chloride or silica gel.
The refractive index of the sealant 50 is greater than the refractive index of the transparent film layer in the thin film transistor array layer 30.
It is understood that, in the present embodiment, due to the existence of the seam 60, it is inevitable that light is exposed from the seam 60 of the display panel 100. When light enters from the light-sparse medium to the light-dense medium, two phenomena of refraction and reflection occur in the medium layer. Therefore, the refractive index of the sealant 50 is larger than that of the transparent film layer in the thin film transistor array layer 30, the reflection effect of the sealant 50 is improved, and more light rays are prevented from being exposed from the abutted seams 60. It is understood that the transparent film layers in the thin film transistor array layer 30 include: a first insulating layer 302, a second insulating layer 304, a third insulating layer 306, or a planarization layer 309.
Referring to fig. 4 and 5, the display panel 100 further includes a light emitting device 40, and the light emitting device 40 is disposed on the thin film transistor array layer 30 and electrically connected to the thin film transistor array layer 30. The thin film transistor array layer 30 further includes: a buffer layer 301, a first insulating layer 302, a semiconductor layer 303, a second insulating layer, a gate metal layer 305, a third insulating layer 306, an interlayer dielectric layer 307, a source-drain metal layer 308, and a planarization layer 309. The buffer layer 301 is disposed on the substrate 10. The first insulating layer 302 is disposed on the buffer layer 301. A semiconductor layer 303 is provided on the first insulating layer 302. The second insulating layer is provided over the first insulating layer 302 and covers the semiconductor layer 303. A gate metal layer 305 is disposed on the second insulating layer. The gate metal layer 305 includes a scan line (not shown in the drawing) and a gate 305 a. A third insulating layer 306 is disposed on the second insulating layer and covers the gate 305 a. An interlayer dielectric layer 307 is disposed on the third insulating layer 306. A source drain metal layer 308 is disposed on the interlayer dielectric layer 307, and the source drain metal layer 308 includes a data line (not shown in the figure) and a source drain 308 a. A planarization layer 309 is disposed on the interlayer dielectric layer 307. The light emitting device 40 is disposed on the planarization layer 309.
It is to be understood that, in the present embodiment, the light emitting device 40 includes an anode 401, a light emitting layer 402, a cathode 403, and a pixel defining layer 404. The anode 401 is disposed on the planarization layer 309 and electrically connected to the thin film transistor array layer 30. A light emitting layer 402 is disposed on the anode 401. The cathode 403 is disposed on the light emitting functional layer. The pixel defining layer 404 is disposed on the planarization layer 309, and is disposed around the anode 401, the light emitting layer 402, and the cathode 403. The light emitting device 40 may be a submillimeter-scale light emitting diode or a micro light emitting diode.
Referring to fig. 6, the wiring layer 20 includes a power signal line 203. The power supply signal line 203 is connected to the first pad 201 and the second pad 202, and a portion of the power supply signal line 203 shields the semiconductor layer 303.
It is to be understood that, in the present embodiment, the power signal line 203 is made of a light-impermeable conductive material. Optionally, the opaque metal comprises copper, aluminum, iron, or an alloy.
The embodiment of the present application provides a tiled display screen, and the principle and the implementation of the present application are described herein by applying specific examples, and the description of the embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A tiled display screen, comprising: the display panel comprises at least two display panels, wherein the two display panels are spliced; the display panel comprises a substrate, a wiring layer and a thin film transistor array layer, wherein the wiring layer is arranged on the substrate, and the thin film transistor array layer is arranged on the substrate and the wiring layer; the wiring layer comprises a first bonding pad and a second bonding pad arranged at an interval with the first bonding pad;
in a side direction of the display panel, the first pad protrudes out of the thin film transistor array layer, the second pad protrudes out of the substrate, and a binding face of the first pad is opposite to a binding face of the second pad in orientation;
in two adjacent display panels, the first bonding pad of one display panel is connected with the second bonding pad of the other display panel in a binding manner.
2. The tiled display screen of claim 1, wherein the first pads are connected to the substrate and protrude from the thin film transistor array layer and the second pads are connected to the thin film crystal layer and protrude from the substrate in a peripheral side direction of the display panel.
3. The tiled display screen of claim 2, wherein the thin film transistor array layer includes signal lines connected to the first and second pads.
4. The tiled display screen of claim 3, wherein the signal lines comprise at least one of scan lines, data lines, power signal lines, and clock signal lines.
5. The tiled display screen of claim 1, wherein the first bonding pad and the second bonding pad are bonded and connected through a conductive material.
6. The tiled display screen of claim 1, wherein the first bonding pad physically overlaps the second bonding pad.
7. The spliced display screen of claim 5, wherein adjacent two display panels are spliced to form a splice, and a sealant is filled in the splice.
8. The tiled display screen of claim 7, wherein the sealant has a refractive index greater than the refractive index of the transparent film layer in the thin film transistor array layer.
9. The tiled display screen of claim 2, wherein the display panel further comprises a light emitting device disposed on and electrically connected to the thin film transistor array layer; the thin film transistor array layer further includes:
a buffer layer disposed on the substrate;
a first insulating layer disposed on the buffer layer;
a semiconductor layer disposed on the first insulating layer;
a second insulating layer disposed on the first insulating layer and covering the semiconductor layer;
a gate metal layer disposed on the second insulating layer; the grid metal layer comprises a scanning line and a grid;
a third insulating layer disposed on the second insulating layer and covering the gate electrode;
an interlayer dielectric layer disposed on the third insulating layer;
the source and drain metal layer is arranged on the interlayer dielectric layer and comprises a data line and a source and drain electrode;
a planarization layer disposed on the interlayer dielectric layer;
the light emitting device is disposed on the planarization layer.
10. The tiled display screen of claim 9, wherein the trace layer includes power signal lines; the power signal line is connected to the first pad and the second pad, and a portion of the power signal line blocks the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210315035.9A CN114744011A (en) | 2022-03-28 | 2022-03-28 | Spliced display screen |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210315035.9A CN114744011A (en) | 2022-03-28 | 2022-03-28 | Spliced display screen |
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| Publication Number | Publication Date |
|---|---|
| CN114744011A true CN114744011A (en) | 2022-07-12 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210315035.9A Pending CN114744011A (en) | 2022-03-28 | 2022-03-28 | Spliced display screen |
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| CN (1) | CN114744011A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115035809A (en) * | 2022-07-15 | 2022-09-09 | 惠州中京电子科技有限公司 | Method for eliminating dark lines in splicing area of LED (light emitting diode) board |
| CN115273678A (en) * | 2022-07-29 | 2022-11-01 | 武汉天马微电子有限公司 | Display panel and display device |
-
2022
- 2022-03-28 CN CN202210315035.9A patent/CN114744011A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115035809A (en) * | 2022-07-15 | 2022-09-09 | 惠州中京电子科技有限公司 | Method for eliminating dark lines in splicing area of LED (light emitting diode) board |
| CN115035809B (en) * | 2022-07-15 | 2023-11-10 | 惠州中京电子科技有限公司 | Method for eliminating dark lines in spliced area of LED (light-emitting diode) board |
| CN115273678A (en) * | 2022-07-29 | 2022-11-01 | 武汉天马微电子有限公司 | Display panel and display device |
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