CN114496986A - Ultra-wideband wafer level packaging matching structure - Google Patents

Ultra-wideband wafer level packaging matching structure Download PDF

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Publication number
CN114496986A
CN114496986A CN202210123804.5A CN202210123804A CN114496986A CN 114496986 A CN114496986 A CN 114496986A CN 202210123804 A CN202210123804 A CN 202210123804A CN 114496986 A CN114496986 A CN 114496986A
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chip
passivation layer
rdl
ubm
pcb
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王璞
刘强
郭齐
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Chengdu Tiancheng Dianke Technology Co ltd
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Chengdu Tiancheng Dianke Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application relates to an ultra wide band wafer level encapsulation matching structure, include: chip wafer level encapsulation part and PCB part, chip wafer level encapsulation part includes: the chip package comprises a package substrate, a chip, a first passivation layer, an RDL, a second passivation layer, a UBM and a solder ball. The chip includes: a functional surface, a bottom surface and a chip bonding pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed; the first passivation layer includes: a first passivation layer metal via; the first passivation layer is arranged on the outer side of the functional surface of the chip, and the center of the metal through hole of the first passivation layer is aligned with the center of the bonding pad of the chip; the RDL comprises: the RDL signal line and the RDL metal are grounded; the RDL is arranged outside the first passivation layer; the UBM includes: a signal UBM and a ground UBM; the UBM is arranged in the second passivation layer; the second passivation layer is arranged outside the RDL; the chip is vertically interconnected with the PCB part through the solder balls; and the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer metalized through hole and the signal UBM.

Description

Ultra-wideband wafer level packaging matching structure
Technical Field
The application relates to the technical field of chip packaging, in particular to an ultra-wideband wafer level packaging matching structure.
Background
With the continuous progress of semiconductor technology, various radio devices are developed toward high frequency and miniaturization, and the integrated chip industry is also under active development, and various packages for chips have become preferable in order to meet the requirements of high integration, high reliability, low cost and easy assembly. Wafer Level Package (WLP) has the characteristics of stable chip unit, high integration Level, strong reliability, good mechanical protection and high cost performance, and therefore, the WLP can meet the packaging requirements in the industry, and becomes the mainstream technology of current IC chip packaging. Wafer level packaging is generally defined as a packaging form in which most or all process steps for forming a package body are completed on an intact wafer which is not diced, and is different from a traditional flow of a test of cutting first and then packaging, a series of packaging flows such as packaging, bump preparation and the like are directly performed on a wafer which finishes a previous flow of wafer preparation. Products prepared by wafer level packaging technology, such as processors, sensors, communication modules, and the like, have gained importance in the market. Wafer-packaged chip ports are mainly vertically bonded to a Circuit Board (PCB) substrate through Ball Grid Array (BGA) solder balls to realize three-dimensional vertical interconnection. The chip and the PCB are interconnected through the solder balls, the problems of signal leakage, reflection and the like do not need to be considered too much in the low frequency process, however, in the prior art, the packaging of the radio frequency chip with high speed and high resolution is continuously improved, when the frequency reaches the millimeter wave level, the mismatch between the impedance of the solder balls and the impedance on the PCB is not negligible, the mismatch can cause the reflection of the radio frequency signals seriously, and further the quality of transmission signals is damaged.
Disclosure of Invention
In order to overcome the problem that in the related art, the radio frequency signal is reflected due to serious impedance mismatch to further damage the quality of a transmission signal at least to a certain extent, the application provides an ultra-wideband wafer level packaging matching structure.
The scheme of the application is as follows:
an ultra-wideband wafer-level package matching structure, comprising:
a chip wafer level package portion and a PCB portion;
the chip wafer level package part comprises: a package substrate, a chip, a first passivation Layer, a Redistribution Layer (RDL), a second passivation Layer, an Under Bump Metal (UBM) Layer, and solder balls;
the chip includes: a functional surface, a bottom surface and a chip bonding pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed;
the first passivation layer includes: a first passivation layer metal via; the first passivation layer is arranged on the outer side of the functional surface of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad;
the RDL comprises: the RDL signal line and the RDL metal are grounded; the RDL is arranged outside the first passivation layer;
the UBM includes: a signal UBM and a ground UBM; the UBM is disposed in the second passivation layer;
the second passivation layer is disposed outside the RDL;
the chips are vertically interconnected with the PCB parts through the solder balls;
and the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer metalized through hole and the signal UBM.
Preferably, in an implementable manner of the present application, the PCB section comprises: the PCB comprises a PCB bonding pad, a high-resistance line, a Klopfenstein gradient line, a microstrip line and a dielectric substrate;
the PCB bonding pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line are arranged on the dielectric substrate;
the chips are vertically interconnected with the PCB bonding pads through the solder balls;
the PCB bonding pad is connected with the high-resistance wire;
the Klopfenstein gradient line is respectively connected with the high-resistance line and the microstrip line.
Preferably, in an implementable manner of the present application, the RDL metal ground symmetry is split on both sides of the RDL signal line.
Preferably, in an implementable manner of the present application, the RDL metal ground is provided with an opening avoidance above the microstrip line; the size of the opening avoiding is adjustable.
Preferably, in an achievable form of the present application, the radius of the opening relief compared to the radius of the UBM is 1.5: 1.
Preferably, in an implementable manner of the present application, the comparison of the radius of the solder ball to the radius of the UBM is 0.8: 1;
the comparison relationship between the radius of the PCB welding pad and the radius of the welding ball is 1.2: 1.
Preferably, in an implementable manner of the present application, the ground UBM is distributed coaxially around the signal UBM.
Preferably, in an implementable manner of the present application, the solder ball includes: a signal solder ball and a ground solder ball;
the grounding solder balls are distributed around the signal solder balls in a similar coaxial manner.
Preferably, in an implementable manner of the present application, the dielectric substrate comprises: the surface layer of the substrate and the bottom metal grounding layer; the surface layer of the substrate is arranged on two sides of the PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line, and gaps are formed for avoiding.
Preferably, in an implementable manner of the present application, the size of the matching section has a preset correspondence with the parameter of the Klopfenstein gradient.
The technical scheme provided by the application can comprise the following beneficial effects: the ultra wide band wafer level encapsulation matching structure in this application includes: chip wafer level encapsulation part and PCB part, chip wafer level encapsulation part includes: the chip package comprises a package substrate, a chip, a first passivation layer, an RDL, a second passivation layer, a UBM and a solder ball. The chip includes: a functional surface, a bottom surface and a chip bonding pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed; the first passivation layer includes: a first passivation layer metal via; the first passivation layer is arranged on the outer side of the functional surface of the chip, and the center of the metal through hole of the first passivation layer is aligned with the center of the bonding pad of the chip; the RDL comprises: the RDL signal line and the RDL metal are grounded; the RDL is arranged outside the first passivation layer; the UBM includes: a signal UBM and a ground UBM; the UBM is arranged in the second passivation layer; the second passivation layer is arranged outside the RDL; the chip is vertically interconnected with the PCB part through the solder balls; and the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer metalized through hole and the signal UBM. In this application, because the RDL signal line is provided with the matching section, can adjust the impedance mismatch between first passivation layer metallization through-hole and the signal UBM to tentatively realize the impedance match between core pad to the UBM, promote signal transmission performance.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic structural diagram of an ultra-wideband wafer-level package matching structure according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a chip-on-wafer package portion of an ultra-wideband wafer-on-wafer package matching structure according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a PCB portion in an ultra-wideband wafer-level package matching structure according to an embodiment of the present application.
Reference numerals: chip wafer level package portion-100; a package substrate-110; a chip-120; a first passivation layer 131; a second passivation layer-132; RDL-140; functional side-150 of the chip; chip pad-152; UBM-160; solder ball-170; PCB portion-200; PCB pad-210; a high resistance line-220; klopfenstein gradient-230; microstrip line-240.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
An ultra-wideband wafer-level package matching structure, referring to fig. 1-2, comprising:
chip 120 wafer level package portion 100 and PCB portion 200;
the wafer level package portion 100 of the chip 120 includes: package substrate 110, chip 120, first passivation layer 131, RDL140, second passivation layer 132, UBM160, and solder balls 170;
the chip 120 includes: functional side, bottom side and die pad 152; the bottom surface of the chip 120 is embedded in the package substrate 110, and the functional surface 150 of the chip is exposed;
the first passivation layer 131 includes: a first passivation layer metal via; the first passivation layer 131 is arranged outside the functional surface 150 of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad 152;
RDL140 includes: the RDL signal line and the RDL metal are grounded; the RDL140 is disposed outside the first passivation layer 131;
the UBM160 includes: a signal UBM and a ground UBM; the UBM160 is disposed in the second passivation layer 132;
a second passivation layer 132 is disposed outside the RDL 140;
chip 120 is vertically interconnected with PCB section 200 by solder balls 170;
the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer 131 metalized via and the signal UBM.
The second passivation layer 132 in this embodiment is primarily used to protect the RDL140 layer.
The ultra-wideband wafer-level package matching structure in this embodiment includes: chip 120 wafer level package portion 100 and PCB portion 200, chip 120 wafer level package portion 100 comprising: package substrate 110, chip 120, first passivation layer 131, RDL140, second passivation layer 132, UBM160, and solder balls 170. The chip 120 includes: functional side, bottom side and die pad 152; the bottom surface of the chip 120 is embedded in the package substrate 110, and the functional surface 150 of the chip is exposed; the first passivation layer 131 includes: a first passivation layer metal via; the first passivation layer 131 is arranged outside the functional surface 150 of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad 152; RDL140 includes: the RDL signal line and the RDL metal are grounded; the RDL140 is disposed outside the first passivation layer 131; the UBM160 includes: a signal UBM and a ground UBM; UBM160 is disposed in second passivation layer 132; a second passivation layer 132 is disposed outside the RDL 140; chip 120 is vertically interconnected with PCB section 200 by solder balls 170; the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer 131 metalized via and the signal UBM. In this embodiment, since the RDL signal line is provided with the matching node, impedance mismatch between the first passivation layer 131 metallization through hole and the signal UBM can be adjusted, so that impedance matching between the core pad and the UBM160 is primarily achieved, and signal transmission performance is improved.
In some embodiments of the ultra-wideband wafer-level package matching structure, referring to fig. 3, the PCB portion 200 includes: a PCB pad 210, a high-resistance line 220, a Klopfenstein gradient line 230, a microstrip line 240 and a dielectric substrate;
the PCB pad 210, the high-resistance line 220, the Klopfenstein gradient line 230 and the microstrip line 240 are arranged on the dielectric substrate;
chip 120 is vertically interconnected by solder balls 170 and PCB pads 210;
the PCB pad 210 is connected with a high resistance wire 220;
the Klopfenstein transition line 230 is connected to the high resistance line 220 and the microstrip line 240, respectively.
Preferably, the PCB pad 210 may be, but is not limited to, a circular PCB pad 210.
Preferably, the microstrip line 240 may be, but is not limited to, a 50 ohm microstrip line.
The high resistance line 220 in this embodiment is used to match the capacitive effect brought by the PCB pad 210.
The Klopfenstein gradient line 230 is used for connecting the high-resistance line 220 and the 50-ohm microstrip line 240, and wide-band impedance transformation is realized.
Preferably, in this embodiment, the dielectric substrate is a rogers 3003 substrate with a thickness of 0.127mm, and the width of the corresponding microstrip line 240 is about 0.3 mm.
In some embodiments of the ultra-wideband wafer-level package matching structure, the RDL metal ground is symmetrically distributed on two sides of the RDL signal line.
In this embodiment, the RDL metal ground is symmetrically distributed on both sides of the RDL signal line to form a coplanar waveguide transmission line.
In the ultra-wideband wafer-level package matching structure in some embodiments, the RDL metal ground is provided with an opening above the microstrip line 240 for avoiding; the size of the opening avoiding is adjustable.
In this embodiment, the RDL metal ground is provided with an opening above the microstrip line 240 to avoid, so that the spatial radiation of the microstrip line 240 of the PCB portion 200 is not reflected, and the signal transmission performance is obviously improved.
Further, the comparison relationship between the radius of the opening avoidance and the radius of the UBM160 is 1.5: 1;
the radius of the solder ball 170 is compared to the radius of the UBM160 by 0.8: 1;
the radius of the PCB pad 210 is 1.2:1 compared to the radius of the solder ball 170.
Preferably, the radius of the UBM160 is 100 μm, the radius of the opening relief is 150 μm, the radius of the solder ball 170 is 125 μm, and the radius of the PCB pad 210 is 50 μm.
In some embodiments of the ultra-wideband wafer-level package matching structure, the ground UBMs are distributed around the signal UBM in a quasi-coaxial manner.
Further, the solder ball 170 includes: a signal solder ball and a ground solder ball;
the grounding solder balls are distributed around the signal solder balls in a similar coaxial manner.
In this embodiment, the UBM160 layer and the solder balls 170 are in an approximate distribution structure, and are used for interconnecting the RDL signal lines, the RDL metal ground and the solder balls 170.
The grounding solder balls are distributed around the signal solder balls in a similar coaxial manner, so that the signal can be greatly bound to prevent leakage, and the transmission characteristic of the signal is greatly improved in a millimeter wave frequency band.
The coaxial-like structure in this embodiment may be implemented with some changes for PCB processability, without the need for uniform distribution.
In this embodiment, the chip 120 is soldered to the PCB pad 210 by a signal solder ball.
In some embodiments, the ultra-wideband wafer-level package matching structure includes: the surface layer and the bottom metal grounding layer of the substrate; the substrate surface layer is arranged on two sides of the PCB pad 210, the high-resistance line 220, the Klopfenstein gradient line 230 and the microstrip line 240, and a gap is formed for avoiding.
Preferably, referring to fig. 3, the substrate surface layer of the PCB pad 210 has a yielding radius of 300 μm; the avoiding distance from the surface layer of the substrate to the axis 2 is 400 mu m; the high resistance line 220 has a length of 200 μm and a width of 150 μm.
In some embodiments of the ultra-wideband wafer-level package matching structure, the size of the matching node has a predetermined corresponding relationship with the parameters of the Klopfenstein gradient 230.
Specifically, the calculation formula of the size of Klopfenstein gradient 230 is as follows:
Figure BDA0003499508790000081
Figure BDA0003499508790000082
Figure BDA0003499508790000083
Figure BDA0003499508790000084
wherein, ZLAnd Z0Load impedance and source impedance, I, of the respective transitions1(x) Is a modified Bessel function, ΓmIs the maximum reflection coefficient within the pass band. In practical design, the N-section impedance matching section converter is infinitely close to the Klopfenstein conical line when given ZL、Z0N and gammamThe desired Klopfenstein gradient 230 size can then be accurately determined by MATLAB programming.
Preferably, N is set to 20, Γ in this embodimentmAt 30dB, a detailed impedance profile was developed by MATLAB programming based on the above formula, and the length of the final Klopfenstein gradient 230 was approximately 700 μm.
In this embodiment, Klopfenstein gradient 230 defines the maximum reflectance specification within the pass band, Klopfenstein gradient 230 may give the shortest matching section.
In summary, in the ultra-wideband wafer-level package matching structure in this embodiment, by providing the matching sections on the RDL140 layer, adjusting the opening avoiding radius of the RDL metal ground, providing the solder balls 170 distributed coaxially, and providing the high-resistance line 220Klopfenstein tapered gradient on the PCB, the parasitic effect caused by the solder ball 170 interconnection structure is greatly improved, and the broadband matching is realized through the impedance gradient, which is compared with the conventional quarter-wavelength impedance transformation section matching structure.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that, in the description of the present application, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present application, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and the scope of the preferred embodiments of the present application includes other implementations in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (10)

1. An ultra-wideband wafer-level package matching structure, comprising:
a chip wafer level package portion and a PCB portion;
the chip wafer level package part comprises: the chip packaging structure comprises a packaging substrate, a chip, a first passivation layer, an RDL, a second passivation layer, an UBM and a welding ball;
the chip includes: a functional surface, a bottom surface and a chip bonding pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed;
the first passivation layer includes: a first passivation layer metal via; the first passivation layer is arranged on the outer side of the functional surface of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip bonding pad;
the RDL comprises: the RDL signal line and the RDL metal are grounded; the RDL is arranged outside the first passivation layer;
the UBM includes: a signal UBM and a ground UBM; the UBM is disposed in the second passivation layer;
the second passivation layer is disposed outside the RDL;
the chips are vertically interconnected with the PCB parts through the solder balls;
and the RDL signal line is provided with a matching node for adjusting impedance mismatch between the first passivation layer metalized through hole and the signal UBM.
2. The ultra-wideband wafer-level package matching structure of claim 1, wherein the PCB portion comprises: the PCB comprises a PCB bonding pad, a high-resistance line, a Klopfenstein gradient line, a microstrip line and a dielectric substrate;
the PCB bonding pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line are arranged on the dielectric substrate;
the chips are vertically interconnected with the PCB bonding pads through the solder balls;
the PCB bonding pad is connected with the high-resistance wire;
the Klopfenstein gradient line is respectively connected with the high-resistance line and the microstrip line.
3. The ultra-wideband wafer level package matching structure of claim 1, wherein the RDL metal ground symmetry subdivisions are on both sides of the RDL signal line.
4. The ultra-wideband wafer-level package matching structure of claim 2, wherein the RDL metal ground is provided with an opening relief above the microstrip line; the size of the opening avoiding is adjustable.
5. The matching structure of claim 4, wherein a comparison of a radius of the opening relief and a radius of the UBM is 1.5: 1.
6. The ultra-wideband wafer-level package matching structure of claim 2, wherein a comparison of a radius of the solder ball and a radius of the UBM is 0.8: 1;
the comparison relationship between the radius of the PCB welding pad and the radius of the welding ball is 1.2: 1.
7. The ultra-wideband wafer-level package matching structure of claim 1, wherein the ground UBMs are distributed coaxially around the signal UBM.
8. The ultra-wideband wafer-level package matching structure of claim 1, wherein the solder balls comprise: a signal solder ball and a ground solder ball;
the grounding solder balls are distributed around the signal solder balls in a similar coaxial manner.
9. The ultra-wideband wafer-level package matching structure of claim 2, wherein the dielectric substrate comprises: the surface layer and the bottom metal grounding layer of the substrate; the surface layer of the substrate is arranged on two sides of the PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line, and gaps are formed for avoiding.
10. The matching structure of claim 2, wherein the size of the matching section has a preset corresponding relationship with the parameter of the Klopfenstein gradient.
CN202210123804.5A 2022-02-10 2022-02-10 Ultra-wideband wafer level packaging matching structure Pending CN114496986A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115692350A (en) * 2023-01-03 2023-02-03 成都天成电科科技有限公司 Chip packaging structure for inhibiting higher mode
CN118016638A (en) * 2024-04-10 2024-05-10 成都天成电科科技有限公司 Low-loss broadband transition structure suitable for wafer level packaging

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115692350A (en) * 2023-01-03 2023-02-03 成都天成电科科技有限公司 Chip packaging structure for inhibiting higher mode
CN118016638A (en) * 2024-04-10 2024-05-10 成都天成电科科技有限公司 Low-loss broadband transition structure suitable for wafer level packaging
CN118016638B (en) * 2024-04-10 2024-07-12 成都天成电科科技有限公司 Low-loss broadband transition structure suitable for wafer level packaging

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