CN114495833B

CN114495833B - Driving circuit, driving method thereof and display device

Info

Publication number: CN114495833B
Application number: CN202210279193.3A
Authority: CN
Inventors: 金慧俊; 王听海; 秦丹丹
Original assignee: Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2022-03-21
Filing date: 2022-03-21
Publication date: 2023-07-04
Anticipated expiration: 2042-03-21
Also published as: CN114495833A

Abstract

The invention discloses a driving circuit, a driving method thereof and a display device, and relates to the technical field of display, wherein the driving circuit comprises a plurality of cascaded driving units, and the driving units comprise: the output ends of the first total driving circuits are respectively and electrically connected with clock signal ends of the first sub driving circuits and are used for providing clock signals for the first sub driving circuits; the output ends of the second total driving circuits are respectively and electrically connected with clock signal ends of the second sub driving circuits and are used for providing clock signals for the second sub driving circuits; the first clock signal line is electrically connected with the clock signal end of the first total driving circuit, and the second clock signal line is electrically connected with the clock signal end of the second total driving circuit. This is advantageous in reducing the power consumption of the driving circuit.

Description

Driving circuit, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method thereof, and a display device.

Background

TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor-liquid crystal display) and AMOLED (Active Matrix Driving OLED, active matrix driving organic light emitting diode) display devices are increasingly being used in high performance display fields due to their small size, low power consumption, no radiation, and relatively low manufacturing cost.

In the display device, each pixel in the panel is generally driven by a driving circuit to display. The driving circuit mainly includes a gate driving circuit and a data driving circuit. The data driving circuit is used for sequentially latching input data and clock signals in a timing mode, converting the latched data into analog signals and inputting the analog signals to the data lines of the panel. The gate driving circuit is used for converting a clock signal into an on/off voltage through a Shift Register (SR) and outputting the on/off voltage to each gate line of the panel. With the development of application technology, the requirements of low power consumption performance of display devices are increasing.

Therefore, providing a driving circuit with low power consumption is one of the technical problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above, the present invention provides a driving circuit, a driving method thereof, and a display device, which aims to solve the problem of large power consumption of the driving circuit in the prior art.

In a first aspect, the present application provides a driving circuit comprising: a plurality of cascaded drive units, the drive units comprising:

the output ends of the first total driving circuits are respectively and electrically connected with clock signal ends of the first sub driving circuits and are used for providing clock signals for the first sub driving circuits;

the output ends of the second total driving circuits are respectively and electrically connected with clock signal ends of the second sub driving circuits and are used for providing clock signals for the second sub driving circuits;

the first clock signal line is electrically connected with the clock signal end of the first total driving circuit and is used for providing a first clock signal for the first total driving circuit; the second clock signal line is electrically connected with the clock signal end of the second total driving circuit and is used for providing a second clock signal for the second total driving circuit; at the same driving time, the pulses of the first clock signal and the second clock signal are sequentially and alternately output and are not overlapped with each other.

In a second aspect, the present invention provides a driving method of a driving circuit, which is applied to the driving circuit in the first aspect, the driving method comprising:

and providing a first clock signal for the first total driving circuit by using the first clock signal line, providing a second clock signal for the second total driving circuit by using the second clock signal line, and controlling the first sub driving circuit and the second sub driving circuit in the same driving unit to alternately output control signals by using the output signals of the first total driving circuit and the output signals of the second total driving circuit.

In a third aspect, the present invention provides a display device comprising the driving circuit provided in the first aspect of the present invention.

Compared with the prior art, the driving circuit, the driving method and the display device provided by the invention have the advantages that at least the following effects are realized:

the driving circuit, the driving method thereof and the display device are provided with a plurality of cascaded driving units, wherein each driving unit respectively comprises a first total driving circuit, at least two first sub-driving circuits corresponding to the first total driving circuit, a second total driving circuit and at least two second sub-driving circuits corresponding to the second total driving circuit, wherein the output end of the first total driving circuit is electrically connected with the clock signal end of each first sub-driving circuit, and clock signals are provided for each first sub-driving circuit; the output end of the second total driving circuit is electrically connected with the clock signal end of each second sub driving circuit, and provides clock signals for each second sub driving circuit. In the invention, only the first total driving circuit is electrically connected with the first clock signal line, only the second total driving circuit is electrically connected with the second clock signal line, and the first sub driving circuits and the second sub driving circuits with more numbers are not required to be connected with the first clock signal line and the second clock signal line, each first sub driving circuit can use the output signal of the first total driving circuit as the clock signal, each second sub driving circuit can use the output signal of the second total driving circuit as the clock signal, thus greatly reducing the loads of the first clock signal line and the second clock signal line, and effectively reducing the overall power consumption of the driving circuit when the loads on the clock signal line are reduced.

Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a related art gate driving circuit;

FIG. 2 is a schematic diagram of a driving circuit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram showing a detailed structure of one driving unit in FIG. 2;

FIG. 4 is a circuit diagram of a shift register included in a driving circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a shift register included in a driving circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another connection of the driving circuit according to the embodiment of the present invention;

FIG. 7 is a schematic diagram showing another detailed structure of one of the driving units in FIG. 6;

FIG. 8 is a flow chart of a driving method of the driving circuit according to the embodiment of the invention;

Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the related art, an array substrate is one of important components of a display device (a liquid crystal display device, an organic light emitting diode display device, etc.). The array substrate comprises a plurality of grid lines, and the grid lines are used for circulating a conducting signal. For driving the gate lines, one existing method is to use a gate driving circuit (GOA), i.e., a circuit for driving each gate line is prepared in the array substrate. The gate driving circuit is typically composed of a plurality of shift registers in cascade, each for driving one gate line.

Referring to fig. 1, fig. 1 is a schematic diagram of a related art gate driving circuit, which includes a plurality of cascaded shift registers (e.g. shift registers ASG 1-ASG 5) and a first clock signal line clock1 and a second clock signal line clock2, wherein each shift register is electrically connected to the first clock signal line or the second clock signal line, specifically, any two adjacent shift registers, wherein one shift register is connected to the first clock signal line clock1 and the other shift register is connected to the second clock signal line clock2. That is, the number of shift registers connected to each clock signal line is half of the total number of shift registers, which results in a larger number of shift registers connected to each clock signal line, and a larger load on each clock signal line, which in turn results in a larger overall power consumption of the driving circuit.

The following description will proceed with reference being made to the drawings and specific embodiments.

Fig. 2 is a schematic diagram of a connection of a driving circuit according to an embodiment of the present invention, where the driving circuit 100 includes partially cascaded driving units; fig. 3 is a detailed schematic diagram of one driving unit in fig. 2, and it is understood that fig. 3 illustrates the structure of the driving unit in the first stage in fig. 2, and reference is made to fig. 3 for the structure of the driving units in the second stage and the other stages, which are not shown in detail herein.

Referring to fig. 2 and 3, the embodiment of the present invention provides a driving circuit 100, which includes: a plurality of cascaded drive units 00, the drive units 00 comprising:

the output end Gout of the first total driving circuit A is respectively and electrically connected with the clock signal end clock of the first sub driving circuit 10 and is used for providing a clock signal for the first sub driving circuit 10;

The output end Gout of the second total driving circuit B is respectively and electrically connected with the clock signal end clock of the second sub driving circuit 20 and is used for providing a clock signal for the second sub driving circuit 20;

a first clock signal line CK and a second clock signal line CKB, the first clock signal line CK being electrically connected to the clock signal terminal clock of the first total driving circuit a for supplying the first clock signal to the first total driving circuit a; the second clock signal line CKB is electrically connected with a clock signal end clock of the second total driving circuit B and is used for providing a second clock signal for the second total driving circuit B; at the same driving time, the pulses of the first clock signal and the second clock signal are sequentially and alternately output and do not overlap each other.

It will be appreciated that fig. 2 only shows 3 driving units 00 in the driving circuit, and does not represent the actual number of driving units 00 included in the driving circuit, and in some other embodiments of the present invention, the number of driving units 00 included in the driving circuit may be set according to actual requirements. Each driving unit 00 shown in fig. 2 is connected to 6 scanning lines GL, respectively, and the number of scanning lines GL to which each driving unit 00 is actually connected is the same as the total number of the first and

second sub-driving circuits

10 and 20 in the driving unit 00. Fig. 2 shows only part of the signal terminals of the driving unit 00, and does not represent the actual kind and number of signal terminals of the driving unit 00.

The embodiment of fig. 3 illustrates a specific structure of the driving unit 00 in the first stage in fig. 2, and in the embodiment of fig. 3, only a scheme including two total driving circuits and 6 sub driving circuits in the same driving unit 00 is taken as an example, and specifically includes a first total driving circuit a and three first sub driving circuits 10 (first sub driving circuits a-1, a-2 and a-3, respectively) corresponding to the first total driving circuit a, and a second total driving circuit B and three second sub driving circuits 20 (second sub driving circuits B-1, B-2 and B-3, respectively) corresponding to the second total driving circuit B. In some other embodiments of the present invention, the number of the first sub driving circuits 10 corresponding to the same first total driving circuit a may also be two or more, and the number of the second sub driving circuits 20 corresponding to the same second total driving circuit B may also be two or more.

Alternatively, the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B, and the second sub driving circuit 20 in the embodiment of the present invention are embodied as shift registers.

With continued reference to fig. 2 and 3, in the plurality of driving units 00 included in the driving circuit provided in the embodiment of the present invention, each of the total driving circuit and the sub driving circuit includes a clock signal terminal clock for receiving a clock signal. The driving circuit comprises a first clock signal line CK and a second clock signal line CKB, and for the same driving unit 00, the first clock signal line CK is used for being electrically connected with a clock signal end clock of the first total driving circuit A so as to provide a first clock signal for the first total driving circuit A; the second clock signal line CKB is electrically connected to a clock signal terminal clock of the second total driving circuit B, so as to provide the second clock signal to the second total driving circuit B. In particular, in the embodiment of the present invention, the clock signal terminal clock of each of the first sub-driving circuits 10 (i.e., the first sub-driving circuits a-1, a-2, and a-3) corresponding to the first total driving circuit a is not electrically connected to the first clock signal line CK, but is electrically connected to the output terminal Gout of the first total driving circuit a, and the signal output by the output terminal Gout of the first total driving circuit a is used as the clock signal of each of the first sub-driving circuits 10 (i.e., the first sub-driving circuits a-1, a-2, and a-3). Similarly, the clock signal terminals clock of the respective second sub driving circuits 20 (i.e., the second sub driving circuits B-1, B-2, and B-3) corresponding to the second total driving circuit B are not electrically connected to the second clock signal line CKB, but are electrically connected to the output terminal Gout of the second total driving circuit B, and the signal output from the output terminal Gout of the second total driving circuit B serves as the clock signal of the respective second sub driving circuits 20.

In the present invention, the driving circuit adopts a total division structure, only the first total driving circuit a is electrically connected to the first clock signal line CK, only the second total driving circuit B is electrically connected to the second clock signal line CKB, and the first and second

sub driving circuits

10 and 20 with a larger number are not required to be connected to the first and second clock signal lines CK and CKB, each first sub driving circuit 10 can use the output signal of the first total driving circuit a as a clock signal, each second sub driving circuit 20 can use the output signal of the second total driving circuit B as a clock signal, so that the number of shift registers connected to the first and second clock signal lines CK and CKB is greatly reduced, and when the load on the clock signal lines is reduced, the overall power consumption of the driving circuit can be effectively reduced.

Alternatively, assuming that the driving circuits are layered as a whole, the first total driving circuit a and the second total driving circuit B are located at a first layer, and the first sub driving circuit 10 and the second sub driving circuit 20 are located at a second layer. The ratio of the number of the shift registers of the first layer to the number of the shift registers of the second layer is less than 1:2, and when the ratio of the numbers is 1:2, the load on the clock signal line is reduced to 1/2 of the load in the prior art, and the total power consumption is reduced to 1/2 of the prior art. When the ratio of the numbers is 1:10, the load on the clock signal line is reduced to 1/10 of the load in the prior art, and the total power consumption is reduced to 1/10 of the prior art.

With continued reference to fig. 2 and 3, in an alternative embodiment of the present invention, in each driving unit 00, the clock signal terminals clock of the first total driving circuit a are connected to the same first clock signal line CK, and the clock signal terminals clock of the second total driving circuit B are connected to the same second clock signal line CKB.

Specifically, when the driving circuit includes a plurality of driving units 00, the clock signal terminals clock of each first total driving circuit a in each driving unit 00 are connected to the same first clock signal line CK, so that it is unnecessary to provide different first clock signal lines CK for different driving units 00, which is advantageous in reducing the number of first clock signal lines CK included in the driving circuit as a whole, and thus is advantageous in simplifying the overall structure of the driving circuit.

Similarly, when the driving circuit includes a plurality of driving units 00, the clock signal terminals clock of each second total driving circuit B in each driving unit 00 are all connected to the same second clock signal line CKB, so that it is not necessary to provide different second clock signal lines CKB for different driving units 00, which is beneficial to reducing the number of second clock signal lines CKB included in the driving circuit as a whole, and thus is beneficial to simplifying the overall structure of the driving circuit.

With the above structure, only one first clock signal line CK and one first second clock signal line CKB need to be introduced into the whole driving circuit, which greatly reduces the number of clock signal lines included in the driving circuit, and since the first clock signal line CK is electrically connected with each first sub driving circuit 10 only and the second clock signal line CKB is electrically connected with each second sub driving circuit 20 only, the number of shift registers connected with each clock signal line is effectively reduced, thereby greatly reducing the overall power consumption of the driving circuit.

Fig. 4 is a circuit diagram of a shift register included in a driving circuit according to an embodiment of the present invention, and fig. 5 is another circuit diagram of a shift register included in a driving circuit according to an embodiment of the present invention, alternatively, a first total driving circuit a, a second total driving circuit B, a first sub driving circuit 10 and a second sub driving circuit 20 in the embodiment of fig. 3 may be implemented as the structure shown in fig. 4 or the structure shown in fig. 5.

Assuming that the first total driving circuit a and the second total driving circuit B are both embodied in the structure shown in fig. 4, in an alternative embodiment of the present invention, each of the first total driving circuit a and the second total driving circuit B includes a first transistor T5, and a gate of the first transistor T5 is connected to a first node P;

In the first total driving circuit a, a first pole of the first transistor T5 is used as a clock signal terminal clock of the first total driving circuit a and is connected to a first clock signal line CK; the second pole of the first transistor T5 is connected with the output end Gout of the first total driving circuit A;

in the second total driving circuit B, a first pole of the first transistor T5 is used as a clock signal terminal clock of the second total driving circuit B and is connected to a second clock signal line CKB; the second pole of the first transistor T5 is connected to the output Gout of the second overall driving circuit B.

Specifically, referring to fig. 4 or fig. 5, a first pole of the first transistor T5 in the first total driving circuit a is electrically connected to the first clock signal line CK, and a second pole of the first transistor T5 is connected to the output terminal Gout of the first total driving circuit a, and it is seen that the first pole of the first transistor T5 is directly connected to the clock signal, and the clock signal is not a constant signal but a fluctuating signal with alternating high and low levels, and the fluctuation of the clock signal causes a variation of the coupling capacitance between the first pole and the second pole of the first transistor T5. Similarly, in the second total driving circuit B, the clock signal with the alternating high and low levels on the second clock signal line CKB may also cause a change in the coupling capacitance between the first pole and the second pole of the first transistor T5.

If clock signal terminals clock of each shift register in the driving circuit are directly connected with the clock signal line, the fluctuating clock signal on the clock signal line can cause the variation of coupling capacitance between the first pole and the second pole of the first transistor in each shift register, so that the total load of the clock signal line is increased. Therefore, the driving circuit is divided into the total split structure, only the first transistors of the first total driving circuit A and the second total driving circuit B are electrically connected with the clock signal line, and the clock signal ends clock of the first transistors of the first total driving circuit A and the second total driving circuit B are not connected with the clock signal line, but signals output by the first total driving circuit A or the second total driving circuit B are used as clock signals, so that the number of shift registers connected with the clock signal line is greatly reduced, the load of the clock signal line is effectively reduced, and the overall load of the driving circuit is further reduced.

In the shift register shown in fig. 4, the shift register has a 9T2C structure composed of 9 transistors (T1 to T9), 2 capacitors (C1 and C2), and the like, and the pull-down signal Q at point P is ac-coupled by the clock oscillation signal CKB, and thus is an ac signal. In the initial state, the Q point is at a low potential. When the clock oscillation signal CKB rises from low potential to high potential, the Q-point voltage rises by the capacitive coupling effect, and the transistors T3, T6 are put in an on state. When the clock oscillation signal CKB drops from high to low, the Q-point voltage is coupled to low again, turning off the transistors T3 and T6. When the clock oscillation signal CKB is at a low potential and the next rising has not started yet, the Q point is always at a low potential, and the transistors T3 and T6 are always in an off state. The pull-down signal (Q point) of the gate (P point) of the output driving tube T5 of the shift register in fig. 4 is generated by ac coupling of the clock oscillation signal CKB, which has two problems: the clock oscillating signal CKB is an ac square wave, when the clock oscillating signal CKB is at a high potential, the Q point works, and when the clock oscillating signal CKB is at a low potential, the Q point fails.

The shift register shown in fig. 5 includes a first node P, a second node Q1, a third node Q2, a clock signal terminal clock, a first control potential terminal FW, a second control potential terminal BW, a first signal input terminal Gn-1, a second signal input terminal gn+1, a clear potential terminal RESET, a turn-off potential terminal Goff, a low level signal terminal VGL, a first adjustment potential terminal V1, a second adjustment potential terminal V2, and an output terminal Gout.

The shift register of the present embodiment clears static electricity in the first node P and the signal output terminal Gout by first setting the clear potential terminal Reset and the off potential terminal Goff connected to the Reset module (twelfth transistor) high. Then, the first regulated potential terminal V1 or the second regulated potential terminal V2 starts to leak current to the second node Q1 or the third node Q2 through the stabilizing module 20, and the potential of the second node Q1 or the third node Q2 gradually increases to such an extent that the low potential of the low level signal terminal VGL can be transmitted to the first node P and the signal output terminal Gout, thereby pulling down the potentials of the first node P and the signal output terminal Gout. Next, the first control potential terminal FW charges the first node P, and the potentials of the second node Q1 and the third node Q2 are pulled down after the potential of the first node P is gradually filled. Then the first signal input end Gn-1 stops inputting signals, the clock signal end clock starts inputting signals, the first node P generates bootstrap, the signal output end Gout outputs signals, when the bootstrap is performed, the first node P is in a suspended state, at the moment, the potential of the clock signal end clock is lifted from low potential to high potential, the clock signal end clock is coupled through the output module, and the potential coupling of the first node P is lifted. Then, the clock signal terminal clock stops inputting the signal, and the signal output terminal Gout stops outputting the signal. And the signal input of the second signal input terminal gn+1 pulls down the potential of the first node P, and the second node Q1 and the third node Q2 restore the original potential and continuously pull down the potential of the first node P. The subsequent first signal input terminal Gn-1 no longer inputs signals, the potentials of the second node Q1 and the third node Q2 do not change, and the potential of the first node P is pulled down all the time.

Of course, the shift registers included in the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B, and the second sub driving circuit 20 according to the embodiments of the present invention may also be embodied in other structures, such as a conventional 11T1C circuit, etc., which is not limited in detail.

Optionally, the first total driving circuit a, the second total driving circuit B, the first sub driving circuit 10 and the second sub driving circuit 20 provided in the embodiment of the present invention include a clock signal end clock, a first control potential end FW, a second control potential end BW, a first signal input end Gn-1, a second signal input end gn+1, a zero clearing potential end Reset, a closing potential end Goff, a low level signal end VGL and an output end Gout, respectively. For example, please refer to fig. 6 and fig. 7, wherein fig. 6 is a schematic diagram illustrating another connection of the driving circuit according to the embodiment of the present invention, and fig. 7 is a schematic diagram illustrating another detailed structure of one driving unit 00 in fig. 6. Of course, if the first total driving circuit a, the second total driving circuit B, the first sub driving circuit 10 and the second sub driving circuit 20 adopt the structure shown in fig. 4, the simplified drawing method further includes the first adjusting potential terminal V1 and the second adjusting potential terminal V2, which are not shown one by one.

Referring to fig. 2, 3 and 6 and 7, in an alternative embodiment of the present invention, the output terminals Gout of the first sub driving circuit 10 and the second sub driving circuit 20 are respectively connected to different scan lines GL;

the driving unit 00 comprises a total input end group_start, and in the same driving unit 00, the total input end group_start is connected with a first input end Gn-1 of a first total driving circuit A and a first input end Gn-1 of a first sub driving circuit A-1 positioned at a first stage and connected with the first total driving circuit A;

the output end Gout of the first sub driving circuit A-1 positioned at the first stage is also connected with the first input end Gn-1 of the second total driving circuit B positioned at the first stage and the first input end Gn-1 of the second sub driving circuit B-1 positioned at the first stage and connected with the second total driving circuit B;

the output terminal Gout of the second sub driving circuit 20 at the n-th stage is further connected to the first input terminal Gn-1 of the first sub driving circuit 10 at the n+1-th stage, and the output terminal Gout of the first sub driving circuit 10 at the n+1-th stage is further connected to the first input terminal Gn-1 of the second sub driving circuit 20 at the n+1-th stage, wherein n is not less than 1.

Specifically, in the driving circuit provided in the embodiment of the present invention, each of the first sub driving circuit 10 and each of the second sub driving circuits 20 are respectively connected to different scanning lines GL (corresponding to the scanning lines G1 to G6 in the embodiment shown in fig. 7), so as to provide scanning signals to the different scanning lines GL through the first sub driving circuit 10 and the second sub driving circuit 20. The total input group_start of the driving unit 00 at the first stage is used for connecting with a start trigger signal terminal, and is started in response to the signal of the start trigger signal terminal. The total input end of the driving unit 00 is connected with the first input end Gn-1 of the first total driving circuit A and the first input end Gn-1 of the first sub driving circuit A-1 corresponding to the first total driving circuit A and positioned at the first stage, so that the starting trigger signal sent by the starting trigger signal end can be simultaneously transmitted to the first total driving circuit A and the first sub driving circuit A-1 corresponding to the first total driving circuit A and positioned at the first stage. The output terminal Gout of the first sub driving circuit A-1 at the first stage is electrically connected with the first input terminal Gn-1 of the second main driving circuit B at the first stage and the first input terminal Gn-1 of the second sub driving circuit B-1 at the first stage connected with the second main driving circuit B in addition to the scanning line G1. The output terminal Gout of the second sub driving circuit 20 at the nth stage is connected to the first input terminal Gn-1 of the first sub driving circuit 10 at the n+1 stage in addition to the scanning line GL; the output terminal Gout of the first sub driving circuit 10 at the n+1 stage is connected to the first input terminal Gn-1 of the second sub driving circuit 20 at the n+1 stage in addition to the scanning line GL.

The first sub driving circuit 10 and the second sub driving circuit 20 are started in response to the signal of the first input end Gn-1, and the output end Gout of the first sub driving circuit 10 of the nth stage is connected with the first input end Gn-1 of the second sub driving circuit 20 of the nth stage to provide a starting signal for the second sub driving circuit 20 of the nth stage; the output terminal Gout of the second sub driving circuit 20 of the n-th stage is connected to the first input terminal Gn-1 of the first sub driving circuit 10 of the n+1-th stage, and provides the start signal for the first sub driving circuit 10 of the n+1-th stage, thereby realizing a process that the first sub driving circuit 10 and the second sub driving circuit 20 alternately provide the scan signals to the corresponding scan lines GL in the same driving unit 00, that is, the output terminal Gout sequentially outputs the scan signals to the scan lines G1, G2, G3, G4, G5, and G6 connected to each other. In the practical application process, the output terminal Gout of the first sub driving circuit a-1 positioned at the first stage in the same driving unit 00 can be connected with the scanning line G1 of the first row, the output terminal Gout of the second sub driving circuit B-1 positioned at the first stage can be connected with the scanning line G2 of the second row, the output terminal Gout of the first sub driving circuit a-2 positioned at the second stage can be connected with the scanning line G3 of the third row, the output terminal Gout of the second sub driving circuit B-2 positioned at the second stage can be connected with the scanning line G4 of the fourth row, the output terminal Gout of the first sub driving circuit a-3 positioned at the third stage can be connected with the scanning line G5 of the fifth row, and the output terminal Gout of the second sub driving circuit B-3 positioned at the third stage can be connected with the scanning line G6 of the sixth row, thereby realizing progressive scanning of different rows of scanning lines.

With continued reference to fig. 2, 3 and 6 and 7, in an alternative embodiment of the present invention, the first total driving circuit a, the second total driving circuit B, the first sub driving circuit 10 and the second sub driving circuit 20 further comprise second input terminals gn+1, respectively;

in the same driving unit 00, the second input terminal gn+1 of the first total driving circuit a is connected to the second input terminal gn+1 of the first sub driving circuit 10 located at the last stage and the output terminal Gout of the second sub driving circuit 20 located at the last stage; the second input terminal gn+1 of the first sub driving circuit 10 at the nth stage is connected to the output terminal Gout of the second sub driving circuit 20 at the nth stage and the first input terminal Gn-1 of the first sub driving circuit 10 at the n+1 stage, and the second input terminal gn+1 of the second sub driving circuit 20 at the nth stage is connected to the output terminal Gout of the first sub driving circuit 10 at the n+1 stage; the second input terminal gn+1 of the second total driving circuit B and the second input terminal gn+1 of the second sub driving circuit 20 located at the last stage are connected to the total output terminal group_end of the driving unit 00, where n is greater than or equal to 1.

Specifically, the output terminal Gout of the second sub driving circuit 20 of the nth stage is respectively connected with the second input terminal gn+1 of the first sub driving circuit 10 of the nth stage and the first input terminal Gn-1 of the first sub driving circuit 10 of the n+1th stage, so that the signal output by the output terminal Gout of the second sub driving circuit 20 of the nth stage can be fed back to the first sub driving circuit 10 of the nth stage and can be transmitted to the first input terminal Gn-1 of the first sub driving circuit 10 of the n+1th stage as a start signal, thereby playing a role in starting up and down. In addition, the second input terminal gn+1 of the second sub driving circuit 20 at the n-th stage is connected to the output terminal Gout of the first sub driving circuit 10 at the n+1-th stage, and the signal output from the output terminal Gout of the first sub driving circuit 10 at the n+1-th stage can be fed back to the second sub driving circuit 20 at the n-th stage. The second input terminal gn+1 of the second total driving circuit B and the second input terminal gn+1 of the second partial driving circuit 20 located at the last stage are connected to the total output terminal group_end of the driving unit 00, and the total output terminal group_end of the driving unit 00 is connected to the driving unit 00 of the next stage, specifically, the output terminal Gout of the first partial driving circuit 10 located at the first stage in the driving unit 00 of the next stage is connected thereto, so that the signal of the output terminal Gout of the first partial driving circuit 10 located at the first stage in the driving unit 00 of the next stage can be fed back to the driving unit 00 of the previous stage adjacent thereto.

Referring to fig. 2 and 6, in an alternative embodiment of the present invention, the driving circuit further includes an activation trigger signal line STV; in the cascaded driving units 00, the total input end of the driving unit 00 positioned at the first stage is connected with a starting trigger signal line;

in the driving units 00 of the m-th and m+1th stages in cascade, the output terminal Gout of the second sub driving circuit 20 positioned at the last stage in the driving unit 00 of the m-th stage is connected with the total input terminal group_start of the driving unit 00 positioned at the m+1th stage; the total output end group_end of the driving unit 00 of the m-th stage is connected to the output end Gout of the first sub driving circuit 10 located at the first stage of the driving unit 00 of the m+1th stage, wherein m is equal to or greater than 1.

Specifically, in the manner of cascading the driving units 00 provided in the embodiment of the present invention, the total input end group_start of the driving unit 00 of the first stage is connected to the start trigger signal line STV, and the start trigger signal sent by the start trigger signal line STV triggers the driving unit 00 located in the first stage. The output terminal Gout of the second sub driving circuit 20 positioned at the last stage of the driving unit 00 of the m-th stage is connected with the total input terminal group_start of the driving unit 00 of the m+1th stage, and triggers the driving unit 00 of the m+1th stage; the total output terminal Gout of the driving unit 00 of the m-th stage is connected with the output terminal Gout of the first sub driving circuit 10 positioned at the first stage in the driving unit 00 of the m+1-th stage, thereby realizing the feedback of the output signal of the first sub driving circuit 10 positioned at the first stage to the second sub driving circuit 20 positioned at the last stage in the driving unit 00 of the m+1-th stage.

In an alternative embodiment of the present invention, please refer to fig. 7, in which the driving circuit provided in the embodiment of the present invention further includes a first level signal line, a second level signal line, and a reset signal line, and in the driving circuit, the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B, and the second sub driving circuit 20 are respectively connected to the same first level signal line, the same second level signal line, and the same reset signal line.

Specifically, referring to fig. 7, in the embodiment of the present invention, the first level signal line is a signal line connected to the low level signal terminal VGL, the second level signal line is a signal line connected to the high level signal terminal VGH, and the reset signal line is a signal line connected to the reset potential terminal reset. In the present invention, the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B and the second sub driving circuit 20 in the different driving units 00 share the first level signal line, the second level signal line and the reset signal line, and it is not necessary to provide different signal lines for the different driving units 00, so that the structure of the driving circuits is facilitated to be simplified.

In an alternative embodiment of the present invention, please refer to fig. 2 to 4, the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B and the second sub driving circuit 20 all include the same number of transistors and capacitors, and the connection relations between the transistors and the capacitors are the same. That is, the circuit structures of the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B, and the second sub driving circuit 20 in the embodiment of the present invention are identical, and one of them can be regarded as a replica of the other, for example, when the first total driving circuit a adopts a 9T2C structure, the first sub driving circuit 10, the second total driving circuit B, and the second sub driving circuit 20 each adopts a 9T2C structure identical to the first total driving circuit a structure. When the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B and the second sub driving circuit 20 in the embodiment of the present invention are formed by adopting the same circuit structure, the total sub driving circuits can be manufactured by adopting the same specification and dimension, so that the whole manufacturing process of the driving circuits is simplified, and the production efficiency of the driving circuits is improved.

In an alternative embodiment of the present invention, the first total driving circuit a, the first sub driving circuit 10, the second total driving circuit B and the second sub driving circuit 20 are shift registers. The structure of the shift register may refer to the structure of fig. 4 or fig. 5 in particular, or other shift register structures in the related art may be adopted, which is not particularly limited in the present invention. In the invention, only the first total driving circuit A and the second total driving circuit B are electrically connected with the clock signal line, and the first sub driving circuit 10 and the second sub driving circuit 20 with a large number are not electrically connected with the clock signal line, so that the load of the clock signal is greatly reduced, and the overall power consumption of the driving circuit is effectively reduced.

Based on the same inventive concept, the present invention also provides a driving method of a driving circuit, which is applied to the driving circuit provided by any of the above embodiments of the present invention, and fig. 8 is a flowchart of the driving method of the driving circuit provided by the embodiment of the present invention, and referring to fig. 2 and 3, the driving method provided by the embodiment of the present invention includes:

the first clock signal line CK is used to supply a first clock signal to the first total driving circuit a, the second clock signal line CKB is used to supply a second clock signal to the second total driving circuit B, and the output signal of the first total driving circuit a and the output signal of the second total driving circuit B control the first sub driving circuit 10 and the second sub driving circuit 20 in the same driving unit 00 to alternately output control signals.

Specifically, in the driving method of the driving circuit according to the embodiment of the present invention, since the first clock signal line CK is electrically connected to only the first total driving circuit a and the second clock signal line CKB is electrically connected to only the second total driving circuit B, the output signal of the first total driving circuit a is used as the clock signal of the first sub driving circuit 10 and the output signal of the second total driving circuit B is used as the clock signal of the second sub driving circuit 20. When the first clock signal line CK is used to supply the first clock signal to the first total driving circuit a and the second clock signal line CKB is used to supply the second clock signal to the second total driving circuit B, the first sub driving circuit 10 and the second sub driving circuit 20 can be controlled to be alternately turned on, thereby realizing time-sharing output of the scan signals to different scan lines GL. The first clock signal line CK in the present invention only needs to transmit the first clock signal to the first total driving circuit a, and does not need to transmit the clock signal to the first sub driving circuits 10 of which the number is large; the second clock signal line CKB only needs to transmit the second clock signal to the second total driving circuit B, and does not need to transmit the clock signal to the second sub driving circuit 20 of which the number is large. Thus, the loads of the first clock signal line CK and the second clock signal line CKB are effectively reduced, and the overall load of the driving circuit is further effectively reduced.

Based on the same inventive concept, fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 9, a display device 200 according to an embodiment of the present invention includes a driving circuit 100 according to any of the above embodiments. Alternatively, the driving circuit 100 is located at the left and right frame positions of the display device.

In the driving circuit included in the display device provided by the embodiment of the invention, the first clock signal line is only electrically connected with the first main driving circuit, but not electrically connected with the first sub-driving circuits with a large number; the second clock signal line is only electrically connected with the second main driving circuit, but not with the second sub driving circuits with a large number, wherein the first main driving circuit, the first sub driving circuit, the second main driving circuit and the second sub driving circuit can be embodied as shift registers, so that the number of the shift registers connected with the first clock signal line and the second clock signal line is greatly reduced, the load on the second clock signal line is effectively reduced, and the whole power consumption of the display device is further reduced.

It can be understood that fig. 9 of the present invention is only a schematic diagram illustrating the structure of the display device related to the technical scheme of the embodiment of the present invention, and those skilled in the art can make supplementary understanding according to the structure of the display device in the prior art, and the embodiment is not described herein.

It should be noted that the display device provided by the embodiment of the invention can be a liquid crystal display, electronic paper, an OLED display, and can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

In summary, the driving circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A driving circuit, characterized by comprising: a plurality of cascaded drive units, the drive units comprising:

the first clock signal line is electrically connected with the clock signal end of the first total driving circuit and is used for providing a first clock signal for the first total driving circuit; the second clock signal line is electrically connected with the clock signal end of the second total driving circuit and is used for providing a second clock signal for the second total driving circuit; at the same driving moment, the pulses of the first clock signal and the second clock signal are sequentially and alternately output and are not overlapped with each other;

The driving unit comprises a first driving circuit, a first sub driving circuit, a second driving circuit and a second sub driving circuit, wherein the first driving circuit, the first sub driving circuit, the second driving circuit and the second sub driving circuit are respectively connected with a first level signal line, a second level signal line and a reset signal line;

the first total driving circuit, the first sub driving circuit, the second total driving circuit and the second sub driving circuit all comprise the same number of transistors and capacitors, and the connection relations among the transistors and between the transistors and the capacitors are the same;

the first total driving circuit, the first sub driving circuit, the second total driving circuit and the second sub driving circuit are all shift registers.

2. The driving circuit according to claim 1, wherein in each of the driving units, a clock signal terminal of the first total driving circuit is connected to the same first clock signal line, and a clock signal terminal of the second total driving circuit is connected to the same second clock signal line.

3. The drive circuit of claim 1, wherein the first total drive circuit and the second total drive circuit each comprise a first transistor having a gate connected to a first node;

In the first total driving circuit, a first pole of the first transistor is used as a clock signal end and is connected with the first clock signal line; the second pole of the first transistor is connected with the output end of the first total driving circuit;

in the second total driving circuit, a first pole of the first transistor is used as a clock signal end and is connected with the second clock signal line; the second pole of the first transistor is connected with the output end of the second total driving circuit.

4. The driving circuit according to claim 1, wherein the output terminals of the first sub driving circuit and the second sub driving circuit are respectively connected to different scanning lines;

the driving unit comprises a total input end, and the total input end is connected with a first input end of the first total driving circuit and a first input end of the first sub driving circuit which is connected with the first total driving circuit and is positioned at a first stage in the same driving unit;

in the same driving unit, the output end of the first sub driving circuit positioned at the first stage is also connected with the first input end of the second total driving circuit and the first input end of the second sub driving circuit positioned at the first stage and connected with the second total driving circuit;

The output end of the second sub-driving circuit positioned at the nth stage is also connected with the first input end of the first sub-driving circuit positioned at the n+1th stage, and the output end of the first sub-driving circuit positioned at the n+1th stage is also connected with the first input end of the second sub-driving circuit positioned at the n+1th stage, wherein n is more than or equal to 1.

5. The drive circuit of claim 1, wherein the first total drive circuit, the second total drive circuit, the first sub drive circuit, and the second sub drive circuit further comprise second inputs, respectively;

in the same driving unit, a second input end of the first total driving circuit is connected with a second input end of the first sub driving circuit positioned at the last stage and an output end of the second sub driving circuit positioned at the last stage; the second input end of the first sub-driving circuit positioned at the nth stage is connected with the output end of the second sub-driving circuit positioned at the nth stage and the first input end of the first sub-driving circuit positioned at the n+1th stage, and the second input end of the second sub-driving circuit positioned at the nth stage is connected with the output end of the first sub-driving circuit positioned at the n+1th stage; the second input end of the second total driving circuit and the second input end of the second sub driving circuit positioned at the last stage are connected with the total output end of the driving unit, wherein n is more than or equal to 1.

6. The drive circuit of claim 5, further comprising an enable trigger signal line; in the cascaded driving units, the total input end of the driving unit positioned at the first stage is connected with the starting trigger signal line;

in the driving units of the m-th stage and the m+1-th stage in cascade connection, the output end of the second sub-driving circuit positioned at the last stage in the driving unit of the m-th stage is connected with the total input end of the driving unit positioned at the m+1-th stage; the total output end of the driving unit of the mth stage is connected with the output end of the first sub-driving circuit positioned at the first stage in the driving unit of the (m+1) th stage, wherein m is more than or equal to 1.

7. A driving method of a driving circuit, which is applied to the driving circuit according to any one of claims 1 to 6, characterized by comprising:

8. A display device comprising the drive circuit according to any one of claims 1 to 6.