CN114488863A - Single-edition data acquisition system adaptive to ARM architecture CPU - Google Patents
Single-edition data acquisition system adaptive to ARM architecture CPU Download PDFInfo
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Abstract
The invention discloses a single-computer data acquisition system adaptive to an ARM architecture CPU, and particularly relates to the technical field of data acquisition. According to the invention, a plurality of redundancies generated during data transmission and data acquisition are eliminated by arranging the filtering unit, the filtering unit forms a special redundancy processing group aiming at a redundancy mode according to a data acquisition table of the system, on one hand, the internal memory required by the system to operate and process data is reduced, so that the energy consumption during the operation of the system is reduced, and the energy is saved, on the other hand, the data redundancy is reduced, the data validity is higher, the accuracy and the validity of the data finally obtained by the system processing are higher, and the popularization effect is stronger.
Description
Technical Field
The invention relates to the technical field of data acquisition, in particular to a single-computer data acquisition system adaptive to an ARM architecture CPU.
Background
The ARM architecture is a 32-bit RISC architecture that is widely used in many embedded system designs. Due to the characteristic of energy saving, the ARM processor is very suitable for the field of mobile communication and meets the characteristic that the main design target is low power consumption. An embedded system is defined as a special computer system which is centered on application, based on computer technology, and has tailorable software and hardware, and meets the strict requirements of the application system on functions, reliability, cost, volume, power consumption and the like. Compared with a general computer system, the computer system has the characteristics of small volume and low power consumption, and is usually embedded into the computer system as a part of equipment; for specific application, the software and hardware of the customized system must be designed with high efficiency, the size and the clothes are tailored, the cost for removing redundancy is low, the cost performance is high, and the life cycle is long; the method has bootstrap development capability, and the reliability is easily ensured. Data collection is generally two types, one being the process of collecting, identifying, and selecting data from a data source. The other is the recording process of the digitization, electronic scanning system, and the encoding process of the content and attributes. With the advancement of the digital revolution, data acquisition technology has also been rapidly developed. With the rapid development of electronic and computer technologies, data acquisition technology has become one of the most important means for information acquisition. Meanwhile, each application field also puts higher requirements on the real-time performance, the integration level and the flexibility of digital signal processing. The existing low-speed non-real-time data acquisition and processing system is difficult to meet the high-end requirement
The speed of the current common data acquisition system is generally several MSps to several hundred MSps (million samples per second), and the data after analog-to-digital conversion is sent to a digital signal processor with lower performance through a buffer memory or is sent to a microcomputer through various buses, so that the data acquisition benefit of the existing single-machine version data acquisition system adaptive to the ARM architecture CPU is general.
Disclosure of Invention
In order to overcome the above defects in the prior art, embodiments of the present invention provide a single-machine data acquisition system adapted to an ARM architecture CPU, and a filtering unit is provided to eliminate many redundancies generated during data transmission and data acquisition, and a special redundancy processing group is formed for a redundancy mode, so that on one hand, a memory required by a system to process data during operation is reduced, thereby reducing energy consumption during operation of the system to save energy, and on the other hand, data redundancy is reduced, data validity is higher, and accuracy and validity of data finally obtained by processing the system are higher.
The invention provides a single-computer data acquisition system adaptive to an ARM architecture CPU, which comprises a CPU core (1), wherein the CPU core (1) is connected with a data input module (2), a data processing module (3) and a data storage module (4), and the data processing module (3) comprises a digital signal coarse-tuning amplification unit (301), a filtering unit (302) and a D/A converter (304);
the digital signal coarse tuning amplification unit (301) is used for receiving a digital signal and amplifying the digital signal by using an amplification circuit;
the filtering unit (302) is connected with the digital signal coarse tuning amplifying unit (301), and the filtering unit (302) is used for receiving the digital signal transmitted by the digital signal coarse tuning amplifying unit (301), processing redundant parts in the digital signal and reducing the amount of the digital signal.
In one embodiment of the invention, the digital signal coarse tuning amplifying unit (301) comprises a plurality of stages of independent amplifying circuits.
In an embodiment of the invention, the multi-stage independent amplifying circuit is a five-stage independent amplifying circuit, and each stage of amplifying circuit comprises an independent amplifier with an amplification factor of 2, a power supply filter capacitor, an amplifying interstage filter capacitor and an impedance resistor.
In an embodiment of the present invention, the data processing module (3) further includes a digital signal fine-tuning amplifying unit (303), the digital signal fine-tuning amplifying unit (303) is respectively connected to the filtering unit (302) and the D/a converter (304), and the digital signal fine-tuning amplifying unit (303) is configured to receive the filtered digital signal transmitted by the filtering unit (302), perform fine tuning, and amplify the digital signal.
In one embodiment of the invention, the D/a converter (304) is configured to convert a digital signal input by the data processing module (3) into an analog signal of data, convert a digital quantity into an analog quantity, restore the digital signal processed by software into a corresponding analog signal, and transmit the corresponding analog signal to the data storage module (4).
In one embodiment of the invention, the data input module (2) comprises a data receiving unit (201), a data exchange unit (202), a digital input unit (203) and a calibration unit (204), wherein the data receiving unit (201) is used for acquiring data information and transmitting the acquired data information to the data exchange unit (202);
the data exchange unit (202) is used for converting data information transmitted by the data receiving unit (201) into digital signals and inputting the converted digital signals into the digital input unit (203), the digital input unit (203) is used for receiving the digital signals input by the data exchange unit (202), eliminating phase transformation of the digital signals input by the data exchange unit (202) and inputting the digital signals with the phase transformation eliminated into the calibration unit (204);
one end of the calibration unit (204) is connected with the digital input unit (203) and is used for receiving the digital signal transmitted by the digital input unit (203), calibrating the digital signal and transmitting the calibrated digital signal to the data processing module (3).
In one embodiment of the present invention, the other end of the calibration unit (204) is connected to a reference circuit, and the digital signal transmitted by the digital input unit (203) is compared with a reference signal transmitted by the reference circuit for calibration, so as to obtain a calibrated digital signal.
In one embodiment of the present invention, the data storage module (4) includes a receiving unit (401), a communication distribution unit (402), a data management unit (403), and a storage unit (404), where the receiving unit (401) is configured to receive an analog signal transmitted by the data storage module (4) and transmit the analog signal to the communication distribution unit (402);
the communication distribution unit (402) connects the receiving unit (401), the data management unit (403) and the storage unit (404) together, and the receiving unit (401), the data management unit (403) and the storage unit (404) exchange information through the communication distribution unit (402).
In an embodiment of the present invention, the data management unit (403) is configured to manage data in the data storage module (4), and sort the data signals transmitted by the communication distribution unit (402).
In an embodiment of the present invention, the storage unit (404) is configured to respectively transfer the data to different storage locations for storing for a certain time according to the data class allocated by the data management unit (403), and the stored data may be read by the CPU core (1).
The invention also provides a single-computer version data acquisition system adaptive to the ARM architecture CPU, which comprises a CPU core, wherein the output end of the CPU core is connected with a data input module, a data processing module and a data storage module, and the data processing module comprises a digital signal coarse adjustment amplifying unit, a filtering unit, a digital signal fine adjustment amplifying unit and a D/A converter;
the digital signal rough adjustment amplifying unit comprises five independent amplifying circuits, wherein the five independent amplifying circuits are used for receiving digital signals transmitted by the data processing module and amplifying the digital signals by using the amplifying circuits, the amplification times of the five independent amplifying circuits are respectively 1, 2, 4, 8 and 16, each amplifying circuit comprises an independent amplifier, a power supply filter capacitor, an amplifying interstage filter capacitor and an impedance resistor, and the fluctuation carried by a power supply is filtered by the power supply filter capacitor, so that the signals transmitted by the data processing module are not interfered, interference waves generated by the amplifying signals of the amplifiers are filtered and eliminated by using the amplifying interstage filter capacitor, and the signals are amplified by matching with the independent amplifiers;
the filtering unit is used for processing redundant parts in the digital signals and reducing the amount of the digital signals, the filtering unit receives the digital signals transmitted by the digital signal coarse adjustment amplifying unit, forms a processing group aiming at the redundant mode according to a data acquisition table of a system, processes invalid digital signals caused by a single or mixed redundant mode in parallel redundancy and single redundancy, eliminates the redundant digital signals and then continuously transmits the digital signals to the digital signal fine adjustment amplifying unit.
The digital signal fine-tuning amplification unit is used for receiving the filtered digital signals transmitted by the filtering unit and performing fine tuning, the filtering unit filters the digital signals amplified in the digital signal coarse-tuning amplification unit and eliminates redundancy to obtain digital signals of accurate effective data, the digital signals are transmitted to the digital signal fine-tuning amplification unit, the digital signal fine-tuning amplification unit performs fine tuning on the amplified digital signals and amplifies the digital signals, and the amplification times are respectively 1, 2, 4, 8 and 16;
the D/A converter is used for converting the digital signals input by the digital signal fine-tuning amplification unit into analog signals of data, converting the digital quantity into analog quantity, restoring the digital signals processed by software into corresponding analog signals and continuously transmitting the analog signals to the data storage module.
The data input module comprises a data receiving unit, a data exchange unit, a digital input unit and a calibration unit, wherein the data receiving unit is used for acquiring relevant data of equipment, the data receiving unit comprises a plurality of data access ends, and different data access ends gather acquired signals together and transmit the acquired information to the data exchange unit;
the data exchange unit is mainly used for converting the data transmitted by the data receiving unit into digital signals, converting the digital signals into corresponding digital signals according to the data information acquired by the data receiving unit, then inputting the converted digital signals into the digital input unit, the digital input unit is mainly used for receiving the digital signals input by the data exchange unit, eliminating phase transformation of the digital signals input by the data exchange unit, and then inputting the digital signals without phase transformation into the calibration unit.
The calibration unit is used for receiving the digital signals transmitted by the digital input unit and calibrating the digital signals, one end of the calibration unit is connected with the digital input unit and used for receiving the digital signals transmitted by the digital input unit, the other end of the calibration unit is connected with the reference circuit, the reference signals transmitted by the reference circuit are calibrated by comparing the reference signals with the digital signals transmitted by the digital input unit, calibrated digital signals are obtained, and the calibrated digital signals are transmitted to the data processing module.
The data storage module comprises a receiving unit, a communication distribution unit, a data management unit and a storage unit, wherein the receiving unit is used for receiving the analog signals transmitted by the data storage module and transmitting the analog signals to the communication distribution unit.
The communication distribution unit connects the receiving unit, the data management unit and the storage unit together, the receiving unit receives data and transmits the data to the communication distribution unit, then the received information transmitted in the receiving unit is transmitted to the data management unit, and the receiving unit, the data management unit and the storage unit exchange information through the communication distribution unit.
The data management unit is used for managing the global data in the data storage module, and sorting the data signals transmitted by the communication distribution unit according to the sorting mode of the system, so that the data signals are well processed according to categories.
The storage unit is used for storing the data arranged by the data management unit at a proper storage position in the system, the data management unit arranges the data and transmits the data to the storage unit, then the storage unit respectively transmits the data to different storage positions according to the data type distributed by the data management unit for storage for a certain time, and the stored data can be read by a CPU core.
Compared with the prior art, the invention at least has the following technical effects and advantages:
the filtering unit is arranged to eliminate a plurality of redundancies generated during data transmission and data acquisition, a special redundancy processing group is formed by the filtering unit according to a data acquisition table of the system aiming at a redundancy mode to process invalid digital signals brought by a single or mixed redundancy mode in parallel redundancy and single redundancy, redundant data generated in the data acquisition process are eliminated to a great extent by utilizing the mode, the data redundancy is reduced, on the one hand, a memory required by the system for processing the data during operation is reduced, and therefore, the energy consumption during the operation of the system is reduced, and the energy is saved. And on the other hand, the data redundancy is reduced, the proportion of effective data collected by the system is increased, the data validity is higher, and the accuracy and validity of the data finally obtained by the system processing are higher, so that the overall benefit generated by the system operation is improved, the cost performance is improved, and the popularization effect is stronger.
On the other hand, original acquisition, intermediate processing, redundancy elimination and data storage of data are integrated together through setting, the output is specific application, and network connection and open source channels are not needed, so that a single-machine-version data acquisition system is formed, the CPU adaptive to an ARM framework is matched with an embedded system, the size is small, the energy consumption is low, specific application is oriented, the high-efficiency design is realized, the tailoring is realized, the redundancy removal cost is low, the cost performance is high, the life cycle is long, and the reliability is more easily ensured.
Drawings
Fig. 1 is a topology diagram of the present invention.
Fig. 2 is a schematic view of the overall structure of the present invention.
FIG. 3 is a schematic structural diagram of a data input module according to the present invention.
FIG. 4 is a block diagram of a data processing module according to the present invention.
FIG. 5 is a schematic diagram of a data storage module according to the present invention.
The reference signs are: 1. a CPU core; 2. a data input module; 3. a data processing module; 4. a data storage module; 201. a data receiving unit; 202. a data exchange unit; 203. a digital input unit; 204. a calibration unit; 301. a digital signal coarse tuning amplifying unit; 302. a filtration unit; 303. a digital signal fine-tuning amplifying unit; 304. a D/A conversion unit; 401. a receiving unit; 402. a communication distribution unit; 403. a data management unit; 404. and a memory unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, 2 and 4, the single-computer data acquisition system adapted to the ARM framework CPU includes a CPU core 1, the CPU core 1 is connected to a data input module 2, a data processing module 3 and a data storage module 4, and the data processing module 3 includes a digital signal coarse tuning and amplifying unit 301, a filtering unit 302, a digital signal fine tuning and amplifying unit 303 and a D/a converter 304. The digital signal coarse tuning amplification unit 301, the filtering unit 302, the digital signal fine tuning amplification unit 303, and the D/a converter 304 are connected in sequence.
The digital signal rough adjustment amplifying unit 301 includes five independent amplifying circuits for receiving the digital signal transmitted from the data processing module 3 and amplifying the digital signal by using the amplifying circuits, the five independent amplifying circuits have amplification factors of 1, 2, 4, 8 and 16, each amplifying circuit includes an independent amplifier with amplification factor of 2, a power supply filter capacitor, an amplifying interstage filter capacitor and an impedance resistor, and the fluctuation carried by the power supply is filtered by the power supply filter capacitor, so that the signal transmitted from the data processing module 3 is not interfered, and the amplifying interstage filter capacitor is used for filtering and eliminating the interference wave generated by the amplifying signal of the amplifier, and the signal is amplified by matching with the independent amplifier.
The filtering unit 302 is used for processing redundant parts in the digital signal to reduce the amount of the digital signal, the filtering unit 302 receives the digital signal transmitted from the digital signal coarse adjustment amplifying unit 301, forms a processing group aiming at the redundant mode according to a data acquisition table of a system, processes invalid digital signals caused by a single or mixed redundant mode in parallel redundancy and single redundancy, eliminates the redundant digital signals, and then continuously transmits the digital signals to the digital signal fine adjustment amplifying unit 303.
The implementation mode is specifically as follows: when the data processing module 3 is in operation, firstly, the digital signal is amplified by the digital signal rough-adjusting amplifying unit 301, the amplification times are respectively 1, 2, 4, 8 and 16 of the five-stage independent amplifying circuit, the fluctuation carried by the power supply is filtered by the power supply filtering capacitor under the combined action of the independent amplifier, the power supply filtering capacitor, the amplifying interstage filtering capacitor and the impedance resistor which are included in the amplifying circuit and have the amplification times of 2, thereby ensuring that the signal transmitted by the data processing module 3 is not interfered, filtering and eliminating interference waves generated by the amplifying signal by the amplifying interstage filtering capacitor, carrying out signal amplification by matching with the independent amplifier, after the digital signal is amplified by the digital signal rough-adjusting amplifying unit 301 and transmitted to the filtering unit 302, the filtering unit 302 receives the digital signal transmitted by the digital signal rough-adjusting amplifying unit 301, and according to the data acquisition table of the system, forming a processing group aiming at the redundancy mode, processing invalid digital signals caused by a single or mixed redundancy mode in parallel redundancy and single redundancy, removing redundant digital signals, then continuously transmitting the redundant digital signals to a digital signal fine-tuning amplifying unit 303, finely tuning the amplified digital signals by the digital signal fine-tuning amplifying unit 303, amplifying the digital signals, wherein the amplification times are respectively 1, 2, 4, 8 and 16, continuously inputting the digital signals after fine tuning and amplification into a D/A converter 304, the D/A converter 304 is used for converting the digital signals input by the digital signal fine-tuning amplifying unit 303 into analog signals of data, converting the digital quantities into analog quantities, reducing the digital signals after software processing into corresponding analog signals, continuously transmitting the analog signals to a data storage module 4, eliminating a plurality of redundancies generated during data transmission and data acquisition by using a filtering unit, the filtering unit 302 forms a special redundancy processing group aiming at the redundancy mode according to the data acquisition table of the system, processes invalid digital signals caused by a single or mixed redundancy mode of parallel redundancy and single redundancy, eliminates redundant data generated in the data acquisition process to a great extent by using the mode, reduces the data redundancy, reduces the memory required by the system for processing the data during operation on one hand, thereby reducing the energy consumption of the system during operation and saving energy, on the other hand, reducing the data redundancy, increasing the proportion of effective data acquired by the system, and the higher the data validity, the higher the accuracy and the validity of the data finally obtained by the system, thereby improving the overall benefit generated by the system operation, improving the cost performance, having stronger popularization effect, the implementation mode specifically solves the problem that the data acquisition benefit of the existing single-machine version data acquisition system adaptive to the ARM architecture CPU is general.
As shown in fig. 1, 2, 3 and 5, the data input module includes a data receiving unit 201, a data exchanging unit 202, a digital input unit 203 and a calibration unit 204, the data receiving unit 201 is used for collecting relevant data of the device, the data receiving unit 201 includes a plurality of data accessing terminals, different data accessing terminals collect the collected signals together and transmit the collected information to the data exchanging unit 202, the data exchanging unit 202 is mainly used for converting the data transmitted from the data receiving unit 201 into digital signals, converting the digital signals into corresponding digital signals according to the data information collected by the data receiving unit 201, and then inputting the converted digital signals into the digital input unit 203, the digital input unit 203 is mainly used for receiving the digital signals input by the data exchanging unit 202 and eliminating phase transformation of the digital signals input by the data exchanging unit 202, then, the digital signal with the phase transformation removed is input to the calibration unit 204, the calibration unit 204 is configured to receive the digital signal transmitted from the digital input unit 203 and calibrate the digital signal, one end of the calibration unit 204 is connected to the digital input unit 203 and is configured to receive the digital signal transmitted from the digital input unit 203, the other end of the calibration unit 204 is connected to the reference circuit, the reference signal transmitted from the reference circuit is calibrated with respect to the digital signal transmitted from the digital input unit 203 to obtain a calibrated digital signal, and the calibrated digital signal is transmitted to the data processing module 3.
The data storage module 4 comprises a receiving unit 401, a communication distribution unit 402, a data management unit 403 and a storage unit 404, the receiving unit 401 is used for receiving the analog signal transmitted by the data storage module 4 and transmitting the analog signal to the communication distribution unit 402, the communication distribution unit 402 connects the receiving unit 401, the data management unit 403 and the storage unit 404 together, the receiving unit 401 transmits the data to the communication distribution unit 402 after receiving the data, and then transmits the received information transmitted by the receiving unit 401 to the data management unit 403, the receiving unit 401, the data management unit 403 and the storage unit 404 exchange information through the communication distribution unit 402, the data management unit 403 is used for managing the global data in the data storage module 4, the data signal transmitted by the communication distribution unit 402 is arranged according to the sorting mode of the system, the sorting type processing is good, the storage unit 404 is configured to store the data sorted by the data management unit 403 in a proper storage place configured in the system, the data management unit 403 sorts the data and then transmits the sorted data to the storage unit 404, and then the storage unit 404 respectively transmits the data to different storage places according to the data class allocated by the data management unit 403 to store the data for a certain time, and the stored data can be read by the CPU core 1.
The implementation mode is specifically as follows: when the invention works, the data receiving unit 201 collects the collected signals together by different data access ends and transmits the collected information to the data exchange unit 202, the data exchange unit 202 converts the data information collected by the data receiving unit 201 into corresponding digital signals according to the data information, then the converted digital signals are input into the digital input unit 203, the digital input unit 203 is mainly used for receiving the digital signals input by the data exchange unit 202 and eliminating phase transformation of the digital signals input by the data exchange unit 202, then the digital signals eliminating phase transformation are input into the calibration unit 204, one end of the calibration unit 204 is connected with the digital input unit 203 and used for receiving the digital signals transmitted by the digital input unit 203, the other end is connected with a reference circuit, and the reference signals transmitted by the reference circuit are calibrated compared with the digital signals transmitted by the digital input unit 203, the calibrated digital signal is obtained, the calibrated digital signal is transmitted to the data processing module 3, the data processing module 3 transmits the processed data signal to the data storage module 4, the communication distribution unit 402 connects the receiving unit 401, the data management unit 403 and the storage unit 404 together, the receiving unit 401 receives the data and transmits the data to the communication distribution unit 402, then the received information transmitted in the receiving unit 401 is transmitted to the data management unit 403, the receiving unit 401, the data management unit 403 and the storage unit 404 exchange information through the communication distribution unit 402, the data management unit 403 is used for managing the global data in the data storage module 4, the data signals transmitted by the communication distribution unit 402 are arranged according to the sorting mode of the system, the data are processed in different categories, the storage unit 404 is used for configuring the data arranged by the data management unit 403 at a proper storage position in the system, the data management unit 403 sorts the data and then transmits the sorted data to the storage unit 404, then the storage unit 404 respectively transmits the data to different storage places for storing for a certain time according to the data type allocated by the data management unit 403, the stored data can be read by the CPU core 1, the original collection, intermediate processing, redundancy elimination and data storage of the data are integrated together through the data input module 2, the data processing module 3 and the data storage module 4 which are mutually matched, the data are output to be specific application, and a single-machine version data collection system is formed without network connection and source opening channels, is adapted to the CPU of an ARM framework, is matched with an embedded system, and has the advantages of small volume, low energy consumption, specific application oriented, high efficiency design, size tailoring, low cost for removing redundancy, high cost performance and long life cycle. The reliability is easier to guarantee, and the implementation mode specifically solves the problems that the existing single-computer data acquisition system adaptive to the ARM architecture CPU is complex in data acquisition and weak in applicability.
The working principle of the invention is as follows:
referring to fig. 1, 2 and 4 of the specification, when the data processing module 3 operates, firstly, the digital signal is amplified by the digital signal coarse-tuning amplifying unit 301, the five-stage independent amplifying circuit with the amplification times of 1, 2, 4, 8 and 16 respectively, the power supply filtering capacitor is used for filtering the fluctuation carried by the power supply, thereby ensuring that the signal transmitted by the data processing module 3 is not interfered, the filtering capacitor between the amplifying stages is used for filtering and eliminating the interference wave generated by the amplifying signal of the amplifier, the independent amplifier is used for amplifying the signal, the digital signal coarse-tuning amplifying unit 301 amplifies the digital signal and transmits the amplified digital signal to the filtering unit 302, the filtering unit 302 forms a processing group according to the data acquisition table of the system aiming at the redundancy mode, processes the invalid digital signal brought by the single or mixed redundancy mode of the parallel redundancy and the single redundancy, and eliminates the redundant digital signal, the digital signals are continuously transmitted to a digital signal fine adjustment amplifying unit 303, the digital signal fine adjustment amplifying unit 303 amplifies the digital signals and continuously inputs the digital signals to a D/A converter 304, the D/A converter 304 converts the digital quantity into an analog quantity, the digital signals processed by software are restored into corresponding analog signals, the analog signals are continuously transmitted to a data storage module 4, a plurality of redundancies generated during data transmission and data acquisition are eliminated, a special redundancy processing group is formed by a filtering unit 302 according to a data acquisition table of a system aiming at a redundancy mode, and invalid digital signals brought by a single or mixed redundancy mode in parallel redundancy and single redundancy are processed;
referring to fig. 1, 2, 3 and 5 of the specification, the data receiving unit 201 collects the collected signals at different data access ends together, and transmits the collected information to the data exchanging unit 202, the data exchanging unit 202 converts the collected signals into corresponding digital signals, and then inputs the converted digital signals into the digital input unit 203, the digital input unit 203 receives the digital signals input by the data exchanging unit 202 to eliminate phase transformation, and then inputs the digital signals with the eliminated phase transformation into the calibrating unit 204, one end of the calibrating unit 204 is connected with the digital input unit 203 and used for receiving the digital signals transmitted by the digital input unit 203, and the other end is connected with the reference circuit, and calibrates the reference signals transmitted by the reference circuit with the digital signals transmitted by the digital input unit 203 to obtain calibrated digital signals, and transmits the calibrated digital signals into the data processing module 3, the data processing module 3 sends the processed data signals to the data storage module 4, the communication distribution unit 402 connects the receiving unit 401, the data management unit 403 and the storage unit 404 together, the receiving unit 401 receives the data and then transmits the data to the communication distribution unit 402, the data management unit 403 is used for managing the global data in the data storage module 4, the data signals transmitted by the communication distribution unit 402 are arranged according to the sorting mode of the system, the data are processed according to the categories, the storage unit 404 is used for storing the data arranged by the data management unit 403 in the proper storage position in the system, the data management unit 403 arranges the data and then transmits the data to the storage unit 404, then the storage unit 404 respectively transmits the data to different storage positions according to the categories distributed by the data management unit 403 for storing for a certain time, the stored data can be read by the CPU core 1, through the data input module 2, the data processing module 3 and the data storage module 4 which are matched with each other, the original acquisition, the intermediate processing, the redundancy elimination and the data storage of the data are all integrated together, the data are output to be specific application, and network connection and open source channels are not needed, so that a single-machine data acquisition system is formed and is adaptive to a CPU (central processing unit) of an ARM (advanced RISC machine) framework.
And finally: the present invention is not limited to the above preferred embodiments, but rather, any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The utility model provides a single edition data acquisition system with ARM framework CPU adaptation, includes CPU kernel (1), its characterized in that: the CPU core (1) is connected with a data input module (2), a data processing module (3) and a data storage module (4), and the data processing module (3) comprises a digital signal coarse tuning amplification unit (301), a filtering unit (302) and a D/A converter (304);
the digital signal coarse tuning amplification unit (301) is used for receiving a digital signal and amplifying the digital signal by using an amplification circuit;
the filtering unit (302) is connected with the digital signal coarse tuning amplifying unit (301), and the filtering unit (302) is used for receiving the digital signal transmitted by the digital signal coarse tuning amplifying unit (301), processing redundant parts in the digital signal and reducing the amount of the digital signal.
2. The standalone version of the data acquisition system of claim 1, adapted to an ARM architecture CPU, wherein: the digital signal coarse adjustment amplifying unit (301) comprises a plurality of stages of independent amplifying circuits.
3. The standalone version of the data acquisition system of claim 2, adapted to an ARM architecture CPU, wherein: the multistage independent amplifying circuit is a five-stage independent amplifying circuit, and each stage of amplifying circuit comprises an independent amplifier with the amplification factor of 2, a power supply filter capacitor, an amplifying interstage filter capacitor and an impedance resistor.
4. A standalone version of the data acquisition system adapted to an ARM architecture CPU as claimed in any one of claims 1 to 3, wherein: the data processing module (3) further comprises a digital signal fine-tuning amplifying unit (303), the digital signal fine-tuning amplifying unit (303) is respectively connected with the filtering unit (302) and the D/A converter (304), and the digital signal fine-tuning amplifying unit (303) is used for receiving the filtered digital signal transmitted by the filtering unit (302), performing fine tuning and amplifying the digital signal.
5. The standalone version of the data acquisition system adapted to an ARM architecture CPU of any of claims 1-4, wherein: the D/A converter (304) is used for converting digital signals input by the data processing module (3) into analog signals of data, converting digital quantities into analog quantities, restoring the digital signals processed by software into corresponding analog signals and transmitting the analog signals to the data storage module (4).
6. The standalone version of the data acquisition system of claim 1, adapted to an ARM architecture CPU, wherein: the data input module (2) comprises a data receiving unit (201), a data exchange unit (202), a digital input unit (203) and a calibration unit (204), wherein the data receiving unit (201) is used for acquiring data information and transmitting the acquired data information to the data exchange unit (202);
the data exchange unit (202) is used for converting data information transmitted by the data receiving unit (201) into digital signals and inputting the converted digital signals into the digital input unit (203), the digital input unit (203) is used for receiving the digital signals input by the data exchange unit (202), eliminating phase transformation of the digital signals input by the data exchange unit (202) and inputting the digital signals with the phase transformation eliminated into the calibration unit (204);
one end of the calibration unit (204) is connected with the digital input unit (203) and is used for receiving the digital signal transmitted by the digital input unit (203), calibrating the digital signal and transmitting the calibrated digital signal to the data processing module (3).
7. The standalone version of the data acquisition system of claim 6, adapted to an ARM architecture CPU, wherein: the other end of the calibration unit (204) is connected with a reference circuit, and the digital signal transmitted by the digital input unit (203) is compared and calibrated with the reference signal transmitted by the reference circuit to obtain a calibrated digital signal.
8. The standalone version of the data acquisition system of claim 1, adapted to an ARM architecture CPU, wherein: the data storage module (4) comprises a receiving unit (401), a communication distribution unit (402), a data management unit (403) and a storage unit (404), wherein the receiving unit (401) is used for receiving the analog signal transmitted by the data storage module (4) and transmitting the analog signal to the communication distribution unit (402);
the communication distribution unit (402) connects the receiving unit (401), the data management unit (403) and the storage unit (404) together, and the receiving unit (401), the data management unit (403) and the storage unit (404) exchange information through the communication distribution unit (402).
9. The standalone version of the data acquisition system of claim 8, adapted to an ARM architecture CPU, wherein: the data management unit (403) is used for managing data in the data storage module (4) and classifying, sequencing and sorting the data signals transmitted by the communication distribution unit (402).
10. The standalone version of the data acquisition system of claim 8, adapted to an ARM architecture CPU, wherein: the storage unit (404) is used for respectively transmitting the data to different storage places according to the data classes distributed by the data management unit (403) for storing for a certain time, and the stored data can be read by the CPU core (1).
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