CN114487503A - Test connection device for mass production test of fA-level current - Google Patents
Test connection device for mass production test of fA-level current Download PDFInfo
- Publication number
- CN114487503A CN114487503A CN202210082049.0A CN202210082049A CN114487503A CN 114487503 A CN114487503 A CN 114487503A CN 202210082049 A CN202210082049 A CN 202210082049A CN 114487503 A CN114487503 A CN 114487503A
- Authority
- CN
- China
- Prior art keywords
- operational amplifier
- shielding
- electrically connected
- capacitor
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0416—Connectors, terminals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/18—Screening arrangements against electric or magnetic fields, e.g. against earth's field
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
本发明公开了一种用于量产测试fA级电流的测试连接装置，特点是包括测试金手指和包裹环绕在测试金手指外的电磁屏蔽体，测试金手指分别与待测芯片的器件端脚、电流测量装置电连接，电磁屏蔽体包括从内到外依次设置的第一绝缘环、屏蔽内环、第二绝缘环、电压快速稳定屏蔽环、第三绝缘环和接地屏蔽环，电磁屏蔽体上电连接有屏蔽控制电路，屏蔽控制电路先控制电压快速稳定屏蔽环的电位与测试金手指的电位相同，再控制屏蔽内环的电位与测试金手指的电位相同，直至测量结束；优点是该测试连接装置能减少或避免外界环境对测试金手指的影响，提高了测量精度；还缩短了电流测量装置对fA级漏电流的测量时间，提高了测量效率。
The invention discloses a test connection device for mass production testing fA-level current, which is characterized by comprising a test gold finger and an electromagnetic shielding body wrapped around the test gold finger, and the test gold finger is respectively connected with the device end pins of the chip to be tested. , The current measuring device is electrically connected, and the electromagnetic shielding body includes a first insulating ring, a shielding inner ring, a second insulating ring, a voltage fast and stable shielding ring, a third insulating ring and a grounding shielding ring, which are arranged in sequence from the inside to the outside. The electromagnetic shielding body The shielding control circuit is connected to the power-on. The shielding control circuit first controls the voltage to quickly stabilize the potential of the shielding ring to be the same as the potential of the test gold finger, and then controls the potential of the inner shield to be the same as the potential of the test gold finger until the end of the measurement; the advantage is that the The test connection device can reduce or avoid the influence of the external environment on the test gold finger, and improve the measurement accuracy; it also shortens the measurement time of the fA-level leakage current by the current measurement device, and improves the measurement efficiency.
Description
Technical Field
The invention relates to a test connection device for current, in particular to a test connection device for testing fA-level current in mass production.
Background
At present, according to the requirements of working application scenes and the like, only a very small leakage current is allowed to exist in device pins of chips such as an operational amplifier and the like when the chip works, and the leakage current is of an fA level generally. For the fA-level leakage current, the leakage current is usually measured by a technical means in an experimental environment at present, and in an actual mass production test, because the leakage current is very weak, and the distance between the chip to be tested and the current measuring device is long, the measurement precision of the leakage current of the chip to be tested by the current measuring device is deteriorated due to the environmental influence, so that the leakage current cannot be effectively detected, and the requirement of the mass production test is difficult to meet.
Disclosure of Invention
The invention aims to solve the technical problem of providing a test connection device for mass production test of fA-level current, which can reduce or even avoid the influence of external environment on test connection golden fingers during detection, meet the measurement requirement of fA-level leakage current during mass production, and improve the efficiency and reliability of mass production test.
The technical scheme adopted by the invention for solving the technical problems is as follows: a test connection device for mass production test fA level current is used for connecting a chip to be tested and a current measuring device, and comprises a test golden finger and an electromagnetic shielding body wrapped around the test golden finger, one end of the test golden finger is electrically connected with a device terminal pin of the chip to be tested, the other end of the test golden finger is electrically connected with the current measuring device, the electromagnetic shielding body comprises a first insulating ring, a shielding inner ring, a second insulating ring, a voltage rapid and stable shielding ring, a third insulating ring and a grounding shielding ring which are sequentially arranged from inside to outside, the electromagnetic shielding body is electrically connected with a shielding control circuit, the shielding control circuit enables the grounding shielding ring to be always in a grounding state, and during testing, the shielding control circuit controls the potential of the voltage rapid and stable shielding ring to be the same as the potential of the test golden finger, and then controlling the potential of the shielding inner ring to be the same as the potential of the testing golden finger until the measurement is finished.
Furthermore, the first insulating ring, the shielding inner ring, the second insulating ring, the voltage rapid stabilization shielding ring, the third insulating ring and the grounding shielding ring are concentrically distributed with the testing golden finger.
Furthermore, the shielding control circuit comprises a sample-and-hold circuit, a shielding inner ring control circuit and a stable shielding ring control circuit, wherein the shielding inner ring control circuit and the stable shielding ring control circuit are electrically connected with the sample-and-hold circuit, the sample-and-hold circuit is used for sampling and holding a shielding driving signal, and the shielding inner ring control circuit is electrically connected with the shielding inner ring and is used for controlling the potential of the shielding inner ring to be the same as that of the testing golden finger; the stable shielding ring control circuit is electrically connected with the voltage rapid stable shielding ring and is used for controlling the electric potential of the voltage rapid stable shielding ring to be rapidly stabilized at the same electric potential of the test golden finger.
Furthermore, the sample-and-hold circuit comprises a first NMOS tube, a second NMOS tube and a fifth capacitor, the drain terminal of the first NMOS tube is electrically connected to the shield driving signal, the source terminal of the first NMOS tube is electrically connected to the source terminal of the second NMOS tube, the first terminal of the fifth capacitor, the shield inner-ring control circuit and the stable shield ring control circuit, respectively, and the drain terminal of the second NMOS tube and the second terminal of the fifth capacitor are both grounded.
Furthermore, the stable shielding ring control circuit includes a first operational amplifier, a first capacitor, a second capacitor, a third capacitor, a first resistor and a second resistor, wherein the in-phase terminal of the first operational amplifier is electrically connected to the first terminal of the fifth capacitor, the source terminal of the first NMOS transistor and the source terminal of the second NMOS transistor, the positive power terminal of the first operational amplifier is grounded through the second capacitor, the negative power terminal of the first operational amplifier is grounded through the first capacitor, the inverting terminal of the first operational amplifier is electrically connected to one terminal of the second resistor, the other terminal of the second resistor is electrically connected to the output terminal of the first operational amplifier and one terminal of the first resistor, the other terminal of the first resistor is electrically connected to one terminal of the third capacitor to form a stable shielding ring control output terminal, the control output end of the stable shielding ring is electrically connected with the voltage rapid stable shielding ring, and the other end of the third capacitor is grounded.
Furthermore, the shielding inner ring control circuit comprises a square wave signal generating circuit and a constant voltage generating circuit, and the constant voltage generating circuit is respectively and electrically connected with the square wave signal generating circuit and the sampling and holding circuit.
Furthermore, the square wave signal generating circuit comprises a second operational amplifier, a fourth capacitor, a third resistor, a first variable resistor, a second variable resistor and a third NMOS tube, the in-phase end of the second operational amplifier is respectively and electrically connected with one end of the third resistor and one end of the first variable resistor, the other end of the third resistor is grounded, the other end of the first variable resistor is electrically connected with the output end of the second operational amplifier and the drain end of the third NMOS tube, the inverting terminal of the second operational amplifier is electrically connected with one end of the second variable resistor and one end of the fourth capacitor, the other end of the fourth capacitor is grounded, the other end of the second variable resistor is electrically connected with the output end of the second operational amplifier and the drain end of the third NMOS tube, and the source end of the third NMOS tube is electrically connected with the constant voltage generating circuit.
Furthermore, the constant voltage generating circuit includes a third operational amplifier, a fourth NMOS transistor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a fifth resistor, and a sixth resistor, wherein a non-inverting terminal of the third operational amplifier is electrically connected to a first terminal of the fifth capacitor, a source terminal of the first NMOS transistor, and a source terminal of the second NMOS transistor, an inverting terminal of the third operational amplifier is electrically connected to one terminal of the fifth resistor, another terminal of the fifth resistor is electrically connected to an output terminal of the third operational amplifier and one terminal of the sixth resistor, a negative terminal of a power supply of the third operational amplifier is grounded via the sixth capacitor, a positive terminal of the power supply of the third operational amplifier is grounded via the seventh capacitor, and another terminal of the sixth resistor is electrically connected to one terminal of the eighth capacitor and a drain terminal of the fourth NMOS transistor, the other end of the eighth capacitor is grounded, a source terminal of the fourth NMOS tube is electrically connected with a source terminal of the third NMOS tube to form a shielding inner ring control output end, and the shielding inner ring control output end is electrically connected with the shielding inner ring.
Furthermore, the second operational amplifier and the third operational amplifier both adopt high-bandwidth operational amplifiers, each high-bandwidth operational amplifier comprises a voltage comparator, a CMOS input operational amplifier, a JFET input operational amplifier, a phase inverter, a push-pull output circuit and a ninth capacitor, the in-phase end of the JFET input operational amplifier, the in-phase end of the CMOS input operational amplifier and the first voltage negative end of the voltage comparator are connected with each other to form the in-phase end of the high-bandwidth operational amplifier, the inverting end of the JFET input operational amplifier, the inverting end of the CMOS input operational amplifier and the second voltage negative end of the voltage comparator are connected with each other to form the inverting end of the high-bandwidth operational amplifier, the voltage positive end of the voltage comparator is connected with a reference voltage, and the output end of the voltage comparator and the enabling end of the JFET input operational amplifier, The input end of the phase inverter is electrically connected, and the output end of the phase inverter is electrically connected with the enable end of the CMOS input operational amplifier; the output end of the JFET input operational amplifier and the output end of the CMOS input operational amplifier are electrically connected with the input end of the push-pull output circuit and one end of the ninth capacitor, and the output end of the push-pull output circuit and the other end of the ninth capacitor are mutually connected to form the output end of the high-bandwidth operational amplifier.
Furthermore, the shielding driving signal is a voltage signal of an input protection terminal pin of the chip to be tested, or a voltage signal for sampling the test golden finger.
Compared with the prior art, the invention has the advantages that because the electromagnetic shield is wrapped and surrounded outside the test golden finger, the influence of the external environment on the test golden finger can be reduced or avoided through the electromagnetic shield, and the measurement precision is improved; the electromagnetic shield is electrically connected with a shielding control circuit, and when the leakage current flowing through the device terminal pin on the chip to be tested is measured through the testing golden finger, the potential of the voltage rapid-stabilization shielding ring is rapidly stabilized to the same potential as that of the testing golden finger through the shielding control circuit; after the electric potential of the voltage rapid stabilization shielding ring is kept to be the same as the electric potential of the testing golden finger, the shielding control circuit controls the electric potential of the shielding inner ring to be consistent with the electric potential of the testing golden finger until the measurement of the leakage current is finished, so that the steady-state time during the whole measurement is greatly shortened, the time of the current measuring device for measuring the fA-level leakage current through the testing golden finger is shortened, and the measuring efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of connection in use when the present invention is used to measure a chip under test;
FIG. 2 is a top view of the electromagnetic shield of the present invention mated with a test golden finger;
FIG. 3 is a cross-sectional view of FIG. 2;
FIG. 4 is a circuit schematic of the mask control circuit of the present invention;
FIG. 5 is a diagram illustrating a timing control circuit generating timing control signals according to the present invention;
FIG. 6 is a diagram illustrating timing control signals according to the present invention;
fig. 7 is a circuit block diagram of a high bandwidth operational amplifier of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
As shown in the figure, the test connecting device for mass production test of fA level current is used for connecting a chip 1 to be tested and a current measuring device 2, the chip 1 to be tested can be a commonly used chip such as an operational amplifier, the current measuring device 2 is a conventional device, the test connecting device comprises a test golden finger 3 and an electromagnetic shielding body 4 wrapped around the test golden finger 3, one end of the test golden finger 3 is electrically connected with a device terminal pin 5 of the chip 1 to be tested, the other end of the test golden finger 3 is electrically connected with the current measuring device 2, the chip 1 to be tested is generally provided with a plurality of device terminal pins 5, the number of the test golden finger 3 is generally equal to that of the device terminal pins 5 on the chip 1 to be tested, when in mass production test, the chip 1 to be tested is placed in a test station, the chip 1 to be tested is electrically connected with the test golden finger 3 on the test connecting device through the device terminal pins 5 in a one-to-one correspondence manner, if only the leakage current measurement is needed to be performed on part of the device terminal pins 5 on the chip 1 to be tested, the electromagnetic shields 4 can be arranged on the testing golden fingers 3 electrically connected with the part of the device terminal pins 5 in a one-to-one correspondence manner, other testing golden fingers 3 can adopt the existing common form, and of course, the electromagnetic shields 4 can be arranged on all the testing golden fingers 3;
the electromagnetic shield 4 comprises a first insulating ring 41, a shielding inner ring 42, a second insulating ring 43, a voltage rapid stabilizing shielding ring 44, a third insulating ring 45 and a grounding shielding ring 46 which are arranged from inside to outside in sequence, as shown in fig. 3, the first insulating ring 41, the shielding inner ring 42, the second insulating ring 43, the voltage fast-stabilizing shielding ring 44, the third insulating ring 45 and the grounding shielding ring 46 are all concentrically distributed with the testing gold finger 3, the shielding inner ring 42, the voltage fast-stabilizing shielding ring 44 and the grounding shielding ring 46 can adopt the existing common shielding material, the first insulating ring 41, the second insulating ring 43 and the third insulating ring 45 can adopt the existing common insulating and isolating material, the shielding inner ring 42 is insulated and isolated from the testing gold finger 3 by the first insulating ring 41, the shielding inner ring 42 is insulated and isolated from the voltage fast-stabilizing shielding ring 44 by the second insulating ring 43, and the grounding shielding ring 46 is insulated and isolated from the voltage fast-stabilizing shielding ring 44 by the third insulating ring 45; in addition, the electromagnetic shielding body 4 may be set to be flat to reduce the protruding height of the electromagnetic shielding body 4 on the circuit board, and for the test golden finger 3, the width of one end connected with the device terminal pin 5 of the chip 1 to be tested is smaller, and the width thereof gradually increases along the direction pointing to the other end of the test golden finger 3, as shown in fig. 2.
By arranging the electromagnetic shielding body 4 on the testing golden finger 3, the influence of the testing golden finger 3 on the environment in the test can be reduced, and the measurement requirement of fA-level leakage current in mass production is met. In order to improve the measurement efficiency in mass production, the electromagnetic shield 4 is also electrically connected with a shielding control circuit, the grounding shielding ring 46 is grounded, the shielding control circuit enables the grounding shielding ring 46 to be always in a grounded state, and during testing, the shielding control circuit firstly controls the potential of the voltage fast-stabilizing shielding ring 44 to be fast stabilized to the same potential of the test golden finger 3, and then controls the potential of the shielding inner ring 42 to be the same as the potential of the test golden finger 3 until the measurement of leakage current is finished; specifically, after the potential of the voltage fast-stabilizing shielding ring 44 is the same as the potential of the surrounded testing golden finger 3, the shielding control circuit makes the potential of the voltage fast-stabilizing shielding ring 44 be stabilized at the same potential as the testing golden finger 3, then the shielding control circuit makes the potential of the shielding inner ring 42 be the same as the potential of the testing golden finger 3, and when the potentials of the shielding inner ring 42 and the voltage fast-stabilizing shielding ring 44 are both the same as the potentials of the surrounded testing golden finger 3, stable and accurate measurement of the fA-level leakage current of the device terminal pin 5 can be realized; and can make electromagnetic shield 4 get into the shielding steady state fast, can shorten the steady state time when whole measurement promptly greatly to shorten current-measuring device 2 and through testing golden finger 3 to the time of corresponding fA level leakage current measurement, improve measurement of efficiency.
The shielding control circuit comprises a sampling holding circuit 6, a shielding inner ring control circuit and a stable shielding ring control circuit 7, wherein the shielding inner ring control circuit and the stable shielding ring control circuit are electrically connected with the sampling holding circuit 6, and the stable shielding ring control circuit 7 is electrically connected with the voltage rapid-stabilizing shielding ring 44 and is used for controlling the electric potential of the voltage rapid-stabilizing shielding ring 44 to be rapidly stabilized at the same electric potential of the test golden finger 3; the shielding inner ring control circuit is electrically connected with the shielding inner ring 42, a capacitor formed by the shielding inner ring 42, the first insulating ring 41 and the testing golden finger 3 is charged through a square wave signal output by the shielding inner ring control circuit, after the charging is finished, the shielding inner ring control circuit closes the output square wave signal, and loads a shielding inner ring control voltage which is output constantly onto the shielding inner ring 42, so that the potential of the shielding inner ring 42 is the same as that of the testing golden finger 3 until the leakage current measurement is finished; the sampling and holding circuit 6 is used for sampling the shielding driving signal and controlling the working states of the shielding inner ring control circuit and the stable shielding ring control circuit 7 according to the sampling state of the shielding driving signal; specifically, the shielding driving signal may be a voltage signal of an input protection pin of the chip 1 to be tested, or a voltage signal sampled by the testing golden finger 3, and when the chip 1 to be tested has the input protection pin, the shielding driving signal is a voltage signal of the input protection pin of the chip 1 to be tested, and the specific method is as follows: in the chip 1 to be tested, the voltage of the input protection terminal pin is configured to be consistent with the voltage of the test golden finger 3; when the chip 1 to be tested is not provided with the input protection pin, the voltage signal of the test gold finger 3 can be obtained by the existing method (for example, by adopting circuits such as a buffer) and the specific situation can be determined according to the actual situation. Therefore, different shielding driving signals are obtained by the sample-and-hold circuit 6 according to different specific packaging forms of the chip 1 to be tested, but the potentials of the shielding inner ring 42 and the voltage fast-stabilizing shielding ring 44 can be controlled according to the obtained shielding driving signals and are finally the same as the potential of the testing golden finger 3, so as to meet the requirement of measuring the fA-level leakage current.
Specifically, as shown in fig. 4, the sample-and-hold circuit 6 includes a first NMOS transistor Q1, a second NMOS transistor Q2, and a fifth capacitor C5, a drain terminal of the first NMOS transistor Q1 is electrically connected to the shielding driving signal, a source terminal of the first NMOS transistor Q1 is electrically connected to a source terminal of the second NMOS transistor Q2, a first terminal of the fifth capacitor C5, the shielding inner-ring control circuit, and the stable shielding ring control circuit, and a drain terminal of the second NMOS transistor Q2 and a second terminal of the fifth capacitor C5 are both grounded; when the first NMOS transistor Q1 is controlled to be switched on and the second NMOS transistor Q2 is controlled to be switched off, the fifth capacitor C5 is charged by the shielding driving signal; when the first NMOS transistor Q1 and the second NMOS transistor Q2 are both turned off, the shielding inner-loop control circuit and the stable shielding-loop control circuit 7 are driven to be in corresponding working states by the capacitor voltage of the fifth capacitor C5; when the first NMOS transistor Q1 is turned off and the second NMOS transistor Q2 is turned on, the fifth capacitor C5 is discharged, and after the fifth capacitor C5 is discharged, the working states of the shielding inner ring control circuit and the stable shielding ring control circuit 7 are turned off, and the corresponding potentials on the shielding inner ring 42 and the voltage fast-stabilizing shielding ring 44 are also set to zero.
The stable shielding loop control circuit 7 comprises a first operational amplifier U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first resistor R1 and a second resistor R2, wherein the in-phase terminal of the first operational amplifier U1 is electrically connected with the first terminal of the fifth capacitor C5, the source terminal of the first NMOS transistor Q1 and the source terminal of the second NMOS transistor Q2, the positive power terminal of the first operational amplifier U1 is grounded through the second capacitor C2, the negative power terminal of the first operational amplifier U1 is grounded through the first capacitor C1, the inverting terminal of the first operational amplifier U1 is electrically connected with one terminal of the second resistor R2, the other terminal of the second resistor R2 is electrically connected with the output terminal of the first operational amplifier U1 and one terminal of the first resistor R1, the other terminal of the first resistor R1 is electrically connected with one terminal of the third capacitor C3 to form a stable shielding loop control output terminal Vout, and the stable shielding loop control output terminal 1 is electrically connected with the stable shielding loop 1, the other end of the third capacitor C3 is grounded;
the first operational amplifier U1 can be a high-precision operational amplifier commonly used in the art, and can also be a high-bandwidth operational amplifier. When the first NMOS transistor Q1 and the second NMOS transistor Q2 in the sample-and-hold circuit 6 are both in an off state, the capacitance voltage of the fifth capacitor C5 is loaded to the non-inverting terminal of the first operational amplifier U1, and at this time, the voltage of the voltage fast-stabilization shielding ring 44 is the same as the voltage of the test golden finger 3; when the fifth capacitor C5 is in the discharging state, the stable shielding loop control circuit is in the non-operating state. As can be seen from fig. 4, the first operational amplifier U1 operates in a voltage follower state, so that a voltage consistent with the mask driving signal can be obtained by stabilizing the mask loop control output terminal Vout 1.
The shielding inner ring control circuit comprises a square wave signal generating circuit 8 and a constant voltage generating circuit 9, wherein the constant voltage generating circuit 9 is respectively electrically connected with the square wave signal generating circuit 8 and the sampling holding circuit 6, and specifically:
the square wave signal generating circuit 8 comprises a second operational amplifier U2, a fourth capacitor C4, a third resistor R3, a first variable resistor R9, a second variable resistor R10 and a third NMOS tube Q3, wherein the in-phase end of the second operational amplifier U2 is electrically connected with one end of the third resistor R3 and one end of the first variable resistor R9 respectively, the other end of the third resistor R3 is grounded, the other end of the first variable resistor R9 is electrically connected with the output end of the second operational amplifier U2 and the drain end of the third NMOS tube Q3, the inverting end of the second operational amplifier U2 is electrically connected with one end of the second variable resistor R10 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, the other end of the second variable resistor R10 is electrically connected with the output end of the second operational amplifier U2 and the drain end of the third NMOS tube Q3, and the source end of the third NMOS tube Q3 is electrically connected with a constant voltage generating circuit;
the constant voltage generating circuit 9 includes a third operational amplifier U3, a fourth NMOS tube Q4, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a fifth resistor R5 and a sixth resistor R6, wherein the non-inverting terminal of the third operational amplifier U3 is electrically connected to the first terminal of the fifth capacitor C5, the source terminal of the first NMOS tube Q1 and the source terminal of the second NMOS tube Q2, the inverting terminal of the third operational amplifier U3 is electrically connected to one terminal of the fifth resistor R5, the other terminal of the fifth resistor R5 is electrically connected to the output terminal of the third operational amplifier U3 and one terminal of the sixth resistor R6, the negative terminal of the power supply of the third operational amplifier U3 is grounded through the sixth capacitor C6, the positive terminal of the power supply of the third operational amplifier U3 is grounded through the seventh capacitor C3, the other terminal of the sixth resistor R3 is electrically connected to one terminal of the eighth capacitor C3, the Q3 of the fourth NMOS tube Q3, the drain terminal of the fourth NMOS tube Q3 is electrically connected to the ground, the fourth capacitor Q3, the third operational amplifier U3 forms an NMOS tube Q3, and the second NMOS tube Q3, the shield inner loop control output Vout2 is electrically connected to the shield inner loop 42.
The second operational amplifier U2 and the third operational amplifier U3 in the shielding inner ring control circuit adopt the same high bandwidth operational amplifier, the square wave generated by the square wave signal generating circuit 8 can be adjusted through the first variable resistor R9 and the second variable resistor R10, the output state of the square wave signal generating circuit 8 can be controlled through the third NMOS tube Q3, when the third NMOS tube Q3 is turned on and the fourth NMOS tube Q4 is turned off, the square wave signal generated by the square wave signal generating circuit 8 can be loaded to the shielding inner ring 42 through the shielding inner ring control output terminal Vout2, and when the third NMOS tube Q3 is turned off and the fourth NMOS tube Q4 is turned on, the voltage generated by the constant voltage generating circuit 3879 is loaded to the shielding inner ring 42 through the shielding inner ring control output terminal Vout 5; and the constant voltage generating circuit 9 can rapidly make the shielding inner ring 42 obtain the corresponding voltage through the shielding inner ring control output terminal Vout2 by the third operational amplifier U3, i.e. the potential of the shielding inner ring 42 can rapidly rise to the same potential as the test golden finger 3, as can be seen from fig. 4, the third operational amplifier U3 works in the voltage follower state, so that the voltage consistent with the shielding driving signal can be obtained through the shielding inner ring control output terminal Vout 2.
In specific implementation, the working states of the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 are all controlled by corresponding timing control signals, as shown in fig. 5, which is a schematic diagram of generating timing control signals by a timing control circuit, the timing control circuit may adopt a conventional common circuit form, timing signals Q1, Q2, Q3, and Q4 generated by the timing control circuit may respectively correspond to the first NMOS transistor Q1, the second NMOS transistor Q2, the third NMOS transistor Q3, and the fourth NMOS transistor Q4 one to one, specific conditions of the timing signals Q1, Q2, Q3, and Q4 are shown in fig. 6, when the timing signal Q1 is at a high level, the first NMOS transistor Q1 is in a conducting state, and when the timing signal Q2 is at a high level, the second NMOS transistor Q2 is in a conducting state; when the timing signal Q3 is at a high level, the third NMOS transistor Q3 is in a conducting state; when the timing signal Q4 is at a high level, the fourth NMOS transistor Q4 is in a conducting state. Fig. 6 shows a timing diagram of a complete cycle when the fA-level leakage current is measured, and the timing diagram controls the operation of the whole shielding control circuit through the timing control signal, so that the measurement time under a stable condition can be greatly shortened and the measurement efficiency can be improved under the condition that the mass production test of the fA-level leakage current is satisfied.
As shown in fig. 7, the high bandwidth operational amplifier includes a voltage comparator U4, a CMOS input operational amplifier U5, a JFET input operational amplifier U6, an inverter U7, the power supply comprises a push-pull output circuit U8 and a ninth capacitor C9, wherein the in-phase end of a JFET input operational amplifier U6, the in-phase end of a CMOS input operational amplifier U5 and the first voltage negative end of a voltage comparator U4 are connected with each other to form the in-phase end of a high-bandwidth operational amplifier, the inverting end of the JFET input operational amplifier U6, the inverting end of the CMOS input operational amplifier U5 and the second voltage negative end of the voltage comparator U4 are connected with each other to form the inverting end of the high-bandwidth operational amplifier, the voltage positive end of the voltage comparator U4 is connected with a reference voltage Vref, the output end of the voltage comparator U4 is electrically connected with the enable end of the JFET input operational amplifier U6 and the input end of an inverter U7, and the output end of an inverter U7 is electrically connected with the enable end of the CMOS input operational amplifier U5; the output end of the JFET input operational amplifier U6 and the output end of the CMOS input operational amplifier U5 are electrically connected with the input end of the push-pull output circuit U8 and one end of the ninth capacitor C9, and the output end of the push-pull output circuit U8 and the other end of the ninth capacitor C9 are connected with each other to form the output end of the high-bandwidth operational amplifier.
Wherein: the voltage comparator U4, the CMOS input operational amplifier U5 and the JFET input operational amplifier U6 can all adopt the existing common circuit form, and the size of the reference voltage Vref can be selected according to the requirement. The first voltage negative terminal and the second voltage negative terminal of the voltage comparator U4 are common mode voltage signals of the whole high bandwidth operational amplifier, when the common mode voltage signals are lower than the reference voltage Vref, the JFET input operational amplifier U6 is in an operating state, and when the common mode voltage signals are higher than the reference voltage Vref, the CMOS input operational amplifier U5 is in an operating state. In particular, during operation, the operation of the JFET input operational amplifier U6 is used as the reference in the operation region of the high bandwidth operational amplifier, so that the high bandwidth operational amplifier has the characteristics of high bandwidth, high slew rate and the like according to the operation characteristics of the JFET input operational amplifier U6. The push-pull output stage is formed by a push-pull output circuit U8, and the push-pull output circuit U8 may adopt a push-pull output form commonly used in the prior art.
Further, when the first operational amplifier U1 is a high-bandwidth operational amplifier, the circuit form of the high-bandwidth operational amplifier described above may also be employed.
The scope of the present invention includes, but is not limited to, the above embodiments, and the scope of the present invention is defined by the appended claims, and any substitutions, modifications, and improvements that may occur to those skilled in the art are intended to fall within the scope of the present invention.
Claims (10)
1. The utility model provides a test connecting device for volume production test fA level electric current for connect chip and the current measurement device that awaits measuring, its characterized in that includes the test golden finger and wraps up and encircle the test golden finger outer electromagnetic shield body, the one end of test golden finger be connected with the device end foot electricity of chip that awaits measuring, the other end and the current measurement device electricity of test golden finger be connected, the electromagnetic shield body include first insulating ring, shielding inner ring, second insulating ring, the quick stable shield ring of voltage, third insulating ring and the ground connection shield ring that set gradually from inside to outside, the electromagnetic shield body on be connected with shielding control circuit, shielding control circuit make ground connection shield ring be in the ground connection state all the time, and during the test, shielding control circuit control earlier the electric potential of the quick stable shield ring of voltage with the electric potential of test golden finger the same, and then controlling the potential of the shielding inner ring to be the same as the potential of the testing golden finger until the measurement is finished.
2. A test connection for mass production testing of class fA current according to claim 1, wherein: the first insulating ring, the shielding inner ring, the second insulating ring, the voltage rapid stabilization shielding ring, the third insulating ring and the grounding shielding ring are concentrically distributed with the testing golden finger.
3. A test connection for mass production testing of class fA current according to claim 1, wherein: the shielding control circuit comprises a sampling and holding circuit, a shielding inner ring control circuit and a stable shielding ring control circuit, wherein the shielding inner ring control circuit and the stable shielding ring control circuit are electrically connected with the sampling and holding circuit; the stable shielding ring control circuit is electrically connected with the voltage rapid stable shielding ring and is used for controlling the electric potential of the voltage rapid stable shielding ring to be rapidly stabilized at the same electric potential of the test golden finger.
4. A test connection for mass production testing of class fA current according to claim 3, wherein: the sampling holding circuit comprises a first NMOS tube (Q1), a second NMOS tube (Q2) and a fifth capacitor (C5), wherein the drain end of the first NMOS tube (Q1) is electrically connected with a shielding driving signal, the source end of the first NMOS tube (Q1) is respectively electrically connected with the source end of the second NMOS tube (Q2), the first end of the fifth capacitor (C5), the shielding inner ring control circuit and the stable shielding ring control circuit, and the second ends of the second NMOS tube (Q2) and the fifth capacitor (C5) are grounded.
5. A test connection for mass production testing of class fA currents as claimed in claim 4, wherein: the stable shielding loop control circuit comprises a first operational amplifier (U1), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a first resistor (R1) and a second resistor (R2), wherein the same-phase end of the first operational amplifier (U1) is electrically connected with the first end of the fifth capacitor (C5), the source end of a first NMOS transistor (Q1) and the source end of a second NMOS transistor (Q2), the positive power supply end of the first operational amplifier (U1) is grounded through the second capacitor (C2), the negative power supply end of the first operational amplifier (U1) is grounded through the first capacitor (C1), the inverting end of the first operational amplifier (U1) is electrically connected with one end of the second resistor (R2), and the other end of the second resistor (R2) is electrically connected with the first end of the first operational amplifier (U1) and the first output end of the first resistor (R1), the other end of the first resistor (R1) is electrically connected with one end of the third capacitor (C3) to form a stable shielding ring control output end (Vout 1), the stable shielding ring control output end (Vout 1) is electrically connected with the voltage rapid stable shielding ring, and the other end of the third capacitor (C3) is grounded.
6. The test connection device for mass production testing of class fA current of claim 4, wherein: the shielding inner ring control circuit comprises a square wave signal generating circuit and a constant voltage generating circuit, wherein the constant voltage generating circuit is respectively and electrically connected with the square wave signal generating circuit and the sampling and holding circuit.
7. The test connection device for mass production testing of class fA current of claim 6, wherein: the square wave signal generating circuit comprises a second operational amplifier (U2), a fourth capacitor (C4), a third resistor (R3), a first variable resistor (R9), a second variable resistor (R10) and a third NMOS transistor (Q3), wherein the in-phase end of the second operational amplifier (U2) is electrically connected with one end of the third resistor (R3) and one end of the first variable resistor (R9), the other end of the third resistor (R3) is grounded, the other end of the first variable resistor (R9) is electrically connected with the output end of the second operational amplifier (U2) and the drain end of the third NMOS transistor (Q3), the inverting end of the second operational amplifier (U2) is electrically connected with one end of the second variable resistor (R10), one end of the fourth capacitor (C4), the other end of the fourth capacitor (C4) is electrically connected with the ground, and the other end of the second variable resistor (R10) is electrically connected with the output end of the second operational amplifier (U2), The drain terminal of the third NMOS tube (Q3) is electrically connected, and the source terminal of the third NMOS tube (Q3) is electrically connected with the constant voltage generating circuit.
8. The test connection device for mass production testing of class fA current of claim 7, wherein: the constant voltage generating circuit comprises a third operational amplifier (U3), a fourth NMOS tube (Q4), a sixth capacitor (C6), a seventh capacitor (C7), an eighth capacitor (C8), a fifth resistor (R5) and a sixth resistor (R6), wherein the in-phase terminal of the third operational amplifier (U3) is electrically connected with the first terminal of the fifth capacitor (C5), the source terminal of the first NMOS tube (Q1) and the source terminal of the second NMOS tube (Q42), the inverting terminal of the third operational amplifier (U3) is electrically connected with one terminal of the fifth resistor (R5), the other terminal of the fifth resistor (R5) is electrically connected with the output terminal of the third operational amplifier (U3) and one terminal of the sixth resistor (R6), the power supply terminal of the third operational amplifier (U3) is grounded through the positive terminal of the sixth capacitor (C5), and the seventh operational amplifier (U7) is grounded through the seventh capacitor (C59573) of the power supply (C3524), the other end of the sixth resistor (R6) is electrically connected with one end of the eighth capacitor (C8) and the drain end of the fourth NMOS tube (Q4), the other end of the eighth capacitor (C8) is grounded, the source end of the fourth NMOS tube (Q4) is electrically connected with the source end of the third NMOS tube (Q3) to form a shielding inner ring control output end (Vout 2), and the shielding inner ring control output end (Vout 2) is electrically connected with the shielding inner ring.
9. The test connection device for mass production testing of class fA current of claim 8, wherein: the second operational amplifier (U2) and the third operational amplifier (U3) both adopt high bandwidth operational amplifiers, the high bandwidth operational amplifiers comprise a voltage comparator (U4), a CMOS input operational amplifier (U5), a JFET input operational amplifier (U6), an inverter (U7), a push-pull output circuit (U8) and a ninth capacitor (C9), the in-phase end of the JFET input operational amplifier (U6), the in-phase end of the CMOS input operational amplifier (U5) and the first voltage negative end of the voltage comparator (U4) are connected with each other to form the in-phase end of the high bandwidth operational amplifier, the inverting end of the JFET input operational amplifier (U6), the inverting end of the CMOS input operational amplifier (U5) and the second voltage negative end of the voltage comparator (U4) are connected with each other to form the inverting end of the high bandwidth operational amplifier, the positive voltage terminal of the voltage comparator (U4) is connected with a reference voltage (Vref), the output terminal of the voltage comparator (U4) is electrically connected with the enable terminal of the JFET input operational amplifier (U6) and the input terminal of the inverter (U7), and the output terminal of the inverter (U7) is electrically connected with the enable terminal of the CMOS input operational amplifier (U5); the output end of the JFET input operational amplifier (U6) and the output end of the CMOS input operational amplifier (U5) are electrically connected with the input end of the push-pull output circuit (U8) and one end of the ninth capacitor (C9), and the output end of the push-pull output circuit (U8) and the other end of the ninth capacitor (C9) are mutually connected to form the output end of the high-bandwidth operational amplifier.
10. A test connection for mass production testing of class fA current according to claim 3, wherein: the shielding driving signal is a voltage signal of an input protection terminal pin of the chip to be tested or a voltage signal for sampling the testing golden finger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210082049.0A CN114487503A (en) | 2022-01-24 | 2022-01-24 | Test connection device for mass production test of fA-level current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210082049.0A CN114487503A (en) | 2022-01-24 | 2022-01-24 | Test connection device for mass production test of fA-level current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114487503A true CN114487503A (en) | 2022-05-13 |
Family
ID=81474768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210082049.0A Pending CN114487503A (en) | 2022-01-24 | 2022-01-24 | Test connection device for mass production test of fA-level current |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114487503A (en) |
Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1704714A (en) * | 2004-06-03 | 2005-12-07 | 通用电气公司 | Non-contact capacitive sensor and cable with dual layer active shield |
| CN2930006Y (en) * | 2006-05-26 | 2007-08-01 | 建舜电子制造股份有限公司 | Connector with EMI reduction structure |
| CN101609113A (en) * | 2009-06-11 | 2009-12-23 | 浙江大学 | Device and method for non-contact conductivity measurement based on double-shielded structure and series resonance |
| CN201417856Y (en) * | 2009-04-29 | 2010-03-03 | 艾默生网络能源有限公司 | Shielding device for input and output ports of gold fingers of electrical appliances |
| CN201804696U (en) * | 2010-05-04 | 2011-04-20 | 中国电力科学研究院 | Ultra-high voltage isoelectric shielding CVT |
| CN102074284A (en) * | 2010-12-29 | 2011-05-25 | 金坛市金鹿电缆材料有限公司 | Dual-shielding flame-retardant nuclear power data cable |
| CN203026233U (en) * | 2013-01-04 | 2013-06-26 | 东营嘉宝石油科技有限公司 | Cable special for clinometer |
| CN103293413A (en) * | 2013-05-19 | 2013-09-11 | 国家电网公司 | Special high-voltage testing device for transformers |
| CN103563493A (en) * | 2011-06-09 | 2014-02-05 | 苹果公司 | Electromagnetic shielding structure for shielding components on a substrate |
| CN204595060U (en) * | 2015-05-19 | 2015-08-26 | 国家电网公司 | Leakage current measurement device |
| CN204614513U (en) * | 2015-03-17 | 2015-09-02 | 江苏亨通电子线缆科技有限公司 | High voltage power cables for electric vehicles |
| CN205050682U (en) * | 2015-09-26 | 2016-02-24 | 嘉善华瑞赛晶电气设备科技有限公司 | Cold type solenoid in double -shielded equipotential |
| CN105960157A (en) * | 2016-07-06 | 2016-09-21 | 武汉华星光电技术有限公司 | Electromagnetic shielding protection film and FPC (flexible printed circuit) |
| CN205670164U (en) * | 2016-06-20 | 2016-11-02 | 广州供电局有限公司 | Anti-electromagneticinterference interference system for leakage current monitoring |
| CN205888352U (en) * | 2016-06-28 | 2017-01-18 | 善测（天津）科技有限公司 | Initiatively shield formula electric capacity along with high measuring device |
| CN106597242A (en) * | 2017-02-09 | 2017-04-26 | 北京长城华冠汽车科技股份有限公司 | High-voltage line insulation detecting device |
| CN106872752A (en) * | 2015-12-14 | 2017-06-20 | 全球能源互联网研究院 | A kind of capacitance type potential transformer |
| CN208508137U (en) * | 2018-07-23 | 2019-02-15 | 沈阳圣仁电子科技有限公司 | High frequency probe double shield copper sheathing |
| CN110823316A (en) * | 2019-10-25 | 2020-02-21 | 德阳市新泰自动化仪表有限公司 | Capacitance signal detection circuit with interference shielding function |
| CN210349379U (en) * | 2019-09-17 | 2020-04-17 | 安徽电缆股份有限公司 | Instrument cable for third-generation nuclear power station |
| CN212161342U (en) * | 2020-06-19 | 2020-12-15 | 三元科技（深圳）有限公司 | Cable with shielding signal function |
| CN112534554A (en) * | 2018-08-08 | 2021-03-19 | 琳得科株式会社 | Terminal protection tape and method for manufacturing semiconductor device with electromagnetic wave shielding film |
| CN113067209A (en) * | 2021-02-05 | 2021-07-02 | 武汉英飞光创科技有限公司 | Shielding structure and shielding method for connecting optical module gold finger end |
| CN113393894A (en) * | 2021-05-31 | 2021-09-14 | 西安理工大学 | Voltage-current characteristic testing system of resistive random access memory under irradiation environment |
-
2022
- 2022-01-24 CN CN202210082049.0A patent/CN114487503A/en active Pending
Patent Citations (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1704714A (en) * | 2004-06-03 | 2005-12-07 | 通用电气公司 | Non-contact capacitive sensor and cable with dual layer active shield |
| CN2930006Y (en) * | 2006-05-26 | 2007-08-01 | 建舜电子制造股份有限公司 | Connector with EMI reduction structure |
| CN201417856Y (en) * | 2009-04-29 | 2010-03-03 | 艾默生网络能源有限公司 | Shielding device for input and output ports of gold fingers of electrical appliances |
| CN101609113A (en) * | 2009-06-11 | 2009-12-23 | 浙江大学 | Device and method for non-contact conductivity measurement based on double-shielded structure and series resonance |
| CN201804696U (en) * | 2010-05-04 | 2011-04-20 | 中国电力科学研究院 | Ultra-high voltage isoelectric shielding CVT |
| CN102074284A (en) * | 2010-12-29 | 2011-05-25 | 金坛市金鹿电缆材料有限公司 | Dual-shielding flame-retardant nuclear power data cable |
| CN103563493A (en) * | 2011-06-09 | 2014-02-05 | 苹果公司 | Electromagnetic shielding structure for shielding components on a substrate |
| CN203026233U (en) * | 2013-01-04 | 2013-06-26 | 东营嘉宝石油科技有限公司 | Cable special for clinometer |
| CN103293413A (en) * | 2013-05-19 | 2013-09-11 | 国家电网公司 | Special high-voltage testing device for transformers |
| CN204614513U (en) * | 2015-03-17 | 2015-09-02 | 江苏亨通电子线缆科技有限公司 | High voltage power cables for electric vehicles |
| CN204595060U (en) * | 2015-05-19 | 2015-08-26 | 国家电网公司 | Leakage current measurement device |
| CN205050682U (en) * | 2015-09-26 | 2016-02-24 | 嘉善华瑞赛晶电气设备科技有限公司 | Cold type solenoid in double -shielded equipotential |
| CN106872752A (en) * | 2015-12-14 | 2017-06-20 | 全球能源互联网研究院 | A kind of capacitance type potential transformer |
| CN205670164U (en) * | 2016-06-20 | 2016-11-02 | 广州供电局有限公司 | Anti-electromagneticinterference interference system for leakage current monitoring |
| CN205888352U (en) * | 2016-06-28 | 2017-01-18 | 善测（天津）科技有限公司 | Initiatively shield formula electric capacity along with high measuring device |
| CN105960157A (en) * | 2016-07-06 | 2016-09-21 | 武汉华星光电技术有限公司 | Electromagnetic shielding protection film and FPC (flexible printed circuit) |
| CN106597242A (en) * | 2017-02-09 | 2017-04-26 | 北京长城华冠汽车科技股份有限公司 | High-voltage line insulation detecting device |
| CN208508137U (en) * | 2018-07-23 | 2019-02-15 | 沈阳圣仁电子科技有限公司 | High frequency probe double shield copper sheathing |
| CN112534554A (en) * | 2018-08-08 | 2021-03-19 | 琳得科株式会社 | Terminal protection tape and method for manufacturing semiconductor device with electromagnetic wave shielding film |
| CN210349379U (en) * | 2019-09-17 | 2020-04-17 | 安徽电缆股份有限公司 | Instrument cable for third-generation nuclear power station |
| CN110823316A (en) * | 2019-10-25 | 2020-02-21 | 德阳市新泰自动化仪表有限公司 | Capacitance signal detection circuit with interference shielding function |
| CN212161342U (en) * | 2020-06-19 | 2020-12-15 | 三元科技（深圳）有限公司 | Cable with shielding signal function |
| CN113067209A (en) * | 2021-02-05 | 2021-07-02 | 武汉英飞光创科技有限公司 | Shielding structure and shielding method for connecting optical module gold finger end |
| CN113393894A (en) * | 2021-05-31 | 2021-09-14 | 西安理工大学 | Voltage-current characteristic testing system of resistive random access memory under irradiation environment |
Non-Patent Citations (2)
| Title |
|---|
| 李希胜，王绍纯: "自动检测技术", vol. 1, 31 July 2014, 冶金工业出版社, pages: 293 - 299 * |
| 马忠丽，周雪梅，蔡成涛: "传感器及信号检测转换技术", vol. 1, 31 October 2016, 哈尔滨工程大学出版社, pages: 168 - 170 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9632126B2 (en) | Circuit of measuring leakage current in a semiconductor integrated circuit | |
| CN103424686A (en) | System and method for testing an integrated circuit | |
| CN114113967A (en) | Source measurement unit test system and test method | |
| TW201405137A (en) | Testing circuit for inductance | |
| CN114487503A (en) | Test connection device for mass production test of fA-level current | |
| CN115508735A (en) | Ripple voltage generation method, ripple power supply circuit and power supply ripple test system | |
| CN214409241U (en) | Device for measuring and calculating board-level chip leakage current by using line impedance | |
| CN116840570B (en) | Pseudo-differential capacitance detection circuit and detection method | |
| JPH10124159A (en) | Voltage impressing circuit | |
| CN104485818A (en) | DC/DC (direct current to direct current) converter with testing modes | |
| CN118884162A (en) | A power semiconductor device leakage current measurement circuit and measurement method | |
| CN220691047U (en) | Test circuits and test equipment for semiconductor devices | |
| Li et al. | Design and experiments of voltage sensor based on electric field coupling principle and differential input structure | |
| CN116298759B (en) | Gate charge test circuit | |
| CN220064275U (en) | Transconductance parameter test circuit and test system | |
| CN113406410B (en) | A transmission gate-based radio frequency signal generation system and method | |
| CN105675960A (en) | Apparatus and method for measuring open-circuit voltage of piezoelectric device | |
| CN108051641A (en) | For the measuring circuit of measuring loop resistance | |
| CN102447466B (en) | IO (Input/Output) circuit for accurate pull-down current | |
| CN102520238A (en) | Intelligent programmable-control microcurrent measurement display system | |
| Liang et al. | Analysis of temperature effect on electromagnetic susceptibility of microcontroller | |
| KR100231649B1 (en) | A test board having a capacitor charging circuit and a test method using the test board | |
| CN219574293U (en) | Interelectrode voltage test circuit and test system | |
| CN219609077U (en) | Dielectric loss measuring device of high-voltage capacitive equipment | |
| CN112327991A (en) | Current source circuit and signal conversion chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information |
Inventor after: Cheng Jinxing Inventor after: Wang Qingbo Inventor after: Yu Ai Inventor after: Wen Weiwei Inventor after: Wu Youpeng Inventor before: Cheng Jinxing Inventor before: Feng Yufang Inventor before: Wang Qingbo Inventor before: Yu Ai Inventor before: Wen Weiwei Inventor before: Wu Youpeng |
|
| CB03 | Change of inventor or designer information |