CN114460407A - Simulation circuit breaker test device - Google Patents

Abstract

The invention discloses an analog circuit breaker testing device, comprising a controller, an instruction adjustment unit and a test control management unit. The instruction adjustment unit is used to adjust and process a control instruction signal issued by the controller, and includes an instruction amplification notch conditioning circuit and a stability control unit. Conditioning circuit; the command amplifying notch conditioning circuit includes operational amplifiers AR1, AR2 and AR3. The non-inverting input end of the operational amplifier AR1 is connected to one end of the resistor R1 and the analog command signal output end of the controller through the capacitor C1, and passes through the notch component. Connected to the non-inverting input terminal of the operational amplifier AR3, the stable conditioning circuit is used to stabilize the amplitude of the output signal of the command amplification notch conditioning circuit, and then send it to the test control management unit after being stabilized by buffering; the invention effectively eliminates external power and The interference of environmental factors on the command signal ensures the stability and accuracy of the analog control command signal issuing process, thereby effectively improving the validity of the test results of the analog circuit breaker.

Description

Simulation circuit breaker test device

technical field

The invention relates to the technical field of simulated circuit breakers, in particular to a test device for simulated circuit breakers.

Background technique

As an important link in the monitoring of safe and reliable operation of the power system, the secondary protection relay device is also particularly important for its own operation and judgment reliability. Therefore, it is very important to perform verification tests on the secondary relay protection device used in the power system. . At present, the analog circuit breaker test device has realized automatic detection. For example, the application number is 201811282579.X, and the patent name is a Chinese invention patent of "a human-computer interaction test device for a simulated circuit breaker". The invention provides a simulated circuit breaker man-machine The interactive test device realizes the human-computer interaction test according to the different functional test requirements of the board to be tested, especially the tester cannot test the resources that the tester cannot directly define. In addition to the problems of incomplete testing due to human factors, 5 kinds of modular switching of simulated loads are proposed, and the testable load properties of the test device are increased. In the process of automatic testing, since the control commands issued by the controller will be interfered by external power supply and environmental factors, it is easy to cause instability and imbalance of the analog control command signal, resulting in control failure or error, which seriously affects the test equipment. Stability and accuracy.

Therefore, the present invention provides a new solution to solve this problem.

SUMMARY OF THE INVENTION

In view of the above situation, in order to overcome the defects of the prior art, the purpose of the present invention is to provide an analog circuit breaker testing device.

The technical solution is as follows: a simulated circuit breaker testing device includes a controller, an instruction adjustment unit and a test control management unit, and the instruction adjustment unit is used to adjust and process the control instruction signal issued by the controller, including an instruction Amplifying notch conditioning circuit and stable conditioning circuit; the instruction amplification notch conditioning circuit includes operational amplifiers AR1, AR2 and AR3, and the non-inverting input end of operational amplifier AR1 is connected to one end of resistor R1 and the controller's terminal through capacitor C1. The output terminal of the analog command signal is connected to the non-inverting input terminal of the operational amplifier AR3 through the notch component, the other terminal of the resistor R1 is grounded, and the inverting input terminal and the input terminal of the operational amplifier AR1 are connected to the inverting terminal of the operational amplifier AR2 through the resistor R2. The phase input terminal, the inverting input terminal and output terminal of the operational amplifier AR3 are connected to the non-inverting input terminal of the operational amplifier AR2 and one end of the varistor RP1 through the resistor R4, the other end of the varistor RP1 is grounded with the sliding terminal, and the output of the operational amplifier AR2 The terminal is connected to the input terminal of the stable conditioning circuit, and is connected to the inverting input terminal of the operational amplifier AR2 through the parallel resistor R5 and capacitor C4; the stable conditioning circuit is used to amplify the output signal of the notch conditioning circuit for the command Amplitude adjustment is carried out, and it is sent to the test control management unit after being stabilized by buffering.

Preferably, the stable conditioning circuit includes a MOS transistor Q1, the drain of the MOS transistor Q1 is connected to one end of the resistor R6 and the output end of the operational amplifier AR2, the gate of the MOS transistor Q1 is connected to the other end of the resistor R6, and is connected to the other end of the resistor R6 in parallel. Resistor R7 and capacitor C5 are grounded, the source of MOS transistor Q1 is connected to one end of resistor R9 and the command signal input end of the test control management unit through parallel resistor R8 and capacitor C6, and the other end of resistor R9 is grounded.

Preferably, the wave trap component includes an inductor L1, a resistor R3, and capacitors C2 and C3. One ends of the inductor L1, the resistor R3 and the capacitor C2 are connected to the non-inverting input end of the operational amplifier AR1, and the other ends of the inductor L1 and the capacitor C2 are connected to the op amp AR1. The non-inverting input of the amplifier AR3, the other end of the resistor R3 is grounded through the capacitor C3.

Preferably, the controller selects an FPGA control processing module.

Through the above technical solutions, the beneficial effects of the present invention are:

1. The command amplifying notch conditioning circuit amplifies the analog command signal, and the operational amplifier AR1 and AR2 are connected in series to amplify the analog command signal step by step to avoid the electrical interference of the previous stage and ensure the continuous and stable signal output;

2. There is also a notch component between the op amps AR1 and AR2. The RLC notch filter principle is used to eliminate the power frequency noise in the analog command, and the external power supply noise interference is well suppressed, thereby improving the command control accuracy;

3. Use the op amp AR3 to follow and amplify the signal after the notch, and use the op amp subtraction principle to offset the op amp offset voltage at the non-inverting input of the op amp AR2, thereby suppressing the zero drift of the op amp and effectively avoiding the generation of command signal amplification dissonance;

4. The present invention adjusts the analog command signal issued by the controller by setting the command adjustment unit, effectively eliminating the interference of the external power supply and environmental factors on the command signal, and ensuring the stability and accuracy of the process of issuing the analog control command signal, This effectively improves the validity of the simulated circuit breaker test results.

Description of drawings

FIG. 1 is a circuit schematic diagram of the present invention.

Detailed ways

The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to FIG. 1 . The structural contents mentioned in the following embodiments are all taken as reference to the accompanying drawings.

Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

An analog circuit breaker test device includes a controller, an instruction adjustment unit and a test control management unit. The instruction adjustment unit is used to adjust and process the control instruction signal issued by the controller, including an instruction amplification notch conditioning circuit and a stable conditioning circuit.

As shown in Figure 1, the command amplification notch conditioning circuit includes operational amplifiers AR1, AR2 and AR3. The non-inverting input end of the operational amplifier AR1 is connected to one end of the resistor R1 and the analog command signal output end of the controller through the capacitor C1. The notch component is connected to the non-inverting input terminal of the operational amplifier AR3, the other end of the resistor R1 is grounded, the inverting input terminal and the input terminal of the operational amplifier AR1 are connected to the inverting input terminal of the operational amplifier AR2 through the resistor R2, and the operational amplifier AR3 The inverting input terminal and the output terminal of the AR2 are connected to the non-inverting input terminal of the operational amplifier AR2 and one end of the varistor RP1 through the resistor R4. , and connect the inverting input terminal of the op amp AR2 through the parallel resistor R5 and capacitor C4; the stable conditioning circuit is used to stabilize the amplitude of the output signal of the command amplification notch conditioning circuit, and send it to the test control after the buffer is stabilized. in the snap-in.

The stable conditioning circuit includes a MOS transistor Q1, the drain of the MOS transistor Q1 is connected to one end of the resistor R6 and the output end of the operational amplifier AR2, the gate of the MOS transistor Q1 is connected to the other end of the resistor R6, and is connected to the resistor R7 and the capacitor C5 in parallel. Grounding, the source of the MOS transistor Q1 is connected to one end of the resistor R9 and the command signal input end of the test control management unit through the parallel resistor R8 and the capacitor C6, and the other end of the resistor R9 is grounded.

The notch component includes an inductor L1, a resistor R3, and capacitors C2 and C3. One end of the inductor L1, the resistor R3 and the capacitor C2 is connected to the non-inverting input terminal of the operational amplifier AR1, and the other end of the inductor L1 and the capacitor C2 is connected to the non-inverting input terminal of the operational amplifier AR3. Input end, the other end of resistor R3 is grounded through capacitor C3.

In the specific use of the present invention, the tester performs gear control operations on the simulated circuit breaker through the liquid crystal display screen, and the operation instructions are edited by the controller and sent to the instruction adjustment unit in the form of simulated instruction signals for processing. The controller selects the FPGA control processing module, and the IO control program is programmed in the FPGA control processing module to realize the management CPU, which is a mature prior art.

In order to ensure the stability and accuracy of the analog command signal control, firstly, the command amplification notch conditioning circuit is used to amplify and notch the analog command signal. Among them, the resistor R1 and the capacitor C1 form an RC high-pass filter to block the signal and eliminate low-frequency noise; then the operational amplifier AR1 and AR2 are connected in series to amplify the analog command signal step by step, that is, the operational amplifier AR1 uses the voltage to follow The principle of the amplifier isolates and amplifies the command signal to avoid the electrical interference of the previous stage, and then sends it to the operational amplifier AR2 for secondary amplification to rapidly improve the command signal strength; in the secondary amplification process, the resistor R5 and the capacitor C4 form a resistance-capacitance feedback Compensate for the output signal of op amp AR2 to ensure continuous and stable signal output. At the same time, a notch component is also set between the op amps AR1 and AR2. The RLC notch filter principle is used to eliminate the power frequency noise in the analog command, and the external power supply noise interference is well suppressed, thereby improving the command control accuracy.

Further, the op amp AR3 is used to follow up and amplify the signal after the notch, and then shunted through the resistor and sent to the non-inverting input terminal of the op amp AR2, and the operation of the non-inverting input terminal of the op amp AR2 is offset by the subtraction principle of the op amp. Amplify the offset voltage, so as to suppress the zero drift of the operational amplifier, and effectively avoid the offset caused by the amplification of the command signal.

In the stable conditioning circuit, the MOS transistor Q1 is used as a regulating tube to process the output signal of the command amplification notch conditioning circuit. Among them, the resistor R7 and the capacitor C5 form an RC stabilization element, which plays a very good role in stabilizing the gate voltage of the MOS transistor Q1. , so as to ensure that the output signal amplitude of the source of the MOS transistor Q1 is stable. Then, the resistors R8, R9 and the capacitor C6 form an RC buffer circuit to improve the waveform of the command signal, which effectively improves the stability of the command signal delivery.

After receiving the simulated command signal, the test control management unit drives the corresponding drive module to make corresponding action commands according to the command information, thereby completing the logic test of the object to be tested.

To sum up, the present invention adjusts the analog command signal issued by the controller by setting the command adjustment unit, effectively eliminates the interference of the external power supply and environmental factors on the command signal, and ensures the stability and reliability of the process of issuing the analog control command signal. accuracy, thereby effectively improving the validity of the simulated circuit breaker test results.

The above is a further detailed description of the present invention in combination with the specific embodiments, and it cannot be considered that the specific implementation of the present invention is limited to this; , the expansion and the replacement of the operation method and data should all fall within the protection scope of the present invention.

Claims (4)

1. Simulation circuit breaker testing arrangement, including controller, instruction regulating unit and test control management unit, its characterized in that: the instruction adjusting unit is used for adjusting a control instruction signal issued by the controller and comprises an instruction amplification trapped wave conditioning circuit and a stable conditioning circuit;

the instruction amplification trap conditioning circuit comprises operational amplifiers AR1, AR2 and AR3, wherein the non-inverting input end of an operational amplifier AR1 is connected with one end of a resistor R1 and the analog instruction signal output end of the controller through a capacitor C1, and is connected with the non-inverting input end of the operational amplifier AR3 through a trap component, the other end of the resistor R1 is grounded, the inverting input end and the input end of the operational amplifier AR1 are connected with the inverting input end of the operational amplifier AR2 through a resistor R2, the inverting input end and the output end of the operational amplifier AR3 are connected with the non-inverting input end of the operational amplifier AR2 and one end of a rheostat RP1 through a resistor R4, the other end of the rheostat RP1 is grounded with the sliding end, and the output end of the operational amplifier AR2 is connected with the input end of the stable conditioning circuit, and is connected with the inverting input end of the operational amplifier AR2 through a resistor R5 and a capacitor C4 which are connected in parallel; and the stable conditioning circuit is used for carrying out amplitude stabilization regulation on the output signal of the instruction amplification trapped wave conditioning circuit, and sending the output signal into the test control management unit after the output signal is buffered and stabilized.

2. The analog circuit breaker testing apparatus of claim 1, wherein: the stable conditioning circuit comprises a MOS tube Q1, wherein the drain electrode of the MOS tube Q1 is connected with one end of a resistor R6 and the output end of an operational amplifier AR2, the grid electrode of the MOS tube Q1 is connected with the other end of a resistor R6 and is grounded through a resistor R7 and a capacitor C5 which are connected in parallel, the source electrode of the MOS tube Q1 is connected with one end of a resistor R9 and the instruction signal input end of the test control management unit through a resistor R8 and a capacitor C6 which are connected in parallel, and the other end of the resistor R9 is grounded.

3. The analog circuit breaker testing apparatus of claims 1 and 2, wherein: the trap component comprises an inductor L1, a resistor R3, capacitors C2 and C3, one ends of the inductor L1, the resistor R3 and the capacitor C2 are connected with a non-inverting input end of an operational amplifier AR1, the other ends of the inductor L1 and the capacitor C2 are connected with a non-inverting input end of an operational amplifier AR3, and the other end of the resistor R3 is grounded through a capacitor C3.

4. The analog circuit breaker testing apparatus of claim 1, wherein: the controller adopts an FPGA control processing module.

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