CN114446910A - 芯片结构、封装结构及芯片结构的制作方法、绑定方法 - Google Patents

芯片结构、封装结构及芯片结构的制作方法、绑定方法 Download PDF

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CN114446910A
CN114446910A CN202011197007.9A CN202011197007A CN114446910A CN 114446910 A CN114446910 A CN 114446910A CN 202011197007 A CN202011197007 A CN 202011197007A CN 114446910 A CN114446910 A CN 114446910A
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pin
layer
end device
chip
radio frequency
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CN114446910B (zh
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刘宗民
段立业
黄继景
侯孟军
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN202011197007.9A priority Critical patent/CN114446910B/zh
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Priority to US17/489,759 priority patent/US11769745B2/en
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Abstract

本申请涉及显示领域，提供一种芯片结构、封装结构及芯片结构的制作方法、绑定方法，该芯片结构包括至少一个芯片主体，芯片主体包括至少一个射频前端器件，芯片结构还包括与芯片主体层叠设置的重布线层和设置在重布线层上的至少一个引脚；每个射频前端器件都对应有引脚，引脚通过贯穿重布线层的电连接件与相应的射频前端器件电连接，并且，射频前端器件的延伸方向与和该射频前端器件对应的引脚的延伸方向一致，引脚背离重布线层的表面为第一平面。应用本申请，通过设置具有第一平面的引脚，以能够直接将芯片与柔性线路板电连接。

Description

芯片结构、封装结构及芯片结构的制作方法、绑定方法
技术领域
本发明涉及集成电路技术领域，具体地，涉及一种芯片结构、封装结构及芯片结构的制作方法、绑定方法。
背景技术
传统的RFIC(射频集成电路)主要采用BGA封装(Ball Grid Array Package，球栅阵列封装)或者QFN封装(Quad Flat No-leadPackage，方形扁平无引脚封装)，以获得较低的阻抗和自感。
但采用这两种封装形式进行封装时，都只能通过SMT(Surface MountingTechnology，表面组装技术)工艺将IC(集成电路)通过焊接的方式电连接到刚性PCB(Printed Circuit Board，中文名称为印制电路板)或设有补强的FPC(Flexible PrintedCircuit，柔性线路板)上，无法直接电连接到柔性线路板上。
发明内容
本申请旨在至少解决现有技术中存在的技术问题之一，提出了一种芯片结构、封装结构及芯片结构的制作方法、绑定方法，该芯片结构通过设置具有第一平面的引脚，以能够直接将芯片与柔性线路板电连接。
为实现本申请的目的，第一方面提供一种芯片结构，所述芯片结构包括至少一个芯片主体，所述芯片主体包括至少一个射频前端器件，所述芯片结构还包括与所述芯片主体层叠设置的重布线层和设置在所述重布线层上的至少一个引脚；
每个所述射频前端器件都对应有所述引脚，所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，并且，所述射频前端器件的延伸方向与和该射频前端器件对应的引脚的延伸方向一致，所述引脚背离所述重布线层的表面为第一平面。
可选地，所述第一平面的形状为矩形，所述射频前端器件朝向所述引脚的表面也为矩形。
可选地，所述矩形的尺寸在2mm×50mm以内。
可选地，所述重布线层上形成有通孔，所述电连接件设置在所述通孔中，所述电连接件包括沿背离所述射频前端器件的方向依次设置的第一导电连接层、第二导电连接层和导电连接本体，所述导电连接本体用于与所述引脚连接，
所述第一导电连接层覆盖所述通孔的侧壁和底壁，并且与所述射频前端器件电连接，所述第二导电连接层覆盖所述第一导电连接层，并形成二级孔，所述连接件本体形成在所述二级孔中，且所述导电连接本体与所述引脚电连接。
可选地，所述重布线层为钝化层。
可选地，所述芯片主体包括射频入口区域、射频出口区域及电源区域，所述射频入口区域、所述射频出口区域和所述电源区域分别设置有至少一个所述射频前端器件。
可选地，所述芯片主体与所述重布线层接触的表面为矩形，所述射频入口区域包括多个对称分布在所述矩形的两个相对的边上的子入口区域，每个子入口区域设置有一个所述射频前端器件，所述射频出口区域包括多个对称分布在所述矩形的两个相对的边上的子出口区域，每个子出口区域设置有一个所述射频前端器件，所述电源区域包括多个对称分布在所述矩形的两个相对的边上的子电源区域，每个子电源区域设置有一个所述射频前端器件。
可选地，所述引脚、所述导电连接本体及所述第二导电连接层的材质相同。
可选地，所述引脚、所述导电连接本体及所述第二导电连接层的材质均为金；所述第一导电连接层包括钛金属层和/或钨金属层。
为实现本申请的目的，第二方面提供一种封装结构，包括柔性线路板和第一方面提供的芯片结构，所述柔性线路板上包括电连接盘，所述电连接盘与所述引脚电连接。
为实现本申请的目的，第三方面提供一种芯片结构的制作方法，所述方法包括：
提供至少一个芯片主体，所述芯片主体包括至少一个射频前端器件；
在所述芯片主体上形成重布线层；
在所述重布线层上形成至少一个引脚，且所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，并使每个所述射频前端器件都对应有所述引脚，所述引脚的延伸方向与和该引脚对应的所述射频前端器件的延伸方向一致，所述引脚背离所述重布线层的表面为第一平面。
可选地，所述在所述重布线层上形成至少一个引脚，且所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，包括：
在所述重布线层覆盖所述射频前端器件的部位开设有贯穿所述重布线层的通孔；
形成所述电连接件的第一导电连接层，所述第一导电连接层覆盖所述通孔的侧壁和底壁，并且与所述射频前端器件电连接；
在所述第一导电连接层上形成所述电连接件的第二导电连接层，并形成二级孔；
在所述第二导电连接层上涂覆光刻胶，对所述光刻胶进行曝光显影，以利用所述光刻胶形成所述引脚的成型腔，并显露出所述二级孔；
采用电镀工艺在所述二级孔内形成所述电连接件的导电连接本体，及在所述成型腔内形成所述引脚；
去除所述第一导电连接层和所述第二导电连接层未被所述引脚覆盖的部分。
为实现本申请的目的，第四方面提供一种绑定方法，应用于第二方面提供的封装结构，所述方法包括：
采用绑定压头将所述芯片结构的所述引脚与所述柔性线路板的电连接盘进行绑定，以使所述电连接盘与所述引脚电连接，其中，所述绑定压头的形状与所述引脚的第一平面形状匹配。
附图说明
图1为本申请实施例提供的芯片结构的剖视结构示意图；
图2为本申请实施例提供的芯片结构的立体结构示意图(不包括芯片主体)；
图3为本申请实施例提供的芯片结构的局部剖视结构示意图；
图4为本申请实施例提供的一种射频前端器件芯片的单通道简单示意图；
图5为本申请实施例提供的芯片结构上的引脚布局示意图；
图6-图12为本申请实施例提供的芯片结构上的引脚的制作流程示意图。
具体实施方式
下面详细描述本申请，本申请的实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的部件或具有相同或类似功能的部件。此外，如果已知技术的详细描述对于示出的本申请的特征是不必要的，则将其省略。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。
本技术领域技术人员可以理解，除非另外定义，这里使用的所有术语(包括技术术语和科学术语)，具有与本申请所属领域中的普通技术人员的一般理解相同的意义。还应该理解的是，诸如通用字典中定义的那些术语，应该被理解为具有与现有技术的上下文中的意义一致的意义，并且除非像这里一样被特定定义，否则不会用理想化或过于正式的含义来解释。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”和“该”也可包括复数形式。应该理解，当我们称元件被“连接”或“耦接”到另一元件时，它可以直接连接或耦接到其他元件，或者也可以存在中间元件。此外，这里使用的“连接”或“耦接”可以包括无线连接或无线耦接。这里使用的措辞“和/或”包括一个或更多个相关联的列出项的全部或任一单元和全部组合。
下面结合附图以具体的实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。
本实施例对传统的RFIC(射频集成电路)封装技术进行研究分析，发现：传统的RFIC封装技术，如BGA封装(Ball Grid Array－球状引脚栅格阵列封装技术)或者QFN封装(Quad Flat No-leads Package，方形扁平无引脚封装)，但是这两种封装形式都只能通过SMT工艺将芯片通过焊接的方式电连接到刚性PCB或设有补强的FPC上。因锡球的融化温度及对位、封装形状尺寸等问题，使得传统封装的RFIC无法通过绑定(bonding，又可以被称作连接工艺)的方式电连接到柔性线路板上。如，以塑封BGA为例，其封装流程大致为：圆片减薄→圆片切削→芯片粘结→等离子清洗→引线键合→等离子清洗→模塑封装→装配焊料球→回流焊→表面打标→分离→最终检查。因为芯片功能复杂、引脚众多，一般封装设计为方形居多，这就导致PCB设计复杂度提升、bonding压头无法同时均匀加热的问题，同时锡球的焊接温度一般高达300℃左右，在高温及锡球融化的作用下，会让柔性线路板的基材产生变形。因此，目前基于BGA封装的RFIC均采用在刚性PCB或补强柔性FPC上通过SMT焊接的方式实现电连接。
有鉴于此，本发明提供一种芯片结构，请参照附图1-3，为本实施例提供的芯片结构的剖视结构示意图和立体结构示意图，如图1所示，该芯片结构包括至少一个芯片主体10，芯片主体10包括至少一个射频前端器件11，芯片结构还包括与芯片主体10层叠设置的重布线层20和设置在重布线层20上的至少一个引脚30；每个射频前端器件11都对应有引脚30，引脚30通过贯穿重布线层20的电连接件与相应的射频前端器件11电连接，并且，射频前端器件11的延伸方向与和该射频前端器件11对应的引脚30的延伸方向一致，引脚30背离重布线层20的表面为第一平面。
本实施例提供的芯片结构，在其重布线层20上设置至少一个引脚30，引脚30可通过贯穿重布线层20的电连接件与重布线层20下面相应的射频前端器件11电连接，且射频前端器件11的延伸方向与和该射频前端器件11对应的引脚30的延伸方向一致，引脚30背离重布线层20的表面为第一平面，通过设置该第一平面可以将该芯片结构通过绑定(bonding)压装的方式与一柔性线路板连接，从而能够将射频前端芯片的应用场景扩展到柔性基材上，以做到COP(chip on PI/Plastic，原理是直接将屏幕的一部分弯曲，从而进一步缩小边框，可以达到近乎无边框的效果)，达到一体化的窄边框设计，从而能够将具有射频前端器件11的该芯片结构应用在手机等移动设备有应用场景。
如图1所示，多个射频前端器件11可以同层设置在一个塑封层中进行固定，可以设置与之对应个数的引脚30，以实现每个射频前端器件11与柔性线路板之间的电连接，继而针对不同射频前端器件11实现不同的功能。两个射频前端器件11之间也可以通过金属线连接，以实现两个射频前端器件11之间的关联关系。
其中，如图3所示，上述电连接件可以通过贯穿重布线层20的通孔21与相应的射频前端器件11电连接。具体地，在制作时，可采用电镀的方式一体成型该贯穿重布线层20的电连接件。重布线层20可以包括若干用于电连接的连接线，和用于固定该若干连接线的钝化层，上述通孔21可开设在钝化层中。
需要说明的是，本实施例并不限定射频前端器件11及重布线层20的具体结构，其可以是本领域内任意结构的射频前端器件11和重布线层20，只要能在重布线层20上形成与射频前端器件11连接的引脚30即可。本实施例也不限定射频前端器件11的具体数量，其可以仅包括一个，也可以如图1所示包括两个，也可以包括更多个。为了增强电连接件与引脚30之间的连接性，以形成稳定的引脚30，可以将电连接件整体或部分与引脚30一体成型。例如，上述电连接件可以包括沿背离射频前端器件11的方向依次设置的第一导电连接层31、第二导电连接层32和导电连接本体33。其中，导电连接本体33作为主要的连接件，用于与引脚30连接，其可以与引脚30采用相同的材质，进行一体成型。第一导电连接层31覆盖通孔21的侧壁和底壁，与射频前端器件11和重布线层20接触，并与射频前端器件11电连接，防止引脚30发生松动引起接触不良等现象，以增强电连接件与射频前端器件11及重布线层20之间的电连接稳定性和连接强度。第二导电连接层32覆盖第一导电连接层31，并形成上述通孔21的二级孔，用于分别与第一导电连接层31和导电连接本体33连接，防止导电连接本体33与第一导电连接层31之间，可进一步提高电连接件的连接强度，继而提高引脚30的导电稳定性。
其中，为提高引脚30的电性能，其通常采用金属材料制作，如上，导电连接本体33可以与引脚30采用相同的材料制作，为了进一步提高连接强度，第二导电连接层32也可以与导电连接本体33及引脚30采用相同的材质制作。具体地，第一导电连接层31和第二导电连接层32可以采用磁控溅射的工艺进行制作，以在制作时使金属粒子轰击下层膜层，实现两层膜层之间的稳定有效连接。而导电连接本体33和引脚30可以通过电镀的工艺制作，以形成具有一定厚度的导电连接本体33和引脚30。具体地，可以在重布线层20覆盖电极层的部位开设有贯穿其的通孔，在通孔内设置导电连接本体33，并在导电连接本体33与电极层之间、导电连接本体33与通孔的内壁之间，及引脚30与重布线层20之间均依次设置第二导电连接层32和第一导电连接层31，如此，在电镀导电连接本体33与引脚30之前，在导电连接本体33和引脚30与重布线层20及射频前端器件11之间先形成第一导电连接层31和第二导电连接层32，以增强导电连接本体33及引脚30与重布线层20及射频前端器件11的连接强度，从而增强引脚30的导电稳定性，保证其良好的电性能。
优选地，引脚30、导电连接本体33及第二导电连接层32的材质可以均为金，金属金具有良好的导电性，和足够的机械强度，可以保证引脚30及电连接件的导电性能，且在对芯片结构进行绑定(绑定引脚30)压装时，保证了引脚30的机械强度，可以实现压装要求。
第一导电连接层31可以包括钛金属层和/或钨金属层，由于钛金属和钨金属具有良好的导电性，且与非金属和金属的结合性都较强，可以在第二导电连接层32与射频前端器件11(其钝化层和电极层)及重布线层20之间设置一层或多层钛金属层或钨金属层，也可以同时设置一层或多层钛金属层和钨金属层，本实施例对此不作具体限定。
需要说明的是，上述电连接件的结构及材质只是本实施例的一种实施方式，本实例对此不作具体限定，只要其能够将引脚30与射频前端器件11进行可靠的电连接即可。
为了便于采用bonding的形式将该芯片结构与柔性线路板进行连接，上述引脚30顶面的第一平面的形状可以为矩形，射频前端器件11朝向引脚30的表面也为矩形，以便于与长方形细条状的bonding压头进行匹配，便于bonding压头对引脚30进行加压。
进一步地，可以根据bonding压头的尺寸设计上述第一平面的尺寸，通常可以设计第一平面的尺寸不大于bonding压头的尺寸，以使bonding压头能够对第一平面进行整体加压，以保证压装绑定效果。例如，bonding压头的宽度一般不超过2mm，则上述矩形的第一平面的宽度尺寸可以小于等于2mm，而矩形的第一平面的长度尺寸可根据芯片主体10的尺寸进行合理设计，比如长度尺寸可以小于等于50mm。
另外，如图4所示，为本实施例提供的一种射频前端芯片的单通道简单示意图，该射频前端芯片(该芯片结构)可以包括很多不同功能的射频器件和无源器件，如开关111、移相112、放大113、衰减114、滤波及电阻、电容、电感等。一般射频前端芯片至少包含4个通道，为了保证诸如隔离度、对称性及阻抗匹配等，通常射频前端芯片会设计方形薄片形状，可在其表面的四边均设置引脚30。
如图5所示，芯片主体10可以包括射频入口区域A、射频出口区域B及电源区域C，可在该射频入口区域A、射频出口区域B及电源区域C分别设置至少一个引脚30。例如，芯片主体10与重布线层20接触的表面可以为矩形，射频入口区域A可以包括多个对称分布在矩形的两个相对的边上的子入口区域A1和A2，并对应每个子入口区域设置有一个射频前端器件11；射频出口区域B可以包括多个对称分布在矩形的两个相对的边上的子出口区域，并对应每个子出口区域设置有一个射频前端器件11；电源区域C可以包括多个对称分布在矩形的两个相对的边上的子电源区域，并对应每个子电源区域设置有一个射频前端器件11。多个引脚30可以沿矩形的长度方向或宽度方向间隔布置在子入口区域、子出口区域及子电源区域。如此，将相同功能的射频前端器件11对称设置，将不同功能的射频前端器件11分区域间隔设置，可以保证不同功能的射频前端器件11之间具有足够的隔离度，保证多个射频前端器件11分布的对称性及阻抗匹配性等。
基于上述芯片结构相同的构思，本实施例还提供一种封装结构，该封装结构包括柔性线路板和上述任一实施方式的芯片结构，柔性线路板上包括电连接盘，电连接盘与引脚30电连接。
本实施例提供的封装结构，包括通过绑定的方式封装在一起的芯片结构和柔性线路板，芯片结构在其重布线层20上设置至少一个引脚30，引脚30可通过贯穿重布线层20的电连接件与重布线层20下面相应的射频前端器件11电连接，且射频前端器件11的延伸方向与和该射频前端器件11对应的引脚30的延伸方向一致，引脚30背离重布线层20的表面为第一平面，通过设置该第一平面可以将该芯片结构通过绑定(bonding)压装的方式与一柔性线路板连接，从而能够将射频前端芯片的应用场景扩展到柔性基材上，以做到COP(chip onPI/Plastic，原理是直接将屏幕的一部分弯曲，从而进一步缩小边框，可以达到近乎无边框的效果)，达到一体化的窄边框设计，从而能够将具有射频前端器件11的该芯片结构应用在手机等移动设备有应用场景。
基于上述芯片结构相同的构思，本实施例还提供一种芯片结构的制作方法，该制作方法可以包括以下步骤：
提供至少一个芯片主体10，芯片主体10包括至少一个射频前端器件11；
在芯片主体10上形成重布线层20；
在重布线层20上形成至少一个引脚30，且引脚30通过贯穿重布线层20的电连接件与相应的射频前端器件11电连接，并使每个射频前端器件11都对应有引脚30，引脚30的延伸方向与和该引脚30对应的射频前端器件11的延伸方向一致，引脚30背离重布线层20的表面为第一平面。
其中，如图3及图6-10所示，在重布线层20上形成至少一个引脚30，且引脚30通过贯穿重布线层20的电连接件与相应的射频前端器件11电连接的步骤，可以包括以下处理：
1)在重布线层20覆盖射频前端器件11的部位开设有贯穿重布线层20的通孔21，以使引脚30穿过该通孔21与射频前端器件11连接。
2)形成电连接件的第一导电连接层31，第一导电连接层31覆盖通孔21的侧壁和底壁，并且与射频前端器件11电连接。具体可采用磁控溅射工艺形成第一导电连接层31，第一导电连接层31还覆盖重布线层20的通孔21周围与引脚30接触的表面。第一导电连接层31可以是钛金属层和/或钨金属层。
3)在第一导电连接层31上形成电连接件的第二导电连接层32，第二导电连接层32覆盖第一导电连接层31，并形成通孔21的二级孔。具体可采用磁控溅射工艺形成第二导电连接层32，第二导电连接层32的材质可以与下述导电连接本体33及引脚30的材质一样，例如，均为金属金。
4)在二级孔内形成电连接件的导电连接本体33，使导电连接本体33与第二导电连接层32连接。具体可采用电镀的工艺形成导电连接本体33，以形成厚度尺寸较大的导电连接本体33。
5)继续在导电连接本体33上形成引脚30。具体地，引脚30可以覆盖通孔21边缘的重布线层20区域，以增大引脚30与重布线层20的接触面积，提高引脚30的稳定可靠性。
上述形成引脚30的过程，即步骤2)-5)，具体可以可采用BUMP(凸块)工艺，如图7和图8所示，依次在通孔21内及通孔21周围的重布线层20上沉积钛金属层和/或钨金属层、及金金属层。然后如图9-10所示，在金金属层上涂覆光刻胶40，并采用掩膜版对光刻胶40进行曝光显影，以蚀除通孔21内及其周围的光刻胶40，形成引脚的成型腔，并显露出上述二级孔。然后如图11所示，在蚀除光刻胶的部位电镀金金属，形成上述导电连接本体33和引脚30。最后如图12和图3所示，依次蚀除引脚30外的多余的第二导电连接层32和第一导电连接层31，以保证芯片结构表面的平整性。
本实施例提供的芯片结构的制作方法，可以形成包括引脚30的芯片结构，且该引脚30设置在芯片结构的重布线层20上，并可通过贯穿重布线层20的电连接件与重布线层20下面相应的射频前端器件11电连接，且射频前端器件11的延伸方向与和该射频前端器件11对应的引脚30的延伸方向一致，引脚30背离重布线层20的表面为第一平面，通过设置该第一平面可以将该芯片结构通过绑定(bonding)压装的方式与一柔性线路板连接，从而能够将射频前端芯片的应用场景扩展到柔性基材上，以做到COP，达到一体化的窄边框设计，从而能够将具有射频前端器件11的该芯片结构应用在手机等移动设备有应用场景。
基于上述芯片结构相同的构思，本实施例还提供一种绑定方法，应用于上述的封装结构，该方法包括：
采用绑定压头将芯片结构的引脚30与柔性线路板的电连接盘进行绑定，以使电连接盘与引脚30电连接，其中，绑定压头的形状与引脚30的第一平面形状匹配。
本实施例提供的绑定方法，可以将芯片结构通过bonding的方式与一柔性线路板连接，从而能够将射频前端芯片的应用场景扩展到柔性基材上，以做到COP，达到一体化的窄边框设计，从而能够将具有射频前端器件11的该芯片结构应用在手机等移动设备有应用场景。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。
在本申请的描述中，需要理解的是，术语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
以上仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (13)

1.一种芯片结构，所述芯片结构包括至少一个芯片主体，所述芯片主体包括至少一个射频前端器件，其特征在于，所述芯片结构还包括与所述芯片主体层叠设置的重布线层和设置在所述重布线层上的至少一个引脚；
每个所述射频前端器件都对应有所述引脚，所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，并且，所述射频前端器件的延伸方向与和该射频前端器件对应的引脚的延伸方向一致，所述引脚背离所述重布线层的表面为第一平面。
2.根据权利要求1所述的芯片结构，其特征在于，所述第一平面的形状为矩形，所述射频前端器件朝向所述引脚的表面也为矩形。
3.根据权利要求2所述的芯片结构，其特征在于，所述矩形的尺寸在2mm×50mm以内。
4.根据权利要求1所述的芯片结构，其特征在于，所述重布线层上形成有通孔，所述电连接件设置在所述通孔中，所述电连接件包括沿背离所述射频前端器件的方向依次设置的第一导电连接层、第二导电连接层和导电连接本体，所述导电连接本体用于与所述引脚连接，
所述第一导电连接层覆盖所述通孔的侧壁和底壁，并且与所述射频前端器件电连接，所述第二导电连接层覆盖所述第一导电连接层，并形成二级孔，所述连接件本体形成在所述二级孔中，且所述导电连接本体与所述引脚电连接。
5.根据权利要求4所述的芯片结构，其特征在于，所述重布线层为钝化层。
6.根据权利要求1所述的芯片结构，其特征在于，所述芯片主体包括射频入口区域、射频出口区域及电源区域，所述射频入口区域、所述射频出口区域和所述电源区域分别设置有至少一个所述射频前端器件。
7.根据权利要求6所述的芯片结构，其特征在于，所述芯片主体与所述重布线层接触的表面为矩形，所述射频入口区域包括多个对称分布在所述矩形的两个相对的边上的子入口区域，每个子入口区域设置有一个所述射频前端器件，所述射频出口区域包括多个对称分布在所述矩形的两个相对的边上的子出口区域，每个子出口区域设置有一个所述射频前端器件，所述电源区域包括多个对称分布在所述矩形的两个相对的边上的子电源区域，每个子电源区域设置有一个所述射频前端器件。
8.根据权利要求4所述的芯片结构，其特征在于，所述引脚、所述导电连接本体及所述第二导电连接层的材质相同。
9.根据权利要求8所述的芯片结构，其特征在于，所述引脚、所述导电连接本体及所述第二导电连接层的材质均为金；所述第一导电连接层包括钛金属层和/或钨金属层。
10.一种封装结构，其特征在于，包括柔性线路板和权利要求1-9任意一项所述的芯片结构，所述柔性线路板上包括电连接盘，所述电连接盘与所述引脚电连接。
11.一种芯片结构的制作方法，其特征在于，所述方法包括：
提供至少一个芯片主体，所述芯片主体包括至少一个射频前端器件；
在所述芯片主体上形成重布线层；
在所述重布线层上形成至少一个引脚，且所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，并使每个所述射频前端器件都对应有所述引脚，所述引脚的延伸方向与和该引脚对应的所述射频前端器件的延伸方向一致，所述引脚背离所述重布线层的表面为第一平面。
12.根据权利要求11所述的制作方法，其特征在于，所述在所述重布线层上形成至少一个引脚，且所述引脚通过贯穿所述重布线层的电连接件与相应的射频前端器件电连接，包括：
在所述重布线层覆盖所述射频前端器件的部位开设有贯穿所述重布线层的通孔；
形成所述电连接件的第一导电连接层，所述第一导电连接层覆盖所述通孔的侧壁和底壁，并且与所述射频前端器件电连接；
在所述第一导电连接层上形成所述电连接件的第二导电连接层，并形成二级孔；
在所述第二导电连接层上涂覆光刻胶，对所述光刻胶进行曝光显影，以利用所述光刻胶形成所述引脚的成型腔，并显露出所述二级孔；
采用电镀工艺在所述二级孔内形成所述电连接件的导电连接本体，及在所述成型腔内形成所述引脚；
去除所述第一导电连接层和所述第二导电连接层未被所述引脚覆盖的部分。
13.一种绑定方法，其特征在于，应用于权利要求10所述的封装结构，所述方法包括：
采用绑定压头将所述芯片结构的所述引脚与所述柔性线路板的电连接盘进行绑定，以使所述电连接盘与所述引脚电连接，其中，所述绑定压头的形状与所述引脚的第一平面形状匹配。
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CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装
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KR20200048971A (ko) * 2018-10-31 2020-05-08 삼성전자주식회사 반도체 패키지 및 이를 포함하는 안테나 모듈

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CN102263074A (zh) * 2010-05-24 2011-11-30 联发科技股份有限公司 系统级封装
CN105161468A (zh) * 2015-10-10 2015-12-16 中国电子科技集团公司第三十八研究所 一种射频芯片及其无源器件的封装结构和封装方法
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