CN114446780A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114446780A
CN114446780A CN202011197435.1A CN202011197435A CN114446780A CN 114446780 A CN114446780 A CN 114446780A CN 202011197435 A CN202011197435 A CN 202011197435A CN 114446780 A CN114446780 A CN 114446780A
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layer
material layer
sacrificial
forming
protective
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刘睿
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein a material layer to be etched is formed on the substrate; forming a plurality of mutually discrete sacrificial layers and first protective layers on the material layer to be etched, wherein the first protective layers are positioned on the sacrificial layers, and a first opening is formed between every two adjacent sacrificial layers; forming a mask material layer on the bottom and the side wall surface of the first opening, wherein the mask material layer covers the top and the side wall surface of the first protection layer and the side wall surface of the sacrificial layer; removing the mask material layer on the bottom surface of the first opening and the top surface of the first protective layer; removing the first protective layer and the sacrificial layer, and forming a second opening in the residual mask material layer; and removing the material layer to be etched exposed out of the first opening and the second opening to form a target graph layer. The invention improves the pattern precision of the second opening, thereby improving the performance of the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.
In the development of integrated circuits, the functional density (i.e., the number of interconnect structures per chip) generally increases, while the geometric size (i.e., the minimum component size that can be produced by the process steps) decreases, which increases the difficulty and complexity of integrated circuit fabrication.
At present, the performance of the formed semiconductor structure is poor under the condition that the technical nodes are continuously reduced.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a material layer to be etched is formed on the substrate; forming a plurality of mutually discrete sacrificial layers and first protective layers on the material layer to be etched, wherein the first protective layers are positioned on the sacrificial layers, and a first opening is formed between every two adjacent sacrificial layers; forming a mask material layer on the bottom and the side wall surface of the first opening, wherein the mask material layer covers the top and the side wall surface of the first protection layer and the side wall surface of the sacrificial layer; removing the mask material layer on the bottom surface of the first opening and the top surface of the first protective layer; removing the first protective layer and the sacrificial layer, and forming a second opening in the residual mask material layer; and removing the material layer to be etched exposed out of the first opening and the second opening to form a target graph layer.
Optionally, the step of forming a plurality of mutually discrete sacrificial layers and first protective layers on the material layer to be etched includes: forming a sacrificial material layer on the material layer to be etched; forming a first protective material layer on the sacrificial material layer; forming a patterning layer on the first protective material layer, wherein the patterning layer is internally provided with a patterning opening, and the patterning opening corresponds to the position and the size of the first opening; implanting doping ions into a part of the first protective material layer and the sacrificial material layer by taking the patterning layer as a mask; removing the first protective material layer and the sacrificial material layer implanted with the doped ions to form a sacrificial layer and a first protective layer which are mutually separated; and removing the patterning layer.
Optionally, a process of forming the first protective material layer includes a chemical vapor deposition process or an atomic layer deposition process.
Optionally, before forming the first protective material layer on the sacrificial material layer, the method further includes: and forming a second protective material layer on the surface of the sacrificial material layer.
Optionally, performing oxidation treatment on the sacrificial material layer to form the second protective material layer; the technological parameters of the oxidation treatment comprise: providing oxygen, wherein the gas flow of the oxygen is 100-200 sccm, and the temperature is 30-50 ℃.
Optionally, the step of removing the first protection layer and the sacrificial layer includes: and removing the sacrificial layer by adopting a second etching process after removing the first protective layer by adopting a first etching process.
Optionally, the first etching process is a wet etching process; the parameters of the wet etching process comprise: the etching solution comprises a diluted hydrofluoric acid solution, and the volume ratio of hydrofluoric acid to water of the diluted hydrofluoric acid solution is less than or equal to 1: 500.
Optionally, the second etching process is a wet etching process; the parameters of the wet etching process comprise: the etching solution comprises ammonia water
Optionally, the material of the first protection layer includes silicon oxide or silicon nitride.
Optionally, the material of the sacrificial layer includes amorphous silicon, amorphous carbon or polysilicon.
Optionally, the material layer to be etched includes a single material layer or a plurality of stacked material layers.
Optionally, the material of the mask material layer includes titanium oxide, titanium nitride, silicon oxide, or silicon oxynitride.
Optionally, the process of forming the mask material layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Optionally, the dopant ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions.
Optionally, the process of removing the first protective material layer and the sacrificial material layer implanted with the doped ions is a dry etching process.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the method comprises the steps of forming a plurality of mutually-separated sacrificial layers and a first protective layer on a material layer to be etched, wherein the first protective layer is located on the sacrificial layers and used for covering the top surfaces of the sacrificial layers, the top surfaces of the sacrificial layers are prevented from being exposed in the air and causing atomic agglomeration, and gullies generated on the surfaces of the sacrificial layers are reduced.
Drawings
FIGS. 1-4 are schematic structural diagrams illustrating a method for forming a semiconductor structure according to an embodiment;
fig. 5 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As can be seen from the background, the performance of current semiconductor structures is poor. The reasons for the poor performance of the semiconductor structure are now analyzed in conjunction with the detailed figures.
Referring to fig. 1, a layer to be etched 100 is provided; forming a sacrificial layer 101 on the layer to be etched 100; forming a patterning layer 102 on the sacrificial layer 101, wherein the patterning layer 102 exposes a part of the surface of the sacrificial layer 101; and carrying out ion implantation on the exposed sacrificial layer.
Referring to fig. 2, the patterned layer 102 is removed; and removing the sacrificial layer 101 implanted with ions, and forming a first opening 103 in the remaining sacrificial layer 101, wherein the first opening 103 exposes the surface of the layer to be etched 100.
Referring to fig. 3, a sidewall material layer 104 is formed on the bottom and the sidewall surface of the first opening 103, and the sidewall material layer 104 covers the top and the sidewall surface of the sacrificial layer 101.
Referring to fig. 4, the sidewall material layer 104 on the bottom surface of the first opening 103 and the top surface of the sacrificial layer 101 is removed; and removing the rest of the sacrificial layer 101, and forming a second opening 105 in the rest of the side wall material layer 104.
The inventor has found that, when the semiconductor structure is formed by using the above-mentioned forming method, after the patterned layer 102 is removed, the sacrificial layer 101 without implanted ions is exposed to the air, the sacrificial layer 101 is usually made of amorphous silicon, and the amorphous silicon exposed to the air is prone to silicon agglomeration, which results in a rough surface of the sacrificial layer 101 and a gully, when the sidewall material layer is deposited on the surface of the sacrificial layer 101, the material of the sidewall material layer is prone to be deposited into the gully (refer to the circle portion in fig. 3), which results in a thickened local sidewall material layer, when the sidewall material layer on the top surface of the sacrificial layer 101 is removed, the sidewall material layer 104 cannot be completely removed due to the thicker local sidewall material layer, which results in a portion of the sacrificial layer 102 remaining in the formed second opening 105 when the sacrificial layer 101 without implanted ions is removed. Subsequently, when the layer to be etched 100 is etched by using the remaining sidewall material layer 104 as a mask, the stability of pattern transfer is damaged due to the remaining sacrificial layer 101 in the second opening 105, so that a target pattern layer formed in the layer to be etched 100 has poor morphology and incomplete patterns, and the trench cannot be completely opened, thereby affecting the performance of the finally formed semiconductor structure.
In order to solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, forming a plurality of mutually separated sacrificial layers and first protective layers on the material layer to be etched, wherein the first protective layers are positioned on the sacrificial layers, the first protective layer prevents the surface of the sacrificial layer from directly contacting with air, reduces the phenomenon of atom aggregation on the surface of the sacrificial layer, and forming a mask material layer on the top surface of the first passivation layer to prevent the mask material layer from entering the trenches on the surface of the sacrificial layer, thereby solving the problem that the sacrificial layer remains in the second opening when the sacrificial layer is removed to form the second opening, and when the layer to be etched is etched along the first opening and the second opening, the stability of pattern transfer is high, the morphology of the formed target pattern layer is improved, and the performance of the finally formed semiconductor structure is facilitated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a substrate 200 is provided, and a material layer 210 to be etched is formed on the substrate 200.
The substrate 200 is used to provide a process platform for subsequent processes. In this embodiment, taking the formed semiconductor structure as a planar transistor as an example, the substrate 200 includes a substrate.
In this embodiment, the substrate is a silicon substrate; in other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In other embodiments, when the formed semiconductor structure is a fin field effect transistor, the substrate 200 may include a substrate and a fin protruding from the substrate.
The substrate 200 may also include other structures, such as gate structures, doped regions, shallow trench isolation structures, and the like.
The material layer 210 to be etched may be a single material layer or a plurality of stacked material layers, and may specifically include a dielectric material, a metal material, a hard mask material, or the like.
In this embodiment, the material layer 210 to be etched is a multi-layer stacked material layer, and includes: a first material layer (not shown) on the surface of the substrate 200, and a second material layer (not shown) on the surface of the first material layer.
The material of the first material layer comprises: and the k dielectric material (k is less than or equal to 3.9).
The second material layer is a hard mask layer and comprises a single-layer or multi-layer stack of a SiC layer, a SiN layer, a BD layer, a TEOS layer and a TiN layer.
The second material layer has the functions of serving as an etching stop layer on one hand and serving as a hard mask layer material on the other hand, and in the subsequent etching process, the second material layer is low in etching loss and high in stability of pattern transfer in the pattern transfer process.
After a material layer 210 to be etched is formed on the substrate 200, a plurality of mutually discrete sacrificial layers and first protective layers are formed on the material layer 210 to be etched, the first protective layers are located on the sacrificial layers, and a first opening is formed between every two adjacent sacrificial layers.
In this embodiment, the step of specifically forming a plurality of mutually discrete sacrificial layers and first protective layers includes:
referring to fig. 6, a sacrificial material layer 220 is formed on the material layer to be etched 210.
In this embodiment, the sacrificial material layer 220 is used for forming a discrete sacrificial layer.
The subsequent process includes patterning the sacrificial material layer 220, so that the sacrificial material layer 220 and the material layer 210 to be etched have a high etching selectivity, thereby implementing selective etching in the subsequent process. In this embodiment, the sacrificial material layer 220 is different from the material of the material layer to be etched 210.
The material of the sacrificial material layer 220 includes amorphous silicon, amorphous carbon or polysilicon. In this embodiment, the material of the sacrificial material layer 220 is amorphous silicon.
The process of forming the sacrificial material layer 220 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the sacrificial material layer 220 is a chemical vapor deposition process.
With continued reference to fig. 6, a first protective material layer 230 is formed on the sacrificial material layer 220.
In this embodiment, the first protection material layer 230 is used for forming a first protection layer subsequently.
In this embodiment, a first protection material layer 230 is formed on the sacrificial material layer 220, and the first protection material layer 230 can protect the sacrificial material layer 220 from silicon agglomeration when the sacrificial material layer 220 is exposed to air.
The material of the first protective material layer 230 includes silicon oxide or silicon nitride. In this embodiment, the material of the first protection material layer 230 includes silicon oxide.
The process of forming the first protective material layer 230 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the first protective material layer 230 is a chemical vapor deposition process, and the first protective material layer 230 with good compactness can be obtained by using the chemical vapor deposition process, which is beneficial to better protecting the sacrificial material layer 220.
The thickness of the first protective material layer 230 is in the range of
Figure BDA0002754417210000061
If the thickness of the first protective material layer 230 is less than
Figure BDA0002754417210000062
It does not function well to protect the sacrificial material layer 220; if the thickness of the first protective material layer 230 is greater than
Figure BDA0002754417210000063
The subsequent removal of the first protection layer may result in incomplete removal of the first protection layer.
In this embodiment, before forming the first protective material layer 230, the method further includes: a second protective material layer 240 is formed on the surface of the sacrificial material layer 220, and the first protective material layer 230 is located on the surface of the second protective material layer 240.
In other embodiments, the second protective material layer 240 may not be formed.
In this embodiment, the second protection material layer 240 is also used for protecting the sacrificial material layer 220, and the sacrificial material layer 220 can be prevented from being exposed to the air to the maximum extent by the double-layer protection, so as to prevent the surface of the sacrificial material layer 220 from generating ravines, which is beneficial for improving the roughness of the surface of the sacrificial material layer 220.
In this embodiment, the method for forming the second protection material layer 240 includes: the sacrificial material layer 220 is subjected to an oxidation process, and the second protective material layer 240 is formed on the surface of the sacrificial material layer 220.
In this embodiment, the parameters of the oxidation treatment include: and introducing oxygen, wherein the gas flow of the oxygen is 100-200 sccm, and the process temperature is 30-50 ℃.
In this embodiment, since the material of the sacrificial material layer 220 is amorphous silicon, the material of the second protective material layer 240 formed after the oxidation process includes silicon oxide.
Referring to fig. 7, a patterned layer 250 is formed on the first protective material layer 230, and the patterned layer 250 has a patterned opening 251 therein, wherein the patterned opening 251 defines a position and a size of a first opening to be formed.
In this embodiment, the patterning layer 250 is a patterned photoresist layer.
With continued reference to fig. 7, a portion of the first protective material layer 230 and the sacrificial material layer 220 are implanted with dopant ions using the patterned layer 250 as a mask.
In this embodiment, doped ions are implanted into the first protective material layer 230 exposed by the patterned opening 251 and the sacrificial material layer 220 thereunder.
In this embodiment, implanting dopant ions into a portion of the second protection material layer 240 is further included.
In this embodiment, doping ions are implanted into a portion of the first protective material layer 230, the second protective material layer 240 and the sacrificial material layer 220, which is suitable for increasing a removal selection ratio between the first protective material layer 230, the second protective material layer 240 and the sacrificial material layer 220 in which doping ions are not implanted and the first protective material layer 230, the second protective material layer 240 and the sacrificial material layer 220 in which doping ions are implanted, so that when the first protective material layer 230, the second protective material layer 240 and the sacrificial material layer 220 in which doping ions are implanted are subsequently removed, a process window of a removal process is favorably increased, and the pattern precision of a first opening formed subsequently is ensured.
The doping ions include carbon ions, boron ions, arsenic ions, gallium ions, or indium ions. In this embodiment, the dopant ions are boron ions.
In this embodiment, the process parameters for implanting the dopant ions include: the implantation energy is 5-11 keV, and the implantation dose is 1E 15-2E 15atoms/cm2。
Referring to fig. 8, the first protective material layer 230 and the sacrificial material layer 220 implanted with the dopant ions are removed, a sacrificial layer 221 and a first protective layer 231 which are separated from each other are formed on the material layer 210 to be etched, the first protective layer 231 is located on the sacrificial layer 221, a first opening 261 is formed between adjacent sacrificial layers 221, and the bottom of the first opening 261 exposes the surface of the material layer 210 to be etched.
In this embodiment, the method further includes: and removing the second protection material layer 240 implanted with the doped ions to form a second protection layer 241, where the second protection layer 241 is located on the surface of the sacrificial layer 221, and the first protection layer 231 is located on the surface of the second protection layer 241.
In this embodiment, the process of removing the first protective material layer 230, the second protective material layer 240 and the sacrificial material layer 220 implanted with the doped ions is a dry etching process.
In this embodiment, the first material layer 230 and the second protective material layer 240 implanted with the doped ions are removed by a first dry etching process until the surface of the sacrificial material layer 220 is exposed, and then the sacrificial material layer 220 implanted with the doped ions is removed by a second dry etching process. The parameters of the first dry etching process comprise: the etching atmosphere comprises CF4、CHF3The power of the mixed gas and He is 1000-1500W, the pressure is 5-15 mTorr, the temperature is 30-50 ℃, and the time is 5-10 s; the parameters of the second dry etching process comprise: the etching atmosphere includes Cl2、HBr、CF4And O2The etching power of the mixed gas is 500-1000W, the pressure is 5-8 mTorr, the temperature is 30-50 ℃, and the time is 20-40 s。
In this embodiment, after the sacrificial layer 221 is formed, an ashing process is used to remove the patterning layer 250.
In this embodiment, after the patterning layer 250 is removed, since the second protection layer 241 and the first protection layer 231 are covered on the top of the sacrificial layer 221, the sacrificial layer 221 can be prevented from being exposed in the air to cause silicon agglomeration, thereby improving the situation of generating ravines on the surface of the sacrificial layer 221, and when a mask material layer is formed subsequently, a part of the mask material layer is formed on the top surface of the first protection material layer 231, thereby preventing the mask material layer from being deposited in the ravines on the surface of the sacrificial layer 221, thereby solving the problem of the residue of the sacrificial layer 221 when the sacrificial layer 221 is removed, facilitating the improvement of the pattern transfer precision, and improving the final appearance of the target pattern.
Referring to fig. 9, a masking material layer 270 is formed on the bottom surface and the sidewall surface of the first opening 261, and the masking material layer 270 covers the top and sidewall surfaces of the first protection layer 231 and the sidewall surface of the sacrificial layer 221.
In this embodiment, the mask material layer 270 further covers the sidewall surface of the second protection layer 241.
The process of forming the masking material layer 270 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the mask material layer 270 is formed by an atomic layer deposition process.
The atomic layer deposition process forms the masking material layer 270 with a uniform thickness, so that the thickness of the masking material layer 270 on the bottom surface and the sidewall surface of the first opening 261 is consistent with the thickness of the masking material layer 270 on the top surface of the first protection layer 231, thereby facilitating the exposure of the material layer 210 to be etched on the bottom of the first opening 261 and the top surface of the first protection layer 231 during the subsequent etching of the masking material layer 270.
The material of the mask material layer 270 includes titanium oxide, titanium nitride, silicon oxide, or silicon oxynitride. In this embodiment, the material of the mask material layer 270 is titanium oxide.
Referring to fig. 10, the masking material layer 270 is removed from the bottom surface of the first opening 261 and the top surface of the first protection layer 231.
The process of removing the masking material layer 270 on the bottom surface of the first opening 261 and the top surface of the first protection layer 231 includes one or two of a dry etching process and a wet etching process.
The etching process has a high etching selection ratio to the material layer 210 to be etched, the first protection layer 231 and the mask material layer 270, and the etching rate of the etching process to the material layer 210 to be etched and the first protection layer 231 is far less than the etching rate to the mask material layer 270, so that when part of the mask material layer 270 is removed by etching, the material layer 210 to be etched and the first protection layer 231 are less damaged by etching, and therefore the sacrificial layer 221 covered by the first protection layer 231 is less damaged by etching, the stability of pattern transfer is improved, and the performance of the formed semiconductor structure is improved.
Referring to fig. 11, the first protection layer 231 and the sacrificial layer 221 are removed, and a second opening 262 is formed in the remaining mask material layer 270.
In this embodiment, the removing the second protection layer 241 is further included.
In this embodiment, the step of removing the first protection layer 231, the second protection layer 241 and the sacrificial layer 221 includes: the first and second protection layers 231 and 241 are removed by a first etching process, and the sacrificial layer 221 is removed by a second etching process.
In this embodiment, the first etching process is a wet etching process, and parameters of the wet etching process include: the etching solution comprises a diluted hydrofluoric acid solution, and the volume ratio of hydrofluoric acid to water of the diluted hydrofluoric acid solution is less than or equal to 1: 500.
The first etching process is beneficial to ensure that the second protection layer 241 and the first protection layer 231 on the sacrificial layer 221 are removed completely, and residues are avoided.
The first etching process has a high etching selection ratio for the mask material layer 270, the first protection layer 231 and the second protection layer 241, that is, the etching rate of the first etching process for the mask material layer 270 is far less than the etching rate for the first protection layer 231 and the second protection layer 241, so that the etching damage to the mask material layer 270 is small, the integrity of the pattern of the remaining mask material layer 270 is ensured, and the stability of pattern transfer is improved.
In this embodiment, the second etching process is a wet etching process, and the parameters of the wet etching process include: the etching solution includes ammonia.
The second etching process has a higher etching selection ratio for the mask material layer 270 and the sacrificial layer 221, that is, the etching rate of the second etching process for the mask material layer 270 is far less than that for the sacrificial layer 221, so that the etching damage to the mask material layer 270 is small, the pattern of the remaining mask material layer 270 is kept complete while the sacrificial layer 221 is completely removed, and the stability of pattern transfer is improved.
In this embodiment, due to the existence of the first protection layer 231 and the second protection layer 241, the silicon agglomeration phenomenon and the generation of voids on the top surface of the sacrificial layer 221 are reduced, the surface roughness of the sacrificial layer 221 is improved, and the mask material layer 270 is not formed on the top surface of the sacrificial layer 221, thereby avoiding the occurrence of the deposition of the mask material layer in the voids, so that the problem that the sacrificial layer remains in the second opening 262 when the second opening 262 is formed is solved, the morphology of the formed first opening 261 and the second opening 262 is ensured, and when the material layer 210 to be etched is subsequently etched along the first opening 261 and the second opening 262, the stability and the precision of pattern transfer are improved, thereby facilitating the improvement of the performance of the formed semiconductor.
Referring to fig. 12, the material layer to be etched 210 exposed by the first opening 261 and the second opening 262 is removed to form a target patterning layer 211.
After the material layer 210 to be etched exposed by the first opening 261 and the second opening 262 is removed, the patterns of the first opening 261 and the second opening 262 are transferred to the target pattern layer 211, a first groove 281 corresponding to the first opening 261 and a second groove 282 corresponding to the second opening 262 are formed in the target pattern layer 211, wherein the first opening 261 and the second opening 262 have better shapes and higher pattern accuracy, the pattern accuracy of the first groove 281 and the second groove 282 is correspondingly improved, the quality of a metal interconnection structure formed in the first groove 281 and the second groove 282 subsequently is improved, and the performance of a semiconductor structure is further improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a material layer to be etched is formed on the substrate;
forming a plurality of mutually discrete sacrificial layers and first protective layers on the material layer to be etched, wherein the first protective layers are positioned on the sacrificial layers, and a first opening is formed between every two adjacent sacrificial layers;
forming a mask material layer on the bottom and the side wall surface of the first opening, wherein the mask material layer covers the top and the side wall surface of the first protection layer and the side wall surface of the sacrificial layer;
removing the mask material layer on the bottom surface of the first opening and the top surface of the first protective layer;
removing the first protective layer and the sacrificial layer, and forming a second opening in the residual mask material layer;
and removing the material layer to be etched exposed out of the first opening and the second opening to form a target graph layer.
2. The method of claim 1, wherein the step of forming the plurality of mutually discrete sacrificial layers and the first protective layer on the layer of material to be etched comprises: forming a sacrificial material layer on the material layer to be etched; forming a first protective material layer on the sacrificial material layer; forming a patterning layer on the first protective material layer, wherein the patterning layer is internally provided with a patterning opening, and the patterning opening corresponds to the position and the size of the first opening; implanting doping ions into a part of the first protective material layer and the sacrificial material layer by taking the patterning layer as a mask; removing the first protective material layer and the sacrificial material layer implanted with the doped ions to form a sacrificial layer and a first protective layer which are mutually separated; and removing the patterning layer.
3. The method of claim 2, wherein the process of forming the first protective material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
4. The method of forming a semiconductor structure of claim 2, further comprising, prior to forming the first protective material layer on the sacrificial material layer: and forming a second protective material layer on the surface of the sacrificial material layer.
5. The method for forming a semiconductor structure according to claim 4, wherein the sacrificial material layer is subjected to oxidation treatment to form the second protective material layer; the technological parameters of the oxidation treatment comprise: providing oxygen, wherein the gas flow of the oxygen is 100-200 sccm, and the temperature is 30-50 ℃.
6. The method of forming a semiconductor structure of claim 1, wherein removing the first protective layer and the sacrificial layer comprises: and removing the sacrificial layer by adopting a second etching process after removing the first protective layer by adopting a first etching process.
7. The method of forming a semiconductor structure of claim 6, wherein the first etching process is a wet etching process; the parameters of the wet etching process comprise: the etching solution comprises a diluted hydrofluoric acid solution, and the volume ratio of hydrofluoric acid to water of the diluted hydrofluoric acid solution is less than or equal to 1: 500.
8. The method of forming a semiconductor structure of claim 6, wherein the second etching process is a wet etching process; the parameters of the wet etching process comprise: the etching solution includes ammonia.
9. The method of forming a semiconductor structure of claim 1, wherein a material of the first protective layer comprises silicon oxide or silicon nitride.
10. The method of claim 1, wherein a material of the sacrificial layer comprises amorphous silicon, amorphous carbon, or polysilicon.
11. The method of claim 1, wherein the material layer to be etched comprises a single material layer or a plurality of stacked material layers.
12. The method of claim 1, wherein the material of the masking material layer comprises titanium oxide, titanium nitride, silicon oxide, or silicon oxynitride.
13. The method of claim 1, wherein the process of forming the layer of masking material comprises a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
14. The method of forming a semiconductor structure of claim 2, wherein the dopant ions comprise carbon ions, boron ions, arsenic ions, gallium ions, or indium ions.
15. The method of claim 2, wherein the removing the first protective material layer and the sacrificial material layer implanted with the dopant ions is a dry etching process.
CN202011197435.1A 2020-10-30 2020-10-30 Method for forming semiconductor structure Pending CN114446780A (en)

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