CN114421980B - Intermittent frequency calibration OOK modulation transmitter circuit and control method - Google Patents

Abstract

The invention relates to an intermittent frequency calibration OOK modulation transmitter circuit, which comprises a voltage controlled oscillator VCO, a loop frequency divider, a clock generator, a frequency discriminator, a phase difference-voltage converter and a transmitting antenna; the frequency discriminator is respectively connected with the loop frequency divider, the clock generator and the phase difference-voltage converter; the VCO is respectively connected with the transmitting antenna, the loop frequency divider, the clock generator and the phase difference-voltage converter; the loop frequency divider is also connected with the clock generator and the transmitting antenna respectively; the transmitter circuit inputs the DATA signal DATA to be transmitted and the system clock CKs, and outputs the DATA signal DATA to be transmitted and the system clock CKs as the radio frequency signal RFO after OOK modulation. The invention has the advantages of high frequency calibration speed, high calibration precision, low power consumption and intermittent frequency calibration.

Description

Intermittent frequency calibration OOK modulation transmitter circuit and control method

Technical Field

The invention relates to the field of modulation transmitter control, in particular to an intermittent frequency calibration OOK modulation transmitter circuit and a control method.

Background

Many OOK modulation transmitters in engineering practice transmit directly with an oscillator connected to an antenna to reduce power consumption and cost. However, due to the lack of a frequency synthesizer, the carrier frequency of such a transmitter has a significant deviation, so that it is difficult to meet certain engineering technical index requirements.

Disclosure of Invention

In view of the above, the present invention aims to provide an intermittent frequency calibration OOK modulation transmitter circuit and a control method, which can directly calibrate the frequency of an oscillator during OOK transmission, and has the advantages of fast calibration speed, high calibration precision, low power consumption and intermittent frequency calibration.

In order to achieve the above purpose, the invention adopts the following technical scheme:

an intermittent frequency calibration OOK modulation transmitter circuit comprises a voltage controlled oscillator VCO, a loop frequency divider, a clock generator, a frequency discriminator and a phase difference-voltage converter; the transmitter circuit inputs the DATA signal DATA to be transmitted and the system clock CKs, and outputs the DATA signal DATA to be transmitted and the system clock CKs as the radio frequency signal RFO after OOK modulation. The frequency discriminator is respectively connected with the loop frequency divider, the clock generator and the phase difference-voltage converter; the VCO is respectively connected with the transmitting antenna, the loop frequency divider, the clock generator and the phase difference-voltage converter; the loop frequency divider is also connected with the clock generator and the transmitting antenna respectively;

further, the inputs of the loop divider are a signal IN, an enable signal EN1 and an enable signal EN2, and the outputs thereof are a signal CKB and a count value mn, specifically:

setting a loop divider count value mn to zero when the EN2 signal is at an active level; when the EN1 signal is at an active level and the EN2 signal is at an inactive level, the loop frequency divider counts up the period of the input signal IN and saves the counting result IN mn; when EN1 is at an inactive level, mm remains unchanged; stopping counting when the EN2 signal is at an inactive level and the count value mn is equal to M; when the EN1 signal is at an active level and when the count mn is greater than zero and less than M, the output CKB is at an active level; otherwise, the level is invalid.

Further, the clock generator has inputs of reference clock signal CKs, count value mn and enable signal EN, and outputs of reset enable signal rst_o, regeneration control signal RPC and reference signal CKR; the clock generator circularly generates RST_ O, RPC and CKR signals continuously in 3 links of reset, pulse generation, comparison and the like, and the specific control is as follows:

1) Generating an active level pulse with a width T1 on the RST_O signal when the reset link is in; then, the clock generator jumps to a pulse generation link;

2) When the jump is to the pulse generation link, the clock generator sets the count value pn to zero, starts to count up the period of the reference clock signal CKs and stores the count value in pn; the counting conditions are as follows: counting when the EN signal is at an active level; when the EN signal is at an inactive level, pn remains unchanged; when the count value pn is equal to P, the count value pn is kept unchanged; when the count value pn is greater than 0 and less than P and the EN signal is at an active level, CKR is at an active level, otherwise, CKR is at an inactive level; after the count values mn and pn reach the coefficients M and P respectively, the clock generator jumps into a comparison link;

3) When the jump is to the comparison link, the clock generator generates an effective level pulse with the width of T2 on the RPC signal; the clock generator then jumps to the reset link.

Further, the voltage-controlled oscillator has an input of a control signal Vtune and an enable signal en_vco, and an output of an oscillation signal RFO, and the control is specifically as follows: when the en_vco signal is at an active level, the voltage controlled oscillator generates an output oscillating signal RFO; the voltage-controlled oscillator frequency corresponds to the Vtune voltage one by one.

Further, the input of the frequency discriminator is a signal CKB, CKR, RPC and RST_FD, and the output of the frequency discriminator is signals UP and DW, and the frequency discriminator is reset when the RST_FD signal is at an effective level; after the frequency discriminator is reset, the effective level pulse widths on the CKR signal and the CKB signal are discriminated respectively, and the results are accumulated and stored; when the RPC signal becomes the effective level, the frequency discriminator compares the difference of the accumulated stored values of the pulse width and converts the difference into a phase difference between the pulses of the effective level on the output signal UP and the DW; conversely, when the pulse width on the CKB signal is smaller than the pulse width on the CKR signal, the output signal DW is turned to an active level earlier than UP; when the pulse width on the CKB signal is equal to the pulse width on the CKR signal, the output signals DW and UP are flipped to active levels simultaneously.

Further, the input of the phase difference-voltage converter is signals UP and DW, the output of the phase difference-voltage converter is signals Vtune, and the phase difference-voltage converter is specifically controlled to accumulate the phase difference between the effective level pulses on the UP and the DW and convert the accumulated result into one-to-one corresponding voltages on the signals Vtune. Therefore, if the signal DW becomes an active level earlier than UP, the phase-difference-to-voltage converter output signal Vtune decreases in voltage; if the signals DW and UP become active levels at the same time, the voltage of the output signal Vtune of the phase difference-voltage converter is kept unchanged; if the signal UP goes active level earlier than the DW, the phase-difference-to-voltage converter increases the output signal Vtune voltage.

A method of controlling an intermittent frequency calibration OOK modulation transmitter circuit, comprising the steps of:

the OOK modulated DATA signal DATA controls the entire circuitry, and when DATA is at an active level, the voltage controlled oscillator generates an oscillating signal RFO; RFO is input to the loop divider; the loop frequency divider generates a frequency-divided signal CKB; simultaneously, the clock generator generates a reset enabling signal RST_O, a regeneration control signal RPC and a frequency-divided reference signal CKR;

CKB, CKR, RPC, RST _O is input to a frequency discriminator to generate output signals UP and DW with phase differences;

the UP and the DW are input into a phase difference-voltage converter, and the phase difference-voltage converter accumulates the phase difference of the UP and the DW and converts the accumulated value into voltages corresponding to the signal Vtune one by one;

the feedback signal Vtune is input to the voltage controlled oscillator to change the oscillation frequency of the voltage controlled oscillator, and the whole circuit also carries out cyclic calibration on the VCO frequency as the clock generator works in the cyclic mode, so that the oscillation frequency is the same as the preset value.

Compared with the prior art, the invention has the following beneficial effects:

the invention realizes the frequency calibration of the oscillator directly when the OOK emission is carried out, and has the advantages of high calibration speed, high calibration precision, low power consumption and intermittent frequency calibration.

Drawings

FIG. 1 is a schematic diagram of the structure of the present invention;

FIG. 2 is a schematic diagram of a loop divider control in accordance with one embodiment of the present invention;

FIGS. 3 and 4 are diagrams illustrating clock generator control in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram of a frequency discriminator according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a phase difference-voltage converter according to an embodiment of the present invention;

fig. 7 is a timing diagram of intermittent frequency calibration of a transmitter circuit in accordance with an embodiment of the present invention.

Detailed Description

The invention will be further described with reference to the accompanying drawings and examples.

The figure assumes a high level as an active level and a low level as an inactive level.

Referring to fig. 1, the present invention provides an intermittent frequency calibration OOK modulation transmitter circuit, which includes a voltage controlled oscillator VCO, a loop divider, a clock generator, a frequency discriminator, a phase difference-voltage converter and a transmitting antenna; the frequency discriminator is respectively connected with the loop frequency divider, the clock generator and the phase difference-voltage converter; the VCO is respectively connected with the transmitting antenna, the loop frequency divider, the clock generator and the phase difference-voltage converter; the loop frequency divider is also connected with the clock generator and the transmitting antenna respectively; the transmitter circuit inputs the DATA signal DATA to be transmitted and the system clock CKs, and outputs the DATA signal DATA to be transmitted and the system clock CKs as the radio frequency signal RFO after OOK modulation.

IN the present embodiment, the inputs of the loop divider are the signal IN, the enable signal EN1 and the enable signal EN2, and the outputs thereof are the signal CKB and the count value mn. The specific control is as follows:

when the EN2 signal is at an active level, the loop divider count mn is set to zero. When the EN1 signal is at an active level and the EN2 signal is at an inactive level, the loop frequency divider counts up the period of the input signal IN and saves the counting result IN mn; when EN1 is at an inactive level, mm remains unchanged; when the EN2 signal is at an inactive level and the count value mn is equal to M, counting is stopped. When the EN1 signal is at an active level and when the count mn is greater than zero and less than M, the output CKB is at an active level; otherwise, the level is invalid. The working principle is shown in figure 2.

The inputs of the clock generator in this embodiment are the reference clock signal CKs, the count value mn, and the enable signal EN, and the outputs thereof are the reset enable signal rst_o, the regeneration control signal RPC, and the reference signal CKR.

The clock generator continuously and circularly generates RST_ O, RPC and CKR signals in 3 links of reset, pulse generation, comparison and the like, and the specific working method comprises the following steps: as shown in fig. 3 and 4, the specific control is as follows:

1) Generating an active level pulse with a width T1 on the RST_O signal when the reset link is in; the clock generator then jumps to the pulse generation link.

2) When the jump is to the pulse generation link, the clock generator sets the count value pn to zero, starts to count up the period of the reference clock signal CKs and stores the count value in pn; the counting conditions are as follows: counting when the EN signal is at an active level; when the EN signal is at an inactive level, pn remains unchanged; when the count value pn is equal to P, the count value pn remains unchanged. When the count value pn is greater than 0 and less than P and the EN signal is active, CKR is active and otherwise inactive. After the count values mn and pn reach the coefficients M and P respectively, the clock generator jumps into the comparison link.

3) When the jump is to the comparison link, the clock generator generates an effective level pulse with the width of T2 on the RPC signal; the clock generator then jumps to the reset link.

In this embodiment, the input of the voltage controlled oscillator is a control signal Vtune and an enable signal en_vco, and the output thereof is an oscillating signal RFO, which is specifically controlled as follows:

the working method of the voltage-controlled oscillator comprises the following steps: when the en_vco signal is at an active level, the voltage controlled oscillator generates an output oscillating signal RFO; the voltage-controlled oscillator frequency corresponds to the Vtune voltage one by one.

The inputs of the discriminator in this embodiment are signals CKB, CKR, RPC and RST FD, and the outputs are signals UP and DW, which are specifically controlled as follows: as shown in fig. 5, the discriminator is reset when the rst_fd signal is at an active level; after the frequency discriminator is reset, the effective level pulse widths on the CKR signal and the CKB signal are discriminated respectively, and the results are accumulated and stored; when the RPC signal becomes active level, the discriminator will compare the difference in the accumulated stored values of the pulse width and convert the difference into a phase difference between the active level pulses on the output signals UP and DW. When the pulse width on the CKB signal is larger than that on the CKR signal, the output signal UP is turned to be an effective level earlier than the DW; conversely, when the pulse width on the CKB signal is smaller than the pulse width on the CKR signal, the output signal DW is turned to an active level earlier than UP; when the pulse width on the CKB signal is equal to the pulse width on the CKR signal, the output signals DW and UP are flipped to active levels simultaneously.

In this embodiment, the inputs of the phase difference-voltage converter are signals UP and DW, and the output thereof is signal Vtune, which is specifically controlled as follows: as shown in fig. 6, the phase difference-voltage converter accumulates the phase difference between the active level pulses on UP and DW and converts the accumulated result into a one-to-one voltage on the signal Vtune. Therefore, if the signal DW becomes an active level earlier than UP, the phase-difference-to-voltage converter output signal Vtune decreases in voltage; if the signals DW and UP become active levels at the same time, the voltage of the output signal Vtune of the phase difference-voltage converter is kept unchanged; if the signal UP goes active level earlier than the DW, the phase-difference-to-voltage converter increases the output signal Vtune voltage.

In this embodiment, the OOK modulated DATA signal DATA controls the entire circuitry, and when DATA is at an active level, the voltage controlled oscillator generates an oscillating signal RFO; RFO is input to the loop divider; the loop frequency divider generates a frequency-divided signal CKB; at the same time, the clock generator generates a reset enable signal rst_o, a regeneration control signal RPC, and a divided reference signal CKR.

CKB, CKR, RPC, RST _o is input to the discriminator to produce output signals UP and DW having a phase difference. The UP and DW are input to a phase difference-to-voltage converter which accumulates the UP and DW phase differences and converts the accumulated values into voltages in one-to-one correspondence on the signal Vtune. The feedback signal Vtune is input to the voltage controlled oscillator to change the oscillation frequency of the voltage controlled oscillator. Since the clock generator is operated in a cyclic mode, the entire circuit will also cyclically calibrate the VCO frequency to the same oscillation frequency as the preset value.

Example 1:

the voltage controlled oscillator frequency is set to be positively correlated with the Vtune voltage, i.e., the higher the Vtune voltage, the higher the frequency of the RFO signal. When the frequency of the oscillating signal RFO is smaller than the preset oscillating frequency, the pulse width on the CKB signal is larger than the pulse width on the CKR signal, and Vtune is increased after passing through the frequency discriminator and the phase difference-voltage converter, and finally the oscillating frequency of the voltage-controlled oscillator is increased. Conversely, when the frequency of the oscillating signal RFO is greater than the preset oscillating frequency, vtune decreases, and finally the oscillating frequency of the voltage-controlled oscillator decreases. When the frequency of the oscillating signal RFO is equal to the preset oscillating frequency, vtune remains unchanged, and the oscillating frequency reaches the preset frequency.

Taking the high level as the active level and the falling edge as the active edge as an example. Fig. 7 shows the timing of the intermittent frequency calibration of the transmitter circuit.

Resetting the loop divider, the clock generator, and the discriminator when the rst_o signal goes high; otherwise, when DATA is high, the loop divider and clock generator generate active level pulses on CKB, CKR, respectively, in the manner described above. The clock generator then generates pulses on the RPC signal and the rst_o signal in the manner described above.

Under the drive of RST_O and RPC, the frequency discriminator converts the pulse width difference between CKR and CKB signals into the phase difference between output signals UP and DW; the phase difference-voltage converter converts the phase difference of UP and DW into a proportional voltage difference Vtune. The voltage-controlled oscillator changes the oscillation frequency according to the input feedback signal Vtune.

To illustrate the problem, it is assumed that in the ith cycle of the clock generator, the frequency of the oscillating signal RFO is lower than the preset oscillating frequency, which causes the pulse width on the CKB signal to be greater than the pulse width on the CKR signal, and the Vtune is increased after passing through the discriminator and the phase-difference-voltage converter, so that the oscillating frequency of the voltage-controlled oscillator is increased. Assuming that the frequency of the oscillating signal RFO is higher than the preset oscillating frequency in the i+1th cycle of the clock generator, the modulation action of the circuit is opposite to the i-th cycle.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims (5)

1. An intermittent frequency calibration OOK modulation transmitter circuit is characterized by comprising a voltage controlled oscillator VCO, a loop frequency divider, a clock generator, a frequency discriminator and a phase difference-voltage converter; the frequency discriminator is respectively connected with the loop frequency divider, the clock generator and the phase difference-voltage converter; the VCO is respectively connected with the loop frequency divider, the clock generator and the phase difference-voltage converter; the loop frequency divider is also connected with a clock generator; the transmitter circuit inputs a DATA signal DATA of 2 system DATA to be transmitted and a system clock CKs, and outputs a radio frequency signal RFO after OOK modulation;

the input of the voltage-controlled oscillator is a control signal Vtune and an enable signal en_vco, and the output is an oscillation signal RFO, and the control is specifically as follows: when the en_vco signal is at an active level, the voltage controlled oscillator generates an output oscillating signal RFO; the frequency of the voltage-controlled oscillator corresponds to the Vtune voltage one by one;

the input of the phase difference-voltage converter is output signals UP and DW of the frequency discriminator, the output of the phase difference-voltage converter is signals Vtune, and the phase difference-voltage converter is specifically controlled to accumulate the phase difference between the effective level pulses on the UP and the DW and convert the accumulated result into one-to-one corresponding voltages on the signals Vtune; therefore, if the signal DW becomes an active level earlier than UP, the phase-difference-to-voltage converter output signal Vtune decreases in voltage; if the signals DW and UP become active levels at the same time, the voltage of the output signal Vtune of the phase difference-voltage converter is kept unchanged; if the signal UP goes active level earlier than the DW, the phase-difference-to-voltage converter increases the output signal Vtune voltage.

2. An intermittent frequency calibration OOK modulation transmitter circuit according to claim 1, wherein the inputs of the loop divider are signal IN, enable signal EN1 and enable signal EN2, the outputs of which are signal CKB and count mn, IN particular:

setting a loop divider count value mn to zero when the EN2 signal is at an active level; when the EN1 signal is at an active level and the EN2 signal is at an inactive level, the loop frequency divider counts up the period of the input signal IN and saves the counting result IN mn; when EN1 is at an inactive level, mn remains unchanged; stopping counting when the EN2 signal is at an inactive level and the count value mn is equal to M; when the EN1 signal is at an active level and when the count mn is greater than zero and less than M, the output CKB is at an active level; otherwise, the level is invalid.

3. An intermittent frequency calibration OOK modulation transmitter circuit according to claim 2, wherein the clock generator has inputs of a reference clock signal CKs, a count value mn and an enable signal EN, and outputs of the clock signal CKs are a reset enable signal rst_o, a regeneration control signal RPC and a reference signal CKR; wherein the count value mn is the count value mn in the output signal of the loop frequency divider; the clock generator circularly generates RST_ O, RPC and CKR signals continuously in 3 links of reset, pulse generation, comparison and the like, and the specific control is as follows:

1) Generating an active level pulse with a width T1 on the RST_O signal when the reset link is in; then, the clock generator jumps to a pulse generation link;

2) When the jump is to the pulse generation link, the clock generator sets the count value pn to zero, starts to count up the period of the reference clock signal CKs and stores the count value in pn; the counting conditions are as follows: counting when the EN signal is at an active level; when the EN signal is at an inactive level, pn remains unchanged; when the count value pn is equal to P, the count value pn is kept unchanged; when the count value pn is greater than 0 and less than P and the EN signal is at an active level, CKR is at an active level, otherwise, CKR is at an inactive level; after the count values mn and pn reach the coefficients M and P respectively, the clock generator jumps into a comparison link;

3) When the jump is to the comparison link, the clock generator generates an effective level pulse with the width of T2 on the RPC signal; the clock generator then jumps to the reset link.

4. An intermittent frequency calibration OOK modulated transmitter circuit according to claim 3, characterized in that the inputs of the discriminator are the output signals CKB, CKR, RPC of the loop divider and clock generator and RST FD, the outputs of which are signals UP and DW, in particular controlled by resetting the discriminator when the RST FD signal is at an active level; after the frequency discriminator is reset, the effective level pulse widths on the CKR signal and the CKB signal are discriminated respectively, and the results are accumulated and stored; when the RPC signal becomes the effective level, the frequency discriminator compares the difference of the accumulated stored values of the pulse width and converts the difference into a phase difference between the pulses of the effective level on the output signal UP and the DW; conversely, when the pulse width on the CKB signal is smaller than the pulse width on the CKR signal, the output signal DW is turned to an active level earlier than UP; when the pulse width on the CKB signal is equal to the pulse width on the CKR signal, the output signals DW and UP are flipped to active levels simultaneously.

5. A method of controlling an intermittent frequency calibration OOK modulation transmitter circuit according to any one of claims 1-4, comprising the steps of:

the OOK modulated DATA signal DATA controls the entire circuitry, and when DATA is at an active level, the voltage controlled oscillator generates an oscillating signal RFO; RFO is input to the loop divider; the loop frequency divider generates a frequency-divided signal CKB; simultaneously, the clock generator generates a reset enabling signal RST_O, a regeneration control signal RPC and a frequency-divided reference signal CKR;

CKB, CKR, RPC, RST _O is input to a frequency discriminator to generate output signals UP and DW with phase differences;

the UP and the DW are input into a phase difference-voltage converter, and the phase difference-voltage converter accumulates the phase difference of the UP and the DW and converts the accumulated value into voltages corresponding to the signal Vtune one by one;

the feedback signal Vtune is input to the voltage controlled oscillator to change the oscillation frequency of the voltage controlled oscillator, and the whole circuit also carries out cyclic calibration on the VCO frequency as the clock generator works in the cyclic mode, so that the oscillation frequency is the same as the preset value.

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