CN114420568A - Memory manufacturing method and memory - Google Patents

Memory manufacturing method and memory Download PDF

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Publication number
CN114420568A
CN114420568A CN202111630356.XA CN202111630356A CN114420568A CN 114420568 A CN114420568 A CN 114420568A CN 202111630356 A CN202111630356 A CN 202111630356A CN 114420568 A CN114420568 A CN 114420568A
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barrier layer
conductive layer
layer
substrate
phase structure
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黄驰
吕术亮
马亮
李�远
孙祥烈
万先进
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/2954—Coating
    • H01L2224/29599—Material
    • H01L2224/296—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29681—Tantalum [Ta] as principal constituent

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
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Abstract

The embodiment of the disclosure discloses a memory, a manufacturing method thereof and a semiconductor device, wherein the manufacturing method comprises the following steps: forming a first barrier layer having a first cell structure type on a first substrate; forming a first conductive layer overlying the first barrier layer; the crystal growth direction of the first conducting layer is a first crystal growth direction, and the lattice matching degree of the first conducting layer and the first barrier layer meets a preset condition.

Description

Memory manufacturing method and memory
The present application is a divisional application of a patent with an application date of 2020, 01/02, an application number of 202010000803.2, entitled method for manufacturing a memory and a memory.
Technical Field
The disclosed embodiments relate to the field of integrated circuits, and in particular, to a memory and a manufacturing method thereof.
Background
In the field of integrated circuits, wafer bonding (bonding) techniques have been developed in order to achieve larger storage capacities per unit area. Specifically, two wafers with different functions are attached through bonding between the conductive layers, so that the different wafers are combined into a whole.
However, in the existing bonding technology, the bonding effect is poor, and the yield of the memory formed by attaching two wafers with different functions is low.
Disclosure of Invention
In view of the above, the present disclosure provides a method for manufacturing a memory and a memory.
According to a first aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a memory, including:
forming a first barrier layer having a first crystal phase structure on a first substrate;
forming a first conductive layer overlying the first barrier layer; the first conductive layer has a second crystal phase structure, and the lattice matching degree of the first conductive layer having the second crystal phase structure and the first barrier layer having the first crystal phase structure satisfies a preset condition.
Optionally, the method further comprises:
forming a second barrier layer on the first substrate; the diffusion rate of the first conductive layer diffusing to the second barrier layer is smaller than that of the first conductive layer diffusing to the first barrier layer;
the forming a first barrier layer having a first crystalline phase structure on a first substrate includes:
and forming the first barrier layer with the first crystalline phase structure on the first substrate to cover the second barrier layer based on the morphology of the second barrier layer.
Optionally, the method further comprises:
forming an insulating layer over the first substrate having the second conductive layer;
forming a channel in the insulating layer; wherein at least a partial region of the second conductive layer is exposed through the channel;
the forming a second barrier layer on the first substrate includes:
forming the second barrier layer covering the side wall and the bottom of the channel on the first substrate based on the topography of the channel; the second barrier layer is located between the insulating layer and the first barrier layer, and located between the second conductive layer and the first barrier layer.
Optionally, the method further comprises:
attaching a second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed; wherein the second substrate is connected to the first conductive layer.
Optionally, the method further comprises:
forming a third conductive layer with the second crystal phase structure on the surface of the second substrate;
the attaching the second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed includes:
and attaching the third conductive layer to the first conductive layer.
Optionally, the first barrier layer further has a third crystalline phase structure;
the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure satisfies a preset condition, and the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure includes:
the first conductive layer of the second crystal phase structure and the first barrier layer of the first crystal phase structure have a first lattice matching degree, the first conductive layer of the second crystal phase structure and the first barrier layer of the third crystal phase structure have a second lattice matching degree, and the first lattice matching degree is greater than the second lattice matching degree. According to a second aspect of embodiments of the present disclosure, there is provided a memory comprising:
a first substrate;
a first conductive layer; wherein the first conductive layer has a second crystal phase structure;
a first barrier layer having a first crystalline phase structure between the first substrate and the first conductive layer; wherein a lattice matching degree of the first barrier layer having the first crystal phase structure and the first conductive layer having the second crystal phase structure satisfies a preset condition.
Optionally, the memory further comprises:
a second barrier layer between the first substrate and the first barrier layer; and the diffusion rate of the first conductive layer diffusing to the second barrier layer is smaller than that of the first conductive layer diffusing to the first barrier layer.
Optionally, the memory further comprises:
a second conductive layer on the first substrate;
an insulating layer covering the second conductive layer; the second barrier layer covers the side wall and the bottom of the channel in the insulating layer, is positioned between the insulating layer and the first barrier layer, and is positioned between the second conducting layer and the first barrier layer.
Optionally, the memory further comprises:
a second substrate attached to the first substrate on which the first barrier layer and the first conductive layer are formed; wherein the second substrate is connected to the first conductive layer.
Optionally, the second substrate further comprises:
and the third conducting layer is provided with the second crystal phase structure and is connected with the first conducting layer.
Optionally, the first barrier layer further has a third crystalline phase structure;
the first conductive layer of the second crystal phase structure and the first barrier layer of the first crystal phase structure have a first lattice matching degree, the first conductive layer of the second crystal phase structure and the first barrier layer of the third crystal phase structure have a second lattice matching degree, and the first lattice matching degree is greater than the second lattice matching degree. Optionally, the material constituting the first barrier layer includes: tantalum;
the material constituting the first conductive layer includes: copper.
Generally, the first conductive layer has a multi-crystalline phase structure. Compared with the first conductive layer with other crystal phase structures except the second crystal phase structure, the diffusion coefficient of the first conductive layer with the second crystal phase structure is higher, and the effect of diffusion generated in the bonding process is better.
Because the lattice matching degree of the first barrier layer with the first crystal phase structure and the first conductive layer with the second crystal phase structure meets the preset condition, the first barrier layer with the first crystal phase structure is formed on the first substrate, and then the first conductive layer covering the first barrier layer is formed, so that the first barrier layer with the first crystal phase structure can promote the formation of the first conductive layer with the second crystal phase structure, the diffusion of the first conductive layer in the bonding process is facilitated, the contact area of the bonding interface is increased, the defects generated in the bonding process are reduced, the quality of the bonding interface is improved, and the yield of the formed memory is ensured.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a memory according to an embodiment of the disclosure;
FIG. 2a shows a crystalline phase structure of a first barrier layer according to an embodiment of the disclosure;
FIG. 2b is a crystalline phase structure of another first barrier layer provided by embodiments of the present disclosure;
FIG. 3 is a partial schematic diagram of a memory according to an embodiment of the disclosure;
FIG. 4 is a partial schematic diagram of another memory provided by an embodiment of the present disclosure;
FIG. 5 is a partial schematic diagram of yet another memory provided by an embodiment of the present disclosure;
FIG. 6 is a partial schematic diagram of yet another memory provided by an embodiment of the present disclosure;
fig. 7a to 7c are schematic diagrams illustrating a method for manufacturing a memory according to an embodiment of the disclosure;
FIG. 8a is an X-ray diffraction pattern of a memory fabricated by a method according to an embodiment of the present disclosure;
FIG. 8b is a graph of resistivity of a memory fabricated by a different method provided by an embodiment of the present disclosure;
FIG. 9a is an X-ray diffraction pattern of another memory fabricated by a different method provided by an embodiment of the present disclosure;
FIG. 9b is a graph of resistivity of another memory fabricated by a different method according to an embodiment of the present disclosure;
FIG. 9c is an electron backscatter diffraction pattern of another memory fabricated by a different method provided by an embodiment of the disclosure;
fig. 9d is a content diagram of the first conductive layer with the second crystal phase structure in another memory fabricated by a different method according to an embodiment of the disclosure.
Detailed Description
The technical solution of the present invention will be further elaborated with reference to the drawings and the embodiments. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present invention is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the embodiment of the present application, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed therebetween.
In the embodiments of the present application, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.
The technical means described in the embodiments of the present invention may be arbitrarily combined without conflict.
FIG. 1 is a flow chart illustrating a method of fabricating a memory according to an exemplary embodiment. Referring to fig. 1, the manufacturing method includes the following steps:
s100: forming a first barrier layer having a first crystal phase structure on a first substrate;
s110: forming a first conductive layer covering the first barrier layer; the first conductive layer has a second crystal phase structure, and the lattice matching degree of the first conductive layer having the second crystal phase structure and the first barrier layer having the first crystal phase structure meets a preset condition.
Illustratively, in step S100, the first barrier layer having the first crystalline phase structure may be formed by Physical Vapor Deposition (PVD).
Specifically, taking tantalum (Ta) as an example of a composition material of the first barrier layer, a method for forming the first barrier layer by physical vapor deposition may be: and bombarding the tantalum target material by argon particles, so that the tantalum particles in the tantalum target material fall off from the tantalum target material and are deposited on the first substrate below the tantalum target material.
In step S110, taking copper (Cu) as an example, the first conductive layer may be formed by physical vapor deposition; alternatively, a seed layer (seed) having a small thickness may be formed by physical vapor deposition, and then the first conductive layer may be formed by Electro-Chemical plating (ECP) based on the seed layer.
Generally, the composition material of the first barrier layer forms a plurality of crystalline phase structures under different conditions. For example, when the constituent material of the first barrier layer is tantalum, the crystalline phase structure of tantalum may include an α phase and a β phase. Fig. 2a shows the lattice structure of an alpha phase tantalum and fig. 2b shows the lattice structure of a beta phase tantalum. As shown in fig. 2a and 2b, the lattice structure of the α -phase tantalum is a Body Centered Cubic (BCC) structure, and the lattice structure of the β -phase tantalum is not a Body Centered Cubic structure. Wherein the resistivity of the alpha phase tantalum is less than the resistivity of the beta phase tantalum.
During the growth of the copper film, the growth of copper particles in the copper lattice has three orientations of (001), (101), and (111). Compared with copper particles grown along the (001) or (101) orientation, the copper particles grown along the (111) orientation have the highest diffusion coefficient, so that the copper particles grown along the (111) orientation are easier to diffuse at a bonding interface during bonding, the contact area of the bonding interface is increased, and defects generated at the bonding interface are reduced.
It is understood that, in order to improve the quality of the bonding interface, when the first conductive layer is a copper film, it is necessary to increase the content of copper particles growing in the (111) orientation in the copper film. Here, the second crystal phase structure is a Face Centered Cubic (FCC) structure composed of (111) oriented copper particles.
Illustratively, the lattice matching degree of the first barrier layer of the different crystal phase structure and the first conductive layer having the second crystal phase structure is different. Therefore, the first barrier layer with high lattice matching degree with the first conductive layer with the second crystal phase structure can be formed firstly, so that the unit cell content of the second crystal phase structure in the first conductive layer is increased in the forming process of the first conductive layer, and the diffusion coefficient of the first conductive layer is further increased.
It is understood that the preset conditions may include: the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure is larger than a preset threshold value. Specifically, the preset threshold may be a lattice matching degree of the first conductive layer having the second crystal phase structure and the first blocking layer having a crystal phase structure other than the first crystal phase structure.
Illustratively, the first barrier layer further has a third crystalline phase structure;
the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure satisfies a preset condition, and the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure includes:
the first conductive layer of the second crystal phase structure and the first barrier layer of the first crystal phase structure have a first lattice matching degree, the first conductive layer of the second crystal phase structure and the first barrier layer of the third crystal phase structure have a second lattice matching degree, and the first lattice matching degree is larger than the second lattice matching degree. Here, the preset threshold is the second lattice matching degree. Specifically, the first conductive layer of the second crystal phase structure may be a copper film grown in a (111) direction, the first barrier layer of the first crystal phase structure may be β -phase tantalum, and the first barrier layer of the third crystal phase structure may be α -phase tantalum. The lattice matching degree of the beta-phase tantalum and the copper film growing along the (111) direction is a first lattice matching degree, and the lattice matching degree of the alpha-phase tantalum and the copper film growing along the (111) direction is a second lattice matching degree, because the first lattice matching degree is higher than the second lattice matching degree, the beta-phase tantalum is more favorable for promoting the epitaxial growth of copper particles in the copper film according to the (111) orientation compared with the alpha-phase tantalum.
It can be understood that, in order to increase the contact area of the bonding interface, reduce defects generated at the bonding interface, improve the reliability of the bonding interface, and improve the chip performance, the beta-phase tantalum can be selected as the first barrier layer having the first crystal phase structure.
According to the embodiment of the disclosure, the first barrier layer with the first crystal phase structure is formed on the first substrate, and then the first conductive layer covering the first barrier layer is formed, so that the first barrier layer with the first crystal phase structure can promote the formation of the first conductive layer with the second crystal phase structure, the diffusion of the first conductive layer in the bonding process is facilitated, the contact area of the bonding interface is increased, the defects generated in the bonding process are reduced, the quality of the bonding interface is improved, and the yield of the formed memory is ensured.
In some embodiments, the method further comprises:
forming a second barrier layer on the first substrate; the diffusion rate of the first conductive layer diffusing to the second barrier layer is less than that of the first conductive layer diffusing to the first barrier layer;
s100 may include:
and forming a first barrier layer with a first crystalline phase structure on the first substrate and covering the second barrier layer based on the morphology of the second barrier layer.
Illustratively, the constituent material of the second barrier layer may include tantalum nitride (TaN). At this time, the forming of the second barrier layer on the first substrate may include: and introducing nitrogen into the cavity in which the first substrate is temporarily stored, and bombarding the tantalum target material in the cavity by using plasma, so that tantalum particles bombarded from the tantalum target material react with the nitrogen particles to generate tantalum nitride, and the generated tantalum nitride is deposited on the surface of the first substrate to form a second barrier layer.
When selecting the barrier layer material of the first conductive layer, it is generally required that the barrier layer material has a good barrier effect on diffusion of the first conductive layer, and the barrier layer material can be well attached to the surface of the first conductive layer.
Because the diffusion barrier effect of tantalum nitride on copper is stronger than that of tantalum on copper, compared with the method of forming only the first barrier layer without forming the second barrier layer, the tantalum nitride second barrier layer is formed on the first substrate, and then the tantalum covering the second barrier layer is formed on the first substrate as the first barrier layer based on the shape of the second barrier layer, so that the diffusion barrier effect on the first conductive layer can be improved.
Meanwhile, a first type of covalent bond can be formed between the tantalum and the copper, and the adhesion force of the tantalum to the copper can be increased through the formed first type of covalent bond; and a second covalent bond can be formed between the tantalum and the tantalum nitride, and the formed second covalent bond can enhance the adhesion of the tantalum to the tantalum nitride, namely, the tantalum can be well adhered to the surface of the copper film and the surface of the tantalum nitride layer.
Because the adhesion of tantalum to copper is greater than the adhesion of tantalum nitride to copper, compared with the case of forming only the second barrier layer without forming the first barrier layer, the embodiment of the disclosure can enhance the adhesion between the second barrier layer and the first conductive layer through the first barrier layer by arranging the first barrier layer between the second barrier layer and the first conductive layer, which is beneficial to improving the quality of the memory.
Because the diffusion rate of the first conductive layer to the second barrier layer is less than the diffusion rate of the first conductive layer to the first barrier layer, the second barrier layer is formed on the first substrate, and then the first barrier layer with the first crystal phase structure covering the second barrier layer is formed on the first substrate based on the appearance of the second barrier layer, so that the diffusion blocking effect on the first conductive layer is favorably improved, and the reliability and the yield of the memory are improved.
In some embodiments, the method further comprises:
forming an insulating layer over the first substrate having the second conductive layer;
forming a channel in the insulating layer; wherein at least a partial region of the second conductive layer is exposed through the channel;
the forming a second barrier layer on the first substrate includes:
forming a second barrier layer covering the side wall and the bottom of the channel on the first substrate based on the appearance of the channel; and the second barrier layer is positioned between the insulating layer and the first barrier layer and between the second conductive layer and the first barrier layer.
Illustratively, the insulating layer can be formed on the first substrate having the second conductive layer by chemical vapor deposition. The constituent materials of the insulating layer may include: a silicide. Taking the insulating layer as an example, the insulating layer is made of silicon oxide, tetraethyl orthosilicate (TEOS) and ozone (O) can be used by chemical vapor deposition3) The reaction takes place to form silicon oxide.
Illustratively, the channel may be formed in the insulating layer by wet etching using a liquid etchant or a gas etchant to react with the insulating layer and to drain out the reaction product. For example, when the insulating layer is a silicon oxide layer, the silicon oxide layer may be etched with a hydrofluoric acid (HF) solution to form the channel.
In some embodiments, the method further comprises:
attaching the second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed; wherein the second substrate is connected to the first conductive layer.
Specifically, the first conductive layer on the surface of the first substrate and the bonding region on the surface of the second substrate may be aligned, and under the action of an external condition (for example, within a temperature range of 200 to 500 degrees celsius), the first conductive layer having the second crystal phase structure diffuses toward the second substrate, and a covalent bond is formed between the first conductive layer and the second substrate, so that the first conductive layer and the second substrate are electrically connected, and the first substrate and the second substrate are bonded together.
In some embodiments, the method further comprises:
forming a third conductive layer with a second crystal phase structure on the surface of the second substrate;
the attaching of the second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed includes:
and attaching the third conductive layer to the first conductive layer.
Illustratively, the composition material of the third conductive layer may be the same as that of the first conductive layer.
When the second substrate is attached to the first substrate, the third conductive layer is aligned with the first conductive layer, the third conductive layer diffuses towards the first conductive layer, and the first conductive layer also diffuses towards the third conductive layer, so that a covalent bond is formed between the third conductive layer and the first conductive layer and is fused into a whole.
In the embodiment of the disclosure, the third conductive layer with the second crystal phase structure is formed on the surface of the second substrate, which is beneficial to increasing the strength of the covalent bond at the joint interface of the first substrate and the second substrate, improving the reliability of the joint of the first substrate and the second substrate, and ensuring the performance of the formed chip.
FIG. 3 is a partial schematic diagram illustrating one type of memory 100 in accordance with an exemplary embodiment. Referring to fig. 3, the memory 100 includes:
a first substrate 110;
a first conductive layer 111; wherein the first conductive layer 111 has a second crystal phase structure;
a first barrier layer 112 having a first crystal phase structure between the first substrate 110 and the first conductive layer 111; the lattice matching degree between the first barrier layer 112 having the first crystal phase structure and the first conductive layer 111 having the second crystal phase structure satisfies a predetermined condition.
The memory 100 may include: three-dimensional (3D) memory. For example, a three-dimensional NAND Flash (3D NAND Flash).
The first substrate 110 may include: a wafer with field effect transistors (MOS) or other control circuitry is formed. The first substrate 110 may further include: and forming a wafer of the storage area.
The composition material of the first conductive layer 111 may include: copper, tungsten, or aluminum, etc.
In practical applications, the barrier material of the first barrier layer is usually selected according to the composition material of the first conductive layer, so that the first barrier layer has a good barrier effect on diffusion of the first conductive layer, and the first barrier layer can be well attached to the surface of the first conductive layer.
Specifically, when the composition material of the first conductive layer is copper, tantalum nitride, or the like can be selected as the barrier layer for copper. In the embodiment of the present disclosure, the composition material of the first barrier layer may be tantalum.
During the growth of the copper film, the growth of copper particles in the copper lattice has three orientations of (001), (101), and (111). Compared with copper particles grown along the (001) or (101) orientation, the copper particles grown along the (111) orientation have the highest diffusion coefficient, so that the copper particles grown along the (111) orientation are easier to diffuse at a bonding interface during bonding, the contact area of the bonding interface is increased, and defects generated at the bonding interface are reduced.
It is understood that the preset conditions may include: the lattice matching degree of the first conductive layer with the second crystal phase structure and the first barrier layer with the first crystal phase structure is larger than a preset threshold value. Specifically, the preset threshold may be a lattice matching degree of the first conductive layer having the second crystal phase structure and the first blocking layer having a crystal phase structure other than the first crystal phase structure.
Illustratively, the first barrier layer further has a third crystalline phase structure;
the first conductive layer of the second crystal phase structure and the first barrier layer of the first crystal phase structure have a first lattice matching degree, the first conductive layer of the second crystal phase structure and the first barrier layer of the third crystal phase structure have a second lattice matching degree, and the first lattice matching degree is larger than the second lattice matching degree. Here, the preset threshold is the second lattice matching degree.
Specifically, the first conductive layer of the second crystal phase structure may be a copper film grown in the (111) direction. When the constituent material of the first barrier layer is tantalum, the crystalline phase structure of tantalum may include an α phase and a β phase. The first barrier layer of the first crystal phase structure may be beta-phase tantalum, the first barrier layer of the third crystal phase structure may be alpha-phase tantalum, the lattice matching degree of the beta-phase tantalum with the copper film grown in the (111) direction is a first lattice matching degree, and the lattice matching degree of the alpha-phase tantalum with the copper film grown in the (111) direction is a second lattice matching degree. Because the first lattice match is higher than the second lattice match, beta-phase tantalum is more favorable for promoting the epitaxial growth of copper particles in the copper film in the (111) orientation than alpha-phase tantalum.
It can be understood that, in order to increase the contact area of the bonding interface, reduce defects generated at the bonding interface, improve the reliability of the bonding interface, and improve the chip performance, the beta-phase tantalum can be selected as the first barrier layer having the first crystal phase structure.
According to the embodiment of the disclosure, the first barrier layer with the first crystal phase structure is formed on the first substrate, and then the first conductive layer covering the first barrier layer is formed, so that the first barrier layer with the first crystal phase structure can promote the formation of the first conductive layer with the second crystal phase structure, the diffusion of the first conductive layer in the bonding process is facilitated, the contact area of the bonding interface is increased, the defects generated in the bonding process are reduced, the quality of the bonding interface is improved, and the yield of the formed memory is ensured.
In some embodiments, as shown with reference to FIG. 4, memory 100 further comprises:
a second barrier layer 113 located between the first substrate 110 and the first barrier layer 112; the diffusion rate of the first conductive layer 111 to the second barrier layer 113 is smaller than the diffusion rate of the first conductive layer 111 to the first barrier layer 112.
When the first barrier layer is tantalum, the composition material of the second barrier layer may include tantalum nitride.
Because the diffusion barrier effect of tantalum nitride to copper is stronger than the diffusion barrier effect of tantalum to copper, but the adhesion effect of tantalum to copper is stronger than the adhesion effect of tantalum nitride to copper, therefore, a second barrier layer of tantalum nitride can be formed on the first substrate, and then the tantalum covering the second barrier layer is formed on the first substrate as the first barrier layer based on the appearance of the second barrier layer, so that the adhesion effect between the second barrier layer and the first conductive layer is enhanced through the first barrier layer while the diffusion barrier effect to the first conductive layer is ensured, and the quality of the memory is favorably improved.
In some embodiments, as shown with reference to FIG. 5, memory 100 further comprises:
a second conductive layer 114 on the first substrate 110;
an insulating layer 115 covering the second conductive layer 114; the second barrier layer 113 covers the trench sidewalls and the trench bottom in the insulating layer 115, is between the insulating layer 115 and the first barrier layer 112, and is between the second conductive layer 114 and the first barrier layer 112.
The composition material of the second conductive layer 114 may include: metals, conductive media, etc. Such as tungsten, copper, aluminum, polysilicon, etc.
The constituent materials of the insulating layer may include: a silicide. Such as silicon oxide, etc.
In some embodiments, as shown with reference to FIG. 6, the memory 100 further comprises:
a second substrate 120 attached to the first substrate 110 on which the first barrier layer 112 and the first conductive layer 111 are formed; wherein the second substrate 120 is connected to the first conductive layer 111.
The second substrate 120 may include: a wafer with field effect transistors or other control circuitry is formed. The first substrate 120 may further include: and forming a wafer of the storage area.
Referring to fig. 6, the second substrate 120 further includes:
the third conductive layer 121 has a second crystal phase structure and is connected to the first conductive layer 111.
The composition material of the third conductive layer 121 may include: metals, conductive media, etc. Such as tungsten, copper, aluminum, polysilicon, etc.
By taking the first substrate as a wafer with a storage region and the second substrate as a wafer with a control circuit as an example, the first substrate and the second substrate are attached to form an electrical connection between the storage region on the first substrate and the control circuit on the second substrate, so that the storage region on the first substrate can be controlled by the control circuit on the second substrate, and the area of a memory chip is reduced while the memory function is realized.
Several specific examples are provided below in connection with any of the embodiments described above:
example 1:
wafer level copper-copper bonding (Wafer level Cu-Cu bonding) is used as a key technology in the preparation process of the three-dimensional memory, and can form electric connection between different wafers by bonding copper films on the bonding surfaces of the different wafers, so that the bonding of the different wafers is realized.
The present example provides a method for manufacturing a memory 100, which is shown in fig. 5 and 6, and includes:
forming an insulating layer 115 on the surface of the first substrate 110 having the second conductive layer 114;
forming a channel in the insulating layer 115; wherein a partial region of the second conductive layer 114 is exposed through the channel;
forming a second barrier layer 113 covering the trench sidewalls and the trench bottom based on the topography of the trench;
forming a first barrier layer 112 covering the second barrier layer 113 in the channel formed with the second barrier layer 113 based on the morphology of the second barrier layer 113; wherein the crystalline phase structure of the first barrier layer 112 comprises a first crystalline phase structure;
forming a first conductive layer 111 in the channel where the first barrier layer 112 is formed based on the morphology of the first barrier layer 112; the first conductive layer 111 has a second crystal phase structure, and the lattice matching degree between the first conductive layer 111 having the second crystal phase structure and the first barrier layer 112 having the first crystal phase structure satisfies a predetermined condition;
attaching a second substrate 120 having a third conductive layer 121 to the first substrate 110 on which the first barrier layer 112 and the first conductive layer 111 are formed; the third conductive layer 121 is electrically connected to the first conductive layer 111.
Illustratively, the constituent material of the first conductive layer 111 is copper.
It is to be understood that although the first barrier layer 112 and the second barrier layer 113 are disposed between the second conductive layer 114 and the first conductive layer 111, the resistivity of the first barrier layer 112 and the second barrier layer 113 is low, so that the second conductive layer 114 and the first conductive layer 111 can be electrically connected.
In a conventional wafer bonding process, due to the low quality of a copper film used for bonding, in the bonding process of different substrates, lattice defects such as voids (void) and lattice dislocation often occur between bonding surfaces of two substrates. The generated lattice defects can increase the contact resistance of the bonding interface and reduce the yield of the formed memory.
Taking a high-temperature bonding manner as an example, at a bonding interface, copper films on surfaces of different substrates for bonding diffuse, and covalent bonds are formed between copper particles from different substrates, so that bonding is realized. Therefore, the diffusion phenomenon of the copper film with high diffusion coefficient in the bonding process is more obvious, the bonding contact area of different substrates is increased, the bonding quality and reliability are improved, and the performance of the formed memory chip is further improved.
The growth of copper particles in the lattice of copper generally has three orientations, namely (001), (101), and (111). Research shows that the diffusion coefficient of the copper particles grown along the (111) orientation is the highest compared with the copper particles grown along the (001) or (101) orientation, so that the copper particles grown along the (111) orientation are easier to diffuse at the bonding interface during bonding, the contact area of the bonding interface is increased, and defects generated at the bonding interface are reduced.
Before the copper film is formed, a barrier layer is usually formed between the copper film and the insulating layer to prevent copper from diffusing into the insulating layer, thereby avoiding memory failure. Commonly used barrier layers for copper films may include: tantalum nitride and tantalum.
Tantalum nitride provides a better barrier to copper than tantalum. However, the resistivity of tantalum nitride is higher than that of tantalum, and the adhesion between tantalum nitride and copper is smaller than that between tantalum and copper, so that tantalum nitride can be used as the second barrier layer, and tantalum can be formed between tantalum nitride and copper as the first barrier layer to improve the adhesion characteristics between tantalum nitride and copper.
Fig. 7a to 7c are schematic process flow diagrams of a Punch Through (Punch Through) interconnect structure. As shown in fig. 7a, an insulating layer 115 is formed on the first substrate 110 having the second conductive layer 114, and then a trench 116 is formed in the insulating layer 115, at least a partial region of the second conductive layer 114 being exposed through the trench 116.
Then, a tantalum nitride layer is formed as the second barrier layer 113 based on the profile of the trench 116, and the tantalum nitride covering the bottom of the trench 116 is bombarded with argon particles (Ar Plasma) to remove the tantalum nitride at the bottom of the trench 116 until the second conductive layer 114 is exposed through the bottom of the trench 116. At this time, as shown in fig. 7b, the second barrier layer 113 covers sidewalls of the trench 116.
Subsequently, as shown in fig. 7c, a layer of tantalum is deposited as the first barrier layer 112, and a copper film is formed in the trench as the first conductive layer 111 based on the profile of the first barrier layer 112. At this time, the first blocking layer covers the bottom of the trench 116 and is located between the first conductive layer 111 and the second conductive layer 114.
Figure 8a shows an X-ray diffraction pattern of tantalum formed on tantalum nitride as a function of time as the argon particles bombard the tantalum nitride. Referring to fig. 8a, as the time for argon particles to bombard the tantalum nitride layer increases from 0 seconds(s) to 16s, the characteristic peak intensity of alpha-phase tantalum increases and the characteristic peak intensity of beta-phase tantalum decreases in the tantalum formed. It is understood that when the characteristic peak intensity of alpha phase tantalum increases and the characteristic peak intensity of beta phase tantalum decreases, it indicates that the content of alpha phase tantalum in the formed tantalum increases and the content of beta phase tantalum decreases. Wherein, when the time for the argon particles to bombard the tantalum nitride layer is 0s, the argon particles are not used for bombarding the tantalum nitride layer.
When the argon particle bombardment time for the tantalum nitride is 0s, i.e., when the argon particle bombardment treatment is not used for the tantalum nitride, the crystal lattice structure of the tantalum nitride is not a body-centered cubic structure. At this time, in the tantalum layer deposited on the surface of the tantalum nitride which is not subjected to the argon particle bombardment treatment, the content of the beta-phase tantalum is high, and the content of the beta-phase tantalum is higher than that of the alpha-phase tantalum.
When argon particles are used for bombarding tantalum nitride, nitrogen particles and tantalum particles bombarded from lattice point positions are recombined to form body-centered cubic structure tantalum nitride, and the body-centered cubic structure tantalum nitride is redeposited and covers the surface of the tantalum nitride layer which is not bombarded.
Because the lattice structure of the body-centered cubic tantalum nitride is the same as that of the alpha-phase tantalum, when the surface of the tantalum nitride subjected to the argon particle bombardment treatment is continuously deposited with tantalum, the content of the generated alpha-phase tantalum is increased, so that the content of the beta-phase tantalum in the deposited tantalum is reduced.
Therefore, as the time for the argon particles to bombard the tantalum nitride layer increases from 0 seconds(s) to 16s, the characteristic peak intensity of the alpha-phase tantalum in the tantalum formed increases, and the characteristic peak intensity of the beta-phase tantalum decreases.
Figure 8b shows the resistivity of a first substrate formed with tantalum nitride and tantalum as a function of argon particle bombardment time for tantalum nitride. Referring to fig. 8b, as the argon particles bombard the tantalum nitride for increasing time from 0s to 16s, the resistivity of the first substrate formed with the tantalum nitride layer and the tantalum layer gradually decreases.
It can be understood that, since the resistivity of the α -phase tantalum is lower than that of the β -phase tantalum, when the α -phase tantalum content in the tantalum is increased and the β -phase tantalum content is decreased, the overall resistivity of the tantalum layer formed is decreased, so that the resistivity of the first substrate having the tantalum nitride layer and the tantalum layer is decreased.
FIG. 9a shows an X-ray diffraction pattern of a first substrate formed with a tantalum layer and a copper film as a function of time of argon particle bombardment of tantalum nitride. Referring to fig. 9a, as the time for the argon particles to bombard the tantalum nitride layer increases from 0 seconds(s) to 12s, (111) the characteristic peak intensity of oriented copper decreases, the characteristic peak intensity of alpha-phase tantalum increases, and the characteristic peak intensity of beta-phase tantalum decreases.
Since the lattice matching degree of the beta-phase tantalum with the copper having a face-centered cubic structure and growing in the (111) direction is higher than that of the alpha-phase tantalum with the copper having a face-centered cubic structure and growing in the (111) direction, the beta-phase tantalum is more favorable for promoting the epitaxial growth of copper particles in the copper film in the (111) orientation than the alpha-phase tantalum.
When the argon particle bombardment time for the tantalum nitride is 0s, i.e., when the argon particle bombardment treatment is not used for the tantalum nitride, the crystal lattice structure of the tantalum nitride is not a body-centered cubic structure. At this time, in the tantalum layer deposited on the surface of the tantalum nitride which is not subjected to the argon particle bombardment treatment, the content of the beta-phase tantalum is higher than that of the alpha-phase tantalum. When copper is deposited on the surface of beta-phase tantalum, the content of copper particles growing in the (111) orientation in the copper film increases.
As the time for the argon particles to bombard the tantalum nitride is gradually increased, the content of alpha-phase tantalum in the formed tantalum is increased, and the content of beta-phase tantalum is reduced, which is not beneficial to promoting the epitaxial growth of the copper particles in the formed copper film according to the (111) orientation. That is, as the time for the argon particles to bombard the tantalum nitride is gradually increased, the content of copper particles growing in the (111) orientation in the copper film is reduced, so that the characteristic peak intensity of the (111) orientation copper is weakened.
FIG. 9b shows the resistivity of the first substrate formed with the tantalum layer and the copper film as a function of the argon particle bombardment time for tantalum nitride. Referring to fig. 9b, as the ar particles bombard the tantalum nitride for increasing time from 0s to 12s, the resistivity of the first substrate formed with the tantalum layer and the copper film gradually decreases.
It is understood that, since the resistivity of copper is smaller than that of tantalum, for the first substrate formed with the tantalum layer and the copper film, the resistivity of the first substrate is mainly determined by the resistivity of the tantalum layer. Since the resistivity of the alpha phase tantalum is lower than that of the beta phase tantalum, when the content of the alpha phase tantalum in the tantalum is increased and the content of the beta phase tantalum is decreased, the overall resistivity of the formed tantalum is decreased, so that the resistivity of the first substrate having the tantalum layer and the copper film is decreased.
Fig. 9c is a distribution of copper particles grown in different orientations in the first substrate on which the copper film is formed at different argon particle bombardment times, obtained by Electron Back Scattering Diffraction (EBSD). FIG. 9d shows texture fractions of (111) oriented copper particles in the resulting copper film at different argon particle bombardment times.
As can be seen from fig. 9c and 9d, compared to the method of depositing a tantalum layer after bombarding the tantalum nitride layer with argon particles and then depositing a copper film, the method of the present disclosure, which does not bombard the tantalum nitride layer with argon particles, directly depositing the tantalum layer on the tantalum nitride layer as a first barrier layer and then depositing the copper film on the tantalum layer as a first conductive layer, can increase the content of (111) oriented copper particles in the copper film, thereby increasing the reliability of copper bonding between different substrates and improving the chip performance.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (21)

1. A method for manufacturing a memory, comprising:
forming a first barrier layer having a first crystal phase structure on a first substrate, the first crystal phase structure representing a unit cell structure type;
forming a first conductive layer overlying the first barrier layer; the first conducting layer is provided with a second crystal phase structure, the second crystal phase structure represents the crystal growth direction, and the lattice matching degree of the first conducting layer and the first barrier layer meets a preset condition.
2. The method of claim 1, further comprising:
forming a second barrier layer on the first substrate; the diffusion rate of the first conductive layer diffusing to the second barrier layer is smaller than that of the first conductive layer diffusing to the first barrier layer;
the forming a first barrier layer having a first crystalline phase structure on a first substrate includes:
and forming the first barrier layer with the first crystalline phase structure on the first substrate to cover the second barrier layer based on the morphology of the second barrier layer.
3. The method of claim 2, further comprising:
forming an insulating layer over the first substrate having the second conductive layer;
forming a channel in the insulating layer; wherein at least a partial region of the second conductive layer is exposed through the channel;
the forming a second barrier layer on the first substrate includes:
forming the second barrier layer covering the side wall and the bottom of the channel on the first substrate based on the topography of the channel; the second barrier layer is located between the insulating layer and the first barrier layer, and located between the second conductive layer and the first barrier layer.
4. The method of claim 1, further comprising:
attaching a second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed; wherein the second substrate is connected to the first conductive layer.
5. The method of claim 4, further comprising:
forming a third conductive layer with the second crystal phase structure on the surface of the second substrate;
the attaching the second substrate to the first substrate on which the first barrier layer and the first conductive layer are formed includes:
and attaching the third conductive layer to the first conductive layer.
6. The method of claim 1, wherein the first barrier layer comprises: a first portion having the first crystal phase structure and a second portion having a third crystal phase structure; wherein the resistivity of the second portion is less than the resistivity of the first portion;
the lattice matching degree of the first conductive layer and the first barrier layer meets a preset condition, and the lattice matching degree of the first conductive layer and the first barrier layer comprises the following steps:
the first conductive layer and the first portion have a first lattice matching degree, the first conductive layer and the second portion have a second lattice matching degree, and the first lattice matching degree is larger than the second lattice matching degree.
7. The method according to claim 6, wherein the first crystalline phase structure is a beta crystalline phase; the third crystal phase structure is alpha crystal phase.
8. The method of claim 1, wherein the crystal growth direction is a (111) orientation.
9. A memory, comprising:
a first substrate;
a first conductive layer; wherein the first conductive layer has a second crystal phase structure representing a crystal growth direction;
a first barrier layer having a first crystalline phase structure between the first substrate and the first conductive layer; wherein the first crystalline phase structure represents a unit cell structure type; the lattice matching degree of the first barrier layer and the first conductive layer meets a preset condition.
10. The memory of claim 9, further comprising:
a second barrier layer between the first substrate and the first barrier layer; and the diffusion rate of the first conductive layer diffusing to the second barrier layer is smaller than that of the first conductive layer diffusing to the first barrier layer.
11. The memory of claim 10, further comprising:
a second conductive layer on the first substrate;
an insulating layer covering the second conductive layer; the second barrier layer covers the side wall and the bottom of the channel in the insulating layer, is positioned between the insulating layer and the first barrier layer, and is positioned between the second conducting layer and the first barrier layer.
12. The memory of claim 9, further comprising:
a second substrate attached to the first substrate on which the first barrier layer and the first conductive layer are formed; wherein the second substrate is connected to the first conductive layer.
13. The memory of claim 12, wherein the second substrate further comprises:
and the third conducting layer is provided with the second crystal phase structure and is connected with the first conducting layer.
14. The memory of claim 9,
the first barrier layer includes: a first portion having the first crystal phase structure and a second portion having a third crystal phase structure; wherein the resistivity of the second portion is less than the resistivity of the first portion;
the lattice matching degree of the first conductive layer and the first barrier layer meets a preset condition, and the lattice matching degree of the first conductive layer and the first barrier layer comprises the following steps:
the first conductive layer and the first portion have a first lattice matching degree, the first conductive layer and the second portion have a second lattice matching degree, and the first lattice matching degree is larger than the second lattice matching degree.
15. The memory of claim 9, wherein the material of the first barrier layer comprises: tantalum;
the material of the first conductive layer includes: copper;
the crystal growth direction is (111) orientation.
16. A semiconductor device, comprising: a first semiconductor structure and a second semiconductor structure;
the first semiconductor structure and the second semiconductor structure include:
a first barrier layer having a first crystalline phase structure, the first crystalline phase structure representing a unit cell structure type;
a first conductive layer overlying the first barrier layer; wherein the first conductive layer has a second crystal phase structure representing a crystal growth direction;
the lattice matching degree of the first barrier layer and the first conductive layer meets a preset condition.
17. The semiconductor device of claim 16, further comprising between the first semiconductor structure and the second semiconductor structure:
a second barrier layer; wherein the first barrier layer is positioned between the second barrier layer and the first conductive layer; the diffusion rate of the first conductive layer to the second barrier layer is smaller than that of the first conductive layer to the first barrier layer.
18. The semiconductor device of claim 17, further comprising between the first semiconductor structure and the second semiconductor structure:
a second conductive layer; wherein the second barrier layer is located between the second conductive layer and the first barrier layer.
19. The semiconductor device of claim 16, wherein the first barrier layer comprises: a first portion having the first crystal phase structure and a second portion having a third crystal phase structure; wherein the resistivity of the second portion is less than the resistivity of the first portion;
the lattice matching degree of the first conductive layer and the first barrier layer meets a preset condition, and the lattice matching degree of the first conductive layer and the first barrier layer comprises the following steps:
the first conductive layer and the first portion have a first lattice matching degree, the first conductive layer and the second portion have a second lattice matching degree, and the first lattice matching degree is larger than the second lattice matching degree.
20. The semiconductor device according to claim 16, wherein the crystal growth direction is a (111) orientation.
21. The semiconductor device according to claim 16,
the first semiconductor structure includes: a memory cell array and/or a control circuit;
and/or the presence of a gas in the gas,
the second semiconductor structure includes: memory cell arrays and/or control circuits.
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