CN114266211A - Method and system for generating connectivity test file and readable storage medium - Google Patents

Method and system for generating connectivity test file and readable storage medium Download PDF

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Publication number
CN114266211A
CN114266211A CN202111553750.8A CN202111553750A CN114266211A CN 114266211 A CN114266211 A CN 114266211A CN 202111553750 A CN202111553750 A CN 202111553750A CN 114266211 A CN114266211 A CN 114266211A
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file
module
input
interface
connectivity test
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乐亚平
田利波
邵海波
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Abstract

The invention discloses a method, a system and a readable storage medium for generating a connectivity test file, wherein the method comprises the following steps: establishing a hierarchical structure configuration file, a special interface description file and a special signal relation description file; acquiring a configuration file of a chip to be verified, and analyzing input and output interface information of each module to be tested and an associated module in the configuration file based on the hierarchical configuration file to respectively generate an input interface file and an output interface file of the module to be tested and an input interface file and an output interface file of the associated module; acquiring an input interface file of a module to be tested, and searching output signals matched with input signals in the input interface file in the output interface file of the associated module in sequence; forming a connection relation group by the matched output signals and the input signals, and outputting the connection relation group to a connectivity test file; and updating the connection relation group of the connectivity test file based on the special signal relation specification file to obtain a final connectivity test file. The invention shortens the time of chip verification.

Description

Method and system for generating connectivity test file and readable storage medium
Technical Field
The invention relates to the technical field of chip verification, in particular to a method and a system for generating a connectivity test file and a readable storage medium.
Background
With the rapid development of large-scale integrated circuit system design, the scale of an integrated circuit is larger and larger, the complexity of a chip is gradually complicated, and the existing project progress pressure is important for quickly finding and solving problems at the early stage of a project and executing and removing problems at the middle and later stages of the project.
At present, a large-scale chip design comprises a plurality of modules, a plurality of subsystems and a plurality of systems, wherein functional and connection coupling exists between each module and each system, and for the large-scale chip with the modules and the systems, the following problems mainly exist in the initial stage of design and verification: firstly, the designers of each module, subsystem and system are different, and the interface definition and the interface time sequence are not completely aligned; in higher-level integration, an integrator does not necessarily have good knowledge of the widths, attributes and connectivity of all interface signals; and finally, for the verification personnel, a large amount of manpower and time are consumed to solve the connection and related problems in the early stage of project verification, and even in the later stage of the project, the situation that the connectivity and functionality of some interfaces are not completely verified is found when the code coverage rate is collected.
In the face of increasingly updated verification technology, as a first firewall for chip function verification, verification personnel must ensure the correctness of connection inside modules, connection between modules, subsystem and system integration connection, so that a foundation can be laid for subsequent verification work. The following problems are currently encountered with connectivity test verification: at the initial stage of verification, for a complex SoC (System on a Chip) Chip, thousands of interface signals exist, and designers cannot provide correct input and output and connection of the interface signals and time sequence documents; the development of the connectivity test case needs to spend a lot of time, and the signals with multi-bit or time sequence requirements cannot be traversed; the connectivity test needs to be redefined at a higher level, and verification points are omitted when subsequent design updates and verification are not followed.
Disclosure of Invention
In view of the above, the invention provides a method, a system and a readable storage medium for generating a connectivity test file, which automatically generate the connectivity test file based on a hierarchical configuration file, a special interface description file and a special signal relationship description file, and solve the problem of connectivity errors caused by non-uniform interfaces due to non-standard design codes; the problems that the traditional test case is long in development time and the chip connectivity error positioning time is long are solved.
Based on the above object, an aspect of the embodiments of the present invention provides a method for generating a connectivity test file, which specifically includes the following steps:
establishing a hierarchical structure configuration file, a special interface description file and a special signal relation description file;
acquiring a configuration file of a chip to be verified, and analyzing input and output interface information of each module to be tested and an associated module in the configuration file based on the hierarchical structure configuration file to respectively generate an input interface file and an output interface file of the module to be tested and an input interface file and an output interface file of the associated module;
acquiring an input interface file of the module to be tested, and searching output signals matched with input signals in the input interface file in the output interface file of the associated module in sequence;
forming a connection relation group by the output signals in the output interface file and the input signals in the input interface file which are matched with each other, and outputting the connection relation group to a connectivity test file;
and updating the connection relation group of the connectivity test file based on the special signal relation description file to obtain a final connectivity test file.
In some embodiments, the method further comprises:
if the output signal matched with the input signal in the input interface file is not searched in the output interface file, searching the output signal which is in connection relation with the unmatched input signal in the output interface file based on the special interface description file and the unmatched input signal;
and outputting the unmatched input signals and the output signals with the connection relation to the connectivity test file, and returning to the step of updating the connectivity test file based on the special interface description file.
In some embodiments, the method further comprises:
and if the output signals which have connection relation with the unmatched input signals are not searched in the output interface file, outputting the unmatched input signals and the modules where the unmatched input signals are located to an error file.
In some embodiments, updating the set of connection relationships of the connectivity test file based on the special signal relationship specification file to obtain a final connectivity test file comprises:
and updating each connection relation group in the connectivity test file according to the connectivity test function of the special signal relation description file to obtain a final connectivity test file.
In some embodiments, updating each connection relationship group in the connectivity test file according to the connectivity test function of the special signal relationship specification file to obtain a final connectivity test file includes:
and acquiring the parameter length and the special character of the connection relation group, and calling a corresponding connectivity test function to update the connection relation group based on the parameter length and the special character.
In some embodiments, parsing the input and output interface information of each module to be tested and associated module in the configuration file based on the hierarchical configuration file to generate an input and output interface file of the module to be tested and an input and output interface file of the associated module, respectively, includes:
extracting path information of each module to be tested and the associated module of the chip to be verified from the configuration file based on the hierarchical structure configuration file;
extracting interface information of the module to be tested and interface information of the correlation module based on the path information;
and analyzing the interface information of the to-be-tested module and the interface information of the associated module to respectively generate input and output interface files of each to-be-tested module and input and output interface files of the associated module of the to-be-verified chip.
In some embodiments, the hierarchical configuration file comprises: the information of the module to be tested, the information of the associated module and the information of the output file;
the special interface specification file includes: the interface information of the unmatched module to be tested and the interface information of the associated module which has a connection relation with the interface information of the unmatched module to be tested.
In some embodiments, after outputting the set of connection relationships to the connectivity test file, the method further comprises:
acquiring an output interface file of the module to be tested, and searching the input interface file of the correlation module for correlation input signals matched with the output signals to be tested in the output interface file in sequence;
and forming a connection relation group by the matched associated input signals and the output signals to be tested, and outputting the connection relation group to the connectivity test file.
In another aspect of the embodiments of the present invention, a system for generating a connectivity test file is further provided, including:
a creation module configured to create a hierarchical configuration file, a special interface specification file, a special signal relationship specification file;
the analysis module is configured to acquire a configuration file of a chip to be verified, and analyze input and output interface information of each module to be tested and the associated module in the configuration file based on the hierarchical structure configuration file to respectively generate an input and output interface file of the module to be tested and an input and output interface file of the associated module;
the searching module is configured to acquire the input interface file of the module to be tested and sequentially search the output interface file of the correlation module for the output signal matched with the input signal in the input interface file;
the searching module is also configured to form a connection relation group by the output signals in the matched output interface file and the input signals in the input interface file, and output the connection relation group to a connectivity test file;
an update module configured to update the connection relationship group of the connectivity test file based on the special signal relationship specification file to obtain a final connectivity test file.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has at least the following beneficial technical effects: the connectivity test file is automatically generated based on the hierarchical structure configuration file, the special interface description file and the special signal relation description file, so that the time for developing a design case by chip verification is shortened, the time for chip verification is shortened, and the chip verification efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a block diagram of one embodiment of a method of generating a connectivity test file provided by the present invention;
FIG. 2 is a diagram illustrating an embodiment of a system for generating a connectivity test file according to the present invention;
fig. 3 is a schematic structural diagram of an embodiment of a computer-readable storage medium provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention proposes an embodiment of a method of generating a connectivity test file. As shown in fig. 1, it includes the following steps:
step S101, establishing a hierarchical structure configuration file, a special interface description file and a special signal relation description file;
step S103, acquiring a configuration file of a chip to be verified, and analyzing input and output interface information of each module to be tested and an associated module in the configuration file based on the hierarchical configuration file to respectively generate an input interface file and an output interface file of the module to be tested and an input interface file and an output interface file of the associated module;
step S105, acquiring an input interface file of the module to be tested, and searching output signals matched with input signals in the input interface file in the output interface file of the associated module in sequence;
step S107, forming a connection relation group by the output signals in the output interface file and the input signals in the input interface file which are matched with each other, and outputting the connection relation group to a connectivity test file;
step S109, updating the connection relationship group of the connectivity test file based on the special signal relationship description file to obtain a final connectivity test file.
The system comprises a hierarchical structure configuration file, a test module and a hierarchical structure of the test module are appointed in the file, and a module related to the test module and the hierarchical structure of the module in the system or the subsystem are appointed at the same time; the system comprises a special interface description file, a code naming rule definition file and a data processing file, wherein an interface which is not defined according to the code naming rule and an interface with special input and output requirements are specified in the file, and the file is analyzed to give a connection relation of an incomplete matching interface and generate a connectivity test file; and updating a corresponding interface signal relation group in the connectivity test file through the file to obtain a final connectivity test file.
And extracting path information of the module to be tested and the associated module from the configuration file of the chip to be verified, analyzing the interfaces of the modules, and generating input and output interface files of each module, so that the subsequent connectivity matching is facilitated.
Because the input signal of the module to be tested is the output signal of the associated module, and the output signal of the module to be tested is the input signal of the associated module, in order to verify the connectivity of the input and output signals of the module to be tested, an input interface connectivity test file and an output interface connectivity test file of the module to be tested need to be generated respectively, and the generation methods of the connectivity test files of the two interfaces are the same. The present embodiment describes the generation of a connectivity test file for an input interface of a module to be tested.
And importing the input files of the modules to be tested, and searching output signals in the output files of the associated modules in sequence. If the signal name of the output signal is completely matched with the signal name of the input signal, outputting the connection relation to a connectivity test file or a copy file; and if matched output signals are not searched in all output interface files of all the associated modules, analyzing the input signals of the modules to be tested, which do not find the matched output signals, according to the special interface description file, namely searching whether the output signals having the connection relation with the input signals exist in the special interface description file.
According to the special signal relation description file, the connection relation group in the current connectivity test file is correspondingly replaced, that is, the signals described in the file are replaced by tasks or functions with special requirements, for example, a signal sig _ a of a module a (a module to be tested) and a signal sig _ B of a module B (a module to be tested) are directly connected and are inverted, so that the following replacement is performed through the special signal relation description file: cc _ check (hier _ a. sig _ a, hier _ b. sig _ b) is replaced with cc _ check (hier _ a. sig _ a, hier _ b. sig _ b, reverse).
In the embodiment, in the process of generating the connectivity test file, basic signal mismatching and connection problems can be directly checked; the method can automatically extract the design file through the design document under the condition that the design document is complete, and can automatically match the signal with the connection relation under the condition that the design document is incomplete and output the signal to the connectivity test file.
Through the embodiment, the connectivity test file can be automatically generated based on the hierarchical structure configuration file, the special interface description file and the special signal relation description file, the time for developing a testability case in the traditional chip verification process is reduced, the positioning time for the signal to generate connection errors is reduced, the risk of verification leaks caused by interface change in the chip middle and later stage design updating process is reduced, the chip verification time is shortened, and the reliability of chip verification is improved.
In some embodiments, the method further comprises:
if the output signal matched with the input signal in the input interface file is not searched in the output interface file, searching the output signal which is in connection relation with the unmatched input signal in the output interface file based on the special interface description file and the unmatched input signal;
and outputting the unmatched input signals and the output signals with the connection relation to the connectivity test file, and returning to the step of updating the connectivity test file based on the special interface description file.
Specifically, an input file of a module to be tested is imported, and output signals are searched in output files of associated modules in sequence. And if matched output signals are not searched in all output interface files of all the associated modules, analyzing the input signals of the modules to be tested, which do not find the matched output signals, according to the special interface description file, namely searching whether the output signals having the connection relation with the input signals exist in the special interface description file.
If the output signal which has connection relation with the input signal exists in the special interface specification file, the input signal and the output signal which has connection relation with the input signal form a connection relation group to be output to the connectivity test file.
In some embodiments, the method further comprises:
and if the output signals which have connection relation with the unmatched input signals are not searched in the output interface file, outputting the unmatched input signals and the modules where the unmatched input signals are located to an error file.
Specifically, the special interface specification file is searched for whether an output signal having a connection relation with the input signal exists. If the special interface description file does not have an output signal which has a connection relation with the input signal, the signal is output to an error file, and subsequent verification and design self-checking are facilitated.
The definition and format of the error file is as follows:
the error file is used for storing the unconnected signals of the module to be tested, the signal width is not matched and the like.
For example, a module contains 100 input signals, then there are theoretically 100 output signals associated with these 100 input signals. After the configuration file of the module A is analyzed through the hierarchical configuration file to obtain the input and output interface files of the module A and the input and output interface files of each associated module of the module A, 90 output signals matched with the input signals of the module A are found in all the output interface files of the associated modules, then 90 matched input and output signals form a connection relation group to be output to the connectivity test file, and then 10 input signals of the module A do not find matched output signals. Searching whether output signals having connection relations with the 10 input signals exist in the special interface description file, if 8 input signals find the output signals having the connection relations and 2 input signals do not find corresponding output signals, outputting a connection relation group consisting of the 8 input signals and the connected output signals to a connectivity test file, and outputting the 2 input signals to an error file. At this time, the connectivity test file includes 98 input signals, and the corresponding input signals in the connectivity test file are updated by using the special signal relation description file to obtain a final connectivity test file.
In some embodiments, updating the set of connection relationships of the connectivity test file based on the special signal relationship specification file to obtain a final connectivity test file comprises:
and updating each connection relation group in the connectivity test file according to the connectivity test function of the special signal relation description file to obtain a final connectivity test file.
In some embodiments, updating each connection relationship group in the connectivity test file according to the connectivity test function of the special signal relationship specification file to obtain a final connectivity test file includes:
and acquiring the parameter length and the special character of the connection relation group, and calling a corresponding connectivity test function to update the connection relation group based on the parameter length and the special character.
According to various embodiments of the present invention, the special signal relationship specification file contains a plurality of connectivity test functions, and the connectivity test functions are packaged.
The following is a predefined partial basic connectivity test function, which indicates that input and output signals are directly connected, that indicates that the input and output signals are inverted, that indicates that clock signal synchronization is required between the input and output signals, that indicates that clock signal synchronization + inversion is required between the input and output signals, that indicates that there is a delay between the input and output signals, and that indicates that delay + inversion is required between the input and output signals, etc. The interface signals of the connection functions are all single bits, each function checks 0 and 1 values, the functions can be expanded and can be expanded to the detection of partial combinational logic, for example, two signals are output to a certain module after being subjected to AND or not.
cc_direct(src,dst);
cc_reversal_chk(src,dst,cmd);
cc_with_clock(src,dst,clock,cnt);
cc_reversal_with_clok(src,dst,clock,cnt,cmd);
cc_with_delay(src,dst,scale,cnt);
cc_reversal_with_delay(src,dst,scale,cnt,cmd)。
And packaging the well-defined connectivity test function, wherein the packaging format is as follows:
the special signal relation description file calls the corresponding connectivity test function by judging the number of the parameters and the special characters, specifically, obtains the parameter length and the special characters of the connection relation group in the connectivity test file, and calls the corresponding connectivity test function to update the connection relation group based on the parameter length and the special characters to obtain the final connectivity test file.
The connectivity test file can be implemented in tcl language, the basic function and the encapsulation function mentioned in the above embodiment can be stored in agent _ tcl.do, the connectivity test file is stored in user _ tcl.do, and the do file for specifying the test case to run in the test case is executed by another piece of automation software. In the test case execution stage, the connection errors between the signals and the basic logic errors can be checked, and when a logic or timing relation exists among a plurality of signals, the connection errors and the basic logic errors can be checked through sva.
The definition and format of the connectivity test file is as follows:
still further, the method further includes generating a signal connection text (csv) file based on the final connectivity test file, as shown in table 1. In table 1, the first behavior tags are the module name of the module where the source signal is located, the signal name of the source signal, the module name of the module where the target signal is located, the signal name of the target signal, and the connection relationship, and each column is the content corresponding to the tag.
TABLE 1
In the embodiment of the invention, in the script execution stage, by analyzing and filtering a plurality of input files, the mismatch and connection problems of partial signals can be checked based on the generated error file, in the test case execution stage, the detection of the connectivity test is realized based on the generated connectivity test file and the error file, the connectivity test file can be updated according to the change of the extracted file, recompilation is not needed, post-processing can be carried out after the execution is finished, and the connectivity test file is output to the csv file.
The embodiment of the invention can extract the interfaces of the script files of each module, subsystem and system of the chip to be verified, and can automatically generate the connectivity test file aiming at the verification of different levels of the chip. Under the condition that the verification environment is not completed, a connectivity test file and an error file can be automatically generated by extracting a configuration file, a connection error interface is automatically output based on the error file, and the connectivity problem at the initial stage of design is found; under the condition that the verification environment is finished, the logic connection problem is found through the automatically generated connectivity test file and the error file, and the consumption of a large amount of time and manpower is reduced; under the condition that the design documents at the middle and later stages are complete, the connection files are directly extracted according to the design documents, so that the consistency of design and verification is ensured; the connectivity test file can be used as a test case for chip verification, and when the test case is operated, the connectivity test file can be automatically updated according to the latest design file of the chip, so that the problem of asynchronism between design and verification is avoided, and the risk of verification leaks caused by interface change in the design updating process of the middle and later stages of the chip is reduced.
In some embodiments, parsing the input and output interface information of each module to be tested and associated module in the configuration file based on the hierarchical configuration file to generate an input and output interface file of the module to be tested and an input and output interface file of the associated module, respectively, includes:
extracting path information of each module to be tested and the associated module of the chip to be verified from the configuration file based on the hierarchical structure configuration file;
extracting interface information of the module to be tested and interface information of the correlation module based on the path information;
and analyzing the interface information of the to-be-tested module and the interface information of the associated module to respectively generate input and output interface files of each to-be-tested module and input and output interface files of the associated module of the to-be-verified chip.
In some embodiments, the hierarchical configuration file comprises: the information of the module to be tested, the information of the associated module and the information of the output file;
the special interface specification file includes: the interface information of the unmatched module to be tested and the interface information of the associated module which has a connection relation with the interface information of the unmatched module to be tested.
The hierarchical configuration file includes: the name of the module to be tested or the name of the associated module, for example by name; a hierarchy of modules to be tested and associated modules, for example denoted by hier; the file names and paths of the modules to be tested and the related modules are represented by paths, for example; the storage location and format of the output file are specified, for example, as output.
The definition and format of the hierarchical configuration file is as follows:
the special interface specification file includes: the signal name of the unmatched signal (source signal) and the module name of the module to be tested are not matched;
the signal name of the connection signal (target signal) and the module name of the associated module in which it is located. The definition and format of the special interface specification file is as follows:
the special signal relation specification document mainly aims at that an input interface and an output interface are not directly connected and have a certain logic relation, or are processed in peripheral logic, for example, an input signal and an output signal are inverted, delay exists between the signals, and the signals directly need clock signal synchronization.
The special signal relationship specification file is also expandable and can be checked by the sva method when multiple signals exist in a logical or temporal relationship.
The definition and format of the special signal relationship specification file is as follows:
in some embodiments, after outputting the set of connection relationships to the connectivity test file, the method further comprises:
acquiring an output interface file of the module to be tested, and searching the input interface file of the correlation module for correlation input signals matched with the output signals to be tested in the output interface file in sequence;
and forming a connection relation group by the matched associated input signals and the output signals to be tested, and outputting the connection relation group to the connectivity test file.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 2, an embodiment of the present invention further provides a system for generating a connectivity test file, including:
a creating module 110, wherein the creating module 110 is configured to create a hierarchical configuration file, a special interface description file and a special signal relation description file;
the analysis module 120 is configured to obtain a configuration file of a chip to be verified, and analyze input and output interface information of each module to be tested and the associated module in the configuration file based on the hierarchical configuration file to generate an input and output interface file of the module to be tested and an input and output interface file of the associated module respectively;
a searching module 130, wherein the searching module 130 is configured to obtain the input interface file of the module to be tested, and sequentially search the output interface file of the associated module for an output signal matched with the input signal in the input interface file;
the search module 130 is further configured to combine the output signals in the matched output interface file and the input signals in the input interface file into a connection relationship group, and output the connection relationship group to a connectivity test file;
an updating module 140, wherein the updating module 140 is configured to update the connection relation group of the connectivity test file based on the special signal relation specification file to obtain a final connectivity test file.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 3, an embodiment of the present invention further provides a computer-readable storage medium 40, where the computer-readable storage medium 40 stores a computer program 410, which when executed by a processor, performs the above method.
The embodiment of the invention also can comprise corresponding computer equipment. The computer device comprises a memory, at least one processor and a computer program stored on the memory and executable on the processor, the processor performing any of the above methods when executing the program.
The memory, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for generating a connectivity test file in the embodiments of the present application. The processor executes various functional applications and data processing of the device by running the nonvolatile software program, instructions and modules stored in the memory, that is, the method for generating the connectivity test file of the above-mentioned method embodiment is realized.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the device, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and such remote memory may be coupled to the local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method of generating a connectivity test file, comprising:
establishing a hierarchical structure configuration file, a special interface description file and a special signal relation description file;
acquiring a configuration file of a chip to be verified, and analyzing input and output interface information of each module to be tested and an associated module in the configuration file based on the hierarchical structure configuration file to respectively generate an input interface file and an output interface file of the module to be tested and an input interface file and an output interface file of the associated module;
acquiring an input interface file of the module to be tested, and searching output signals matched with input signals in the input interface file in the output interface file of the associated module in sequence;
forming a connection relation group by the output signals in the output interface file and the input signals in the input interface file which are matched with each other, and outputting the connection relation group to a connectivity test file;
and updating the connection relation group of the connectivity test file based on the special signal relation description file to obtain a final connectivity test file.
2. The method of claim 1, further comprising:
if the output signal matched with the input signal in the input interface file is not searched in the output interface file, searching the output signal which is in connection relation with the unmatched input signal in the output interface file based on the special interface description file and the unmatched input signal;
and outputting the unmatched input signals and the output signals with the connection relation to the connectivity test file, and returning to the step of updating the connectivity test file based on the special interface description file.
3. The method of claim 2, further comprising:
and if the output signals which have connection relation with the unmatched input signals are not searched in the output interface file, outputting the unmatched input signals and the modules where the unmatched input signals are located to an error file.
4. The method of claim 1, wherein updating the set of connection relationships of the connectivity test file based on the special signal relationship specification file to obtain a final connectivity test file comprises:
and updating each connection relation group in the connectivity test file according to the connectivity test function of the special signal relation description file to obtain a final connectivity test file.
5. The method according to claim 4, wherein updating each connection relation group in the connectivity test file according to the connectivity test function of the special signal relation specification file to obtain a final connectivity test file comprises:
and acquiring the parameter length and the special character of the connection relation group, and calling a corresponding connectivity test function to update the connection relation group based on the parameter length and the special character.
6. The method of claim 1, wherein parsing the input and output interface information of each module under test and associated module in the configuration file based on the hierarchical configuration file to generate an input and output interface file of the module under test and an input and output interface file of the associated module, respectively, comprises:
extracting path information of each module to be tested and the associated module of the chip to be verified from the configuration file based on the hierarchical structure configuration file;
extracting interface information of the module to be tested and interface information of the correlation module based on the path information;
and analyzing the interface information of the to-be-tested module and the interface information of the associated module to respectively generate input and output interface files of each to-be-tested module and input and output interface files of the associated module of the to-be-verified chip.
7. The method of claim 1, wherein the hierarchy configuration file comprises: the information of the module to be tested, the information of the associated module and the information of the output file;
the special interface specification file includes: the interface information of the unmatched module to be tested and the interface information of the associated module which has a connection relation with the interface information of the unmatched module to be tested.
8. The method of claim 1, wherein after outputting the set of connection relationships to the connectivity test file, the method further comprises:
acquiring an output interface file of the module to be tested, and searching the input interface file of the correlation module for correlation input signals matched with the output signals to be tested in the output interface file in sequence;
and forming a connection relation group by the matched associated input signals and the output signals to be tested, and outputting the connection relation group to the connectivity test file.
9. A system for generating a connectivity test file, comprising:
a creation module configured to create a hierarchical configuration file, a special interface specification file, a special signal relationship specification file;
the analysis module is configured to acquire a configuration file of a chip to be verified, and analyze input and output interface information of each module to be tested and the associated module in the configuration file based on the hierarchical structure configuration file to respectively generate an input and output interface file of the module to be tested and an input and output interface file of the associated module;
the searching module is configured to acquire the input interface file of the module to be tested and sequentially search the output interface file of the correlation module for the output signal matched with the input signal in the input interface file;
the searching module is also configured to form a connection relation group by the output signals in the matched output interface file and the input signals in the input interface file, and output the connection relation group to a connectivity test file;
an update module configured to update the connection relationship group of the connectivity test file based on the special signal relationship specification file to obtain a final connectivity test file.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 8.
CN202111553750.8A 2021-12-17 2021-12-17 Method and system for generating connectivity test file and readable storage medium Pending CN114266211A (en)

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