CN114265717A - Instruction synchronization device, chip, computer equipment and data processing method - Google Patents
Instruction synchronization device, chip, computer equipment and data processing method Download PDFInfo
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- CN114265717A CN114265717A CN202111652996.0A CN202111652996A CN114265717A CN 114265717 A CN114265717 A CN 114265717A CN 202111652996 A CN202111652996 A CN 202111652996A CN 114265717 A CN114265717 A CN 114265717A
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Abstract
The embodiment of the disclosure provides an instruction synchronization device, a chip and a computer device, and a data processing method, wherein a trigger instruction and a wait instruction are inserted into an instruction queue, and a count value of a counter is adjusted through the trigger instruction and the wait instruction, and since an instruction after the wait instruction can be sent only when the count value meets a preset value condition, the sending sequence of instructions in the instruction queues can be controlled through the above method, so that instruction synchronization among the instruction queues is realized. The embodiment adopts a hardware mode to realize the synchronization between the instruction queues, and improves the efficiency of a hardware system.
Description
Technical Field
The present disclosure relates to the field of artificial intelligence technologies, and in particular, to an instruction synchronization apparatus, a chip, a computer device, and a data processing method.
Background
In a graphics processor and an artificial intelligence acceleration chip, the computing power of the processor is improved and the parallel processing of data is realized through multiple processes. A large number of processes working in parallel have synchronization dependencies, e.g. an instruction included in one process needs to be sent until the sending of an instruction included in another process is completed. Therefore, it is necessary to design a synchronization mechanism between instructions. However, the instruction synchronization mechanism in the related art causes inefficiency of the hardware system.
Disclosure of Invention
In a first aspect, an embodiment of the present disclosure provides an instruction synchronization apparatus, where the apparatus includes: a counter, and a plurality of instruction queues; each instruction queue of the plurality of instruction queues is used for storing instructions, the instructions comprise execution instructions and at least one of triggering instructions and waiting instructions; the counter is used for responding to the received trigger instruction to carry out first adjustment on the counting value and responding to the received waiting instruction to carry out second adjustment on the counting value; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment; and sending the instruction after the waiting instruction in one instruction queue under the condition that the counting value meets a preset value condition, wherein the preset value condition is determined based on the initial counting value of the counter, the adjustment mode of the first adjustment and the adjustment mode of the second adjustment.
In some embodiments, each instruction queue is configured to parse stored instructions, send parsed trigger instructions and wait instructions to the counter, and send parsed execution instructions to an execution unit.
In some embodiments, one of the first adjustment and the second adjustment is adjusted by increasing the count value by a first preset step size, and the other is adjusted by decreasing the count value by a second preset step size; the first preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues.
In some embodiments, the trigger instruction carries the first preset step size, and the wait instruction carries the second preset step size.
In some embodiments, the first preset step is equal to the product of the number of waiting queues and a preset multiple, the second preset step is equal to the product of the number of waiting queues and the preset multiple, and the like.
In some embodiments, the preset numerical condition is determined based on the initial count value, the first preset step size, the second preset step size, and a preset multiple.
In some embodiments, the preset numerical condition is: the counting value and the target counting value meet a preset numerical value relationship, and the target counting value is as follows: n m a-1+ k 0; wherein n is the first preset step length, m is the second preset step length, a is the preset multiple, and k0 is the initial counting value; when the first adjustment is to increase the count value and the second adjustment is to decrease the count value, the numerical relationship is that the count value is greater than the target count value; and when the first adjustment is to decrease the count value and the second adjustment is to increase the count value, the numerical relationship is that the count value is smaller than the target count value.
In some embodiments, the plurality of instruction queues includes a waited queue and a wait queue; the waiting queue comprises a plurality of trigger instructions, each trigger instruction corresponds to a synchronous event, and the plurality of trigger instructions are used for adjusting the count value of the same counter; a target waiting instruction is also included after the first trigger instruction in the waiting queue; a target trigger instruction is also included after each first waiting instruction in the waiting queue; the ith first trigger instruction in the to-be-waited queue and the ith first waiting instruction in the waiting queue are instructions corresponding to the ith synchronous event, and i is a positive integer.
In some embodiments, the number of counters is greater than 1; the trigger instruction and the waiting instruction included in each instruction queue comprise: and the identification information of the counter is used for the instruction queue to send the trigger instruction and the waiting instruction which are included by the instruction queue to the corresponding counter.
In some embodiments, the instruction synchronization apparatus further comprises: and the execution unit is used for executing the received execution instruction.
In some embodiments, the instruction synchronization apparatus further comprises: and the arbitration unit is used for sending the execution instruction sent by each instruction queue in the plurality of instruction queues to the execution unit according to the preset priority.
In some embodiments, the instruction synchronization apparatus further comprises: and the multiplexer is used for sending the instruction to a corresponding instruction queue in the plurality of instruction queues.
In some embodiments, the trigger instruction and the wait instruction each comprise: and the identification information of the instruction queue is used for the multiplexer to send the trigger instruction and the waiting instruction to the corresponding instruction queue.
In a second aspect, an embodiment of the present disclosure provides a chip, including: the instruction synchronization device according to any embodiment of the disclosure.
In a third aspect, an embodiment of the present disclosure provides a computer device, including: the chip according to any embodiment of the disclosure.
In a fourth aspect, an embodiment of the present disclosure provides a data processing method, which is applied to the instruction synchronization apparatus according to any embodiment of the present disclosure, where the method includes: each instruction queue of the plurality of instruction queues stores instructions, the instructions including execution instructions and at least one of trigger instructions and wait instructions; the counter performs first adjustment on the count value in response to receiving the trigger instruction, and performs second adjustment on the count value in response to receiving the waiting instruction; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment; and each instruction queue sends the instruction behind the waiting instruction in the queue under the condition that the counting value meets a preset value condition, wherein the preset value condition is determined based on the initial counting value of the counter, the adjustment mode of the first adjustment and the adjustment mode of the second adjustment.
In some embodiments, the method further comprises: each instruction queue analyzes the stored instructions, sends the analyzed triggering instructions and waiting instructions to the counter, and sends the analyzed execution instructions to the execution unit.
In some embodiments, the counter performs a first adjustment of the count value in response to receiving a trigger instruction and a second adjustment of the count value in response to receiving a wait instruction, comprising: increasing the count value according to a first preset step length in response to receiving a trigger instruction, and decreasing the count value according to a second preset step length in response to receiving a waiting instruction; or, the count value is decreased according to a first preset step length in response to receiving a trigger instruction, and the count value is increased according to a second preset step length in response to receiving a waiting instruction.
In some embodiments, the first preset step size is determined based on a number of waiting queues of the plurality of instruction queues associated with a target synchronization event, and the second preset step size is determined based on a number of waiting queues of the plurality of instruction queues associated with the target synchronization event.
In some embodiments, the method further comprises: and the counter acquires the first preset step length carried in the trigger instruction and acquires the second preset step length carried in the waiting instruction.
In some embodiments, the first preset step is equal to the product of the number of waiting queues and a preset multiple, the second preset step is equal to the product of the number of waiting queues and the preset multiple, and the like.
In some embodiments, the preset numerical condition is determined based on the initial count value, the first preset step size, the second preset step size, and a preset multiple.
In some embodiments, the preset numerical condition is: the counting value and the target counting value meet a preset numerical value relationship, and the target counting value is as follows: n m a-1+ k 0; wherein n is the first preset step length, m is the second preset step length, a is the preset multiple, and k0 is the initial counting value.
In some embodiments, the method further comprises: determining, by each instruction queue, the numerical relationship that the count value is greater than the target count value when the first adjustment mode is to increase the count value and the second adjustment mode is to decrease the count value; and determining the numerical relationship of each instruction queue to be that the count value is smaller than the target count value when the first adjustment mode is to reduce the count value and the second adjustment mode is to increase the count value.
In some embodiments, the plurality of instruction queues includes a waited queue and a wait queue; the waiting queue comprises a plurality of trigger instructions, each trigger instruction corresponds to a synchronous event, and the plurality of trigger instructions are used for adjusting the count value of the same counter; a target waiting instruction is also included after the first trigger instruction in the waiting queue; a target trigger instruction is also included after each first waiting instruction in the waiting queue; the first trigger instruction and the first waiting instruction are corresponding instructions of other synchronous events except the last synchronous event.
In some embodiments, the number of counters is greater than 1; the method further comprises the following steps: and each instruction queue acquires the identification information of the counters included in the trigger instructions and the waiting instructions in the queue, and sends the trigger instructions and the waiting instructions in the queue to the corresponding counters based on the identification information of the counters included in the trigger instructions and the waiting instructions in the queue.
In some embodiments, sending the parsed execution instructions to the execution unit includes: and sending the analyzed execution instruction to an arbitration unit so that the arbitration unit sends the execution instruction sent by each instruction queue in the plurality of instruction queues to the execution unit according to the preset priority.
In some embodiments, the method further comprises: and each instruction queue acquires the instruction sent by the multiplexer and stores the instruction sent by the multiplexer.
In some embodiments, each instruction queue fetches instructions sent by a multiplexer, including: and each instruction queue acquires the instruction sent to the queue by the multiplexer based on the identification information of the instruction queue included in the instruction.
According to the embodiment of the disclosure, the trigger instruction and the wait instruction are inserted into the instruction queue, and the count value of the counter is adjusted through the trigger instruction and the wait instruction, and the instruction after the wait instruction can be sent only when the count value meets the preset value condition, so that the sending sequence of the instructions in the instruction queues can be controlled through the above manner, and the instruction synchronization among the instruction queues is realized. The embodiment adopts a hardware mode to realize the synchronization between the instruction queues, and improves the efficiency of a hardware system.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of an instruction synchronization process.
Fig. 2 is a schematic structural diagram of an instruction synchronization apparatus according to an embodiment of the present disclosure.
FIG. 3 is a schematic diagram of an instruction synchronization method according to an embodiment of the disclosure.
FIG. 4 is a diagram illustrating an instruction synchronization method according to another embodiment of the disclosure.
Fig. 5A is a schematic diagram illustrating an instruction synchronization manner when multiple synchronization events are mapped to the same synchronization counter according to an embodiment of the present disclosure.
FIG. 5B is a schematic diagram of the instruction issue order in the instruction queue of FIG. 5A.
Fig. 6 is a schematic structural diagram of an instruction synchronization apparatus according to another embodiment of the present disclosure.
Fig. 7 is a flow chart of a data processing method of an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present disclosure. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
In order to make the technical solutions in the embodiments of the present disclosure better understood and make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings.
In the multi-process parallel processing scene, a large number of parallel processes have synchronous dependency relationship. For example, an instruction included in one process may need to be sent if the sending of an instruction included in another process is complete.
The instructions may be issued to each instruction queue according to a preset distribution rule, and there may be a dependency relationship or no dependency relationship between the instructions in different instruction queues. Under the condition that the instructions in the two instruction queues have no dependency relationship, the instructions in the two instruction queues can be sent in parallel, so that the parallel degree between the instructions is improved; under the condition that the instructions in the two instruction queues have dependency relationship, the instructions with the dependency relationship can be ensured to be sent according to a certain sequence by setting an instruction synchronization mechanism in the two queues.
Referring to FIG. 1, a diagram of instruction synchronization of some embodiments is shown. Assuming that the instructions Q1 and Q2 in the instruction queue 1 depend on the instructions Q1, Q2 and Q3 in the instruction queue 2, i.e., the instructions Q1 and Q2 need to be issued when the instructions Q1, Q2 and Q3 are all issued completely, the issue order of the instructions is shown by the time axis in the figure. It will be understood by those skilled in the art that the instruction sending order shown in the figure is only an exemplary illustration, in practical applications, instructions in the same instruction queue are sent sequentially according to the order in which the instructions are stored in the instruction queue, and instructions without dependency relationship between different instruction queues may be sent according to any sending order. For example, the instruction Q4 may be issued earlier than the instruction Q3, or the instruction Q1 may be issued between the instruction Q3 and the instruction Q4. But because instructions Q1 and Q2 depend on instructions Q1, Q2, and Q3, instructions Q1, Q2, and Q3 all issue earlier than instruction Q1 and earlier than instruction Q2.
In the related art, the instructions sent by the current instruction queue are counted by deploying an instruction counter for each instruction queue, and synchronization is realized among other instruction queues by waiting for the count value of the instruction counter of the corresponding instruction queue. However, this way of instruction synchronization, where only the producer has no consumer, risks overflow, and the instructions in each instruction queue can be the same type of instruction. To solve the above problem, another related art employs a producer-consumer model, where a state synchronization counter is deployed between every two instruction queues to implement instruction synchronization. However, in this method, a static state synchronization counter is deployed, and assuming that the number of instruction queues is N, the number of state synchronization counters to be deployed is N (N-1), which results in a waste of the number of counters. In order to solve this technical problem, there is a related art to dynamically allocate a state synchronization counter according to a synchronization event, however, this approach is implemented in software, which reduces the efficiency of a hardware system.
Based on this, the disclosed embodiment provides an instruction synchronization apparatus, referring to fig. 2 and 6, the apparatus includes:
a counter 201, and a plurality of instruction queues 202; each instruction queue (e.g., instruction queue 1, instruction queue 2, instruction queue 3, instruction queue 4, etc.) of the plurality of instruction queues 202 is to store instructions, including execution instructions, and at least one of Trigger instructions Trigger and Wait instructions Wait;
the counter 201 is configured to perform a first adjustment on the count value in response to receiving the Trigger instruction Trigger, and perform a second adjustment on the count value in response to receiving the Wait instruction Wait; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment;
instructions in one instruction queue 202 after the Wait instruction Wait are sent when the count value meets a preset value condition, where the preset value condition is determined based on the initial count value of the counter 201, the adjustment manner of the first adjustment, and the adjustment manner of the second adjustment.
In this embodiment, the number of counters (also referred to as synchronization counters) 201 may be greater than or equal to 1, the number of instruction queues 202 may be greater than or equal to 2, and the illustrated case shows that the number of counters 201 and the number of instruction queues 202 are both 4, but it can be understood by those skilled in the art that the illustrated case is not used to limit the present disclosure, the number of counters 201 and the number of instruction queues 202 may be set to be other numbers greater than 4 or less than 4 according to actual needs, and the number of counters 201 and the number of instruction queues 202 may be equal or may not be equal.
An instruction queue 202 may be used to store execution instructions for sending to execution units for execution. For example, the execution instruction may include, but is not limited to, at least one of various operation instructions such as an add instruction, a multiply instruction, a convolution multiply instruction, and the like. The execution unit may perform an operation on the acquired target data in response to the execution instruction. The target data may be image data, voice data, text data, or other data of various forms.
Instructions in one or more instruction queues may have dependencies with instructions in another one or more instruction queues. In order to perform instruction synchronization on instructions with dependency relationships, a Trigger instruction Trigger and a Wait instruction Wait may be inserted into an instruction queue. The instructions in the respective instruction queues may have different dependencies at different times, for example, at time t1, the instruction in instruction queue 1 needs to wait for the instruction in instruction 2 to complete sending before sending (this case is called instruction queue 1 waiting for instruction queue 2, instruction queue 1 is called waiting queue, and instruction queue 2 is called waiting queue); at time t2, there is no dependency between the instructions in instruction queue 1 and the instructions in instruction queue 2; at time t3, instruction queue 2 needs to wait for instruction queue 1.
In the above example, the instruction queue 1 waiting instruction queue 2 is referred to as a synchronous event, the waiting queue involved in a synchronous event is referred to as a waiting queue corresponding to the synchronous event, and the waiting queue involved in a synchronous event is referred to as a waiting queue corresponding to the synchronous event. The same instruction queue may correspond to one or more synchronization events, for example, at a certain time, an instruction in instruction queue 1 needs to wait for an instruction in instruction queue 2 to complete sending for sending; at another moment, one instruction in the instruction queue 1 needs to wait for the completion of the sending of two instructions in the instruction queue 3 to send; at yet another time, three instructions in instruction queue 4 need to wait for two instructions in instruction queue 1 to complete to issue. Then in the above example, instruction queue 1 corresponds to 3 synchronous events, respectively.
For ease of understanding, two dependent instruction queues are first described below. First, after receiving the instructions, the instruction queue may store the instructions in the order in which the instructions were received, or may parse the stored instructions. Each instruction can include the type of the instruction, and the instruction queue can determine whether the instruction is an execution instruction, a trigger instruction or a waiting instruction according to the type of the instruction. Referring to fig. 3, an instruction 1, an instruction 2, an instruction 3, and the like represent an execution instruction, Trigger and Wait respectively represent a Trigger instruction and a Wait instruction, and an instruction after the Wait instruction in the instruction queue 1 needs to Wait for completion of transmission of each instruction before the Trigger instruction in the instruction queue 2 before transmission. The instruction queue can send the execution instruction to the execution unit after the execution instruction is analyzed; after parsing out the trigger instruction or wait instruction, the trigger instruction or wait instruction may be sent to the counter 201.
The trigger instruction and the wait instruction can trigger the count value of the counter to be adjusted in a first adjustment mode and a second adjustment mode respectively. For example, by sending a trigger instruction to the counter, the counter may be triggered to increment the count value, and by sending a wait instruction to the counter, the counter may be triggered to decrement the count value. Alternatively, the counter may be triggered to decrement the count value by sending a trigger instruction to the counter, and the counter may be triggered to increment the count value by sending a wait instruction to the counter.
In some embodiments, one of the first adjustment and the second adjustment is adjusted by increasing the count value by a first preset step size, and the other is adjusted by decreasing the count value by a second preset step size. For example, each trigger instruction may trigger the counter to increment the count value by 1, and each wait instruction may trigger the counter to decrement the count value by 1. Of course, in addition to taking 1 as the first preset step length and the second preset step length, other positive integers may be taken as the first preset step length and the second preset step length. For example, in the embodiment shown in fig. 3, the first preset step size and the second preset step size may both be 2. In this case, each trigger instruction may trigger the counter to increment the count value by 2, and each wait instruction may trigger the counter to decrement the count value by 2. In a target synchronization event, the first preset step size may not be equal in case that the number of waiting queues is different from the number of queues to be waited. Specifically, the first preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues. For example, assuming that the number of waiting queues is n and the number of queues to be waited is m, a first preset step size may be set to n × a and a second preset step size may be set to m × a, where a is a positive integer.
In some embodiments, the trigger instruction carries the first preset step size, and the wait instruction carries the second preset step size. Since the instruction carries the step information, the counter can directly read the corresponding step information from the instruction after receiving the trigger instruction or the waiting instruction, so as to determine the step for increasing or decreasing the count value. Furthermore, the trigger instruction may further carry identification information for characterizing the adjustment mode of the first adjustment, and the wait instruction may further carry identification information for characterizing the adjustment mode of the second adjustment, so that the counter determines which adjustment mode is used to adjust the step length of the counter.
The instructions in one instruction queue after the waiting instruction are sent only under the condition that the counting value of the counter meets the preset value condition, so that the sending sequence of the instructions in the instruction queue can be controlled based on the counting value of the counter, and the instruction synchronization among the instruction queues is realized. In some embodiments, the preset numerical condition is determined based on the initial count value, the first preset step size, the second preset step size, and a preset multiple. Specifically, the preset value condition may be that the count value of the counter and the target count value satisfy a preset value relationship. The product of the first preset step length, the second preset step length and a preset multiple can be determined, the product and the initial counting value are summed, and the numerical value relationship is determined based on the sum. Assuming that the first preset step is denoted as n, the second preset step is denoted as m, the preset multiple is denoted as a, and the initial count value is denoted as k0, the target count value may be denoted as n × m × a-1+ k 0.
In different cases, different numerical relationships may be determined. For example, in the first mode, if the first adjustment is to increase the count value, and the second adjustment is to decrease the count value, the numerical relationship is that the count value is greater than the target count value. In a second mode, the first adjustment is to decrease the count value, and the second adjustment is to increase the count value, so that the numerical relationship is that the count value is smaller than the target count value. The following describes aspects of the embodiments of the present disclosure by taking the above-described first embodiment as an example.
In the embodiment shown in fig. 3, m and n are equal to 1, and it is assumed that the preset multiple a is also equal to 1, and the initial value of the counter is 0. And the instructions 4 and 5 in the instruction queue 1 need to wait for the instructions 1 and 2 in the instruction queue 2 to finish sending and then send. Therefore, a Trigger instruction Trigger may be inserted after instruction 2 in instruction queue 2 and a Wait instruction Wait may be inserted before instruction 4 in instruction queue 1. The instruction queue 2 may parse each instruction in the queue and send the parsed instructions sequentially. Wherein, instruction 1 and instruction 2 are both execution instructions and can be sequentially sent to the execution unit. At the same time, instruction queue 1 may issue the executing instructions (i.e., instruction 1, instruction 2, and instruction 3) in the present queue in parallel. The instructions with the same reference numbers, such as instruction 1 and instruction 2, in the two instruction queues may be the same instructions or different instructions, where the reference numbers of the instructions are only used for indicating the relative positions of the instructions in the instruction queues to which the instructions belong, and are not used for indicating the contents or types of the instructions. Since the transmission completion time of each instruction having no dependency relationship among different instruction queues is random, there may be a case where instruction 3 in instruction queue 1 completes transmission earlier than instruction 2 in instruction queue 2, or a case where instruction 2 in instruction queue 2 completes transmission earlier than instruction 3 in instruction queue 1.
In any case, because the Trigger instruction and the waiting instruction are respectively inserted into the two instruction queues, the instruction queue 2 sends the Trigger instruction Trigger to the counter after analyzing the Trigger instruction Trigger, and the counter adds 1 to the count value after receiving the Trigger instruction Trigger. After the instruction queue 1 resolves the Wait instruction Wait, the count value of the counter can be read, and only when the count value of the counter is greater than 0, the instruction queue 1 will send the Wait instruction Wait and each instruction after the Wait instruction Wait, otherwise, each instruction after the Wait instruction Wait and each instruction after the Wait instruction Wait are not sent. And the counter may decrement the count value by 1 in the case where the Wait instruction Wait is received. In this way, a synchronous event is completed. If other synchronization events exist between the two instruction queues, the instruction synchronization is carried out continuously according to the process.
In the more general case shown in FIG. 4, where m and n are both positive integers greater than 1, and m and n may not be equal, this is referred to as the n instruction queues waiting for the m instruction queues. Wherein, the instructions 4 and 5 in each waiting queue (i.e. the instruction queue 1 to the instruction queue n above the counter) need to wait for the instructions 3 in all the waiting queues (i.e. the instruction queue 1 to the instruction queue m below the counter) to complete sending before sending. Assuming that the initial count value is 0 and the preset multiple a is 1, after each of the queues to be waited (for example, the instruction queue 1) sends a trigger instruction to the counter, the count value of the counter may be increased by n, so that after all the queues to be waited send the trigger instruction to the counter, the counter has a value of n × m. Each waiting queue can read the count value of the counter under the condition that the waiting instruction is analyzed, if the count value is larger than n m < -1 >, the waiting queue can send the waiting instruction so that the counter subtracts m from the count value, and after all waiting queues send the waiting instruction, the count value of the counter returns to 0. Thus, a synchronization event is completed.
Of course, the situation shown in the figure is only an exemplary illustration, and in practical applications, the positions of the instructions in the waiting state in the respective waiting queues in the belonging instruction queues may be different, and the positions of the instructions in the waiting state in the respective waiting queues in the belonging instruction queues may also be different.
In the embodiment of determining the numerical relationship in the second manner, the synchronization process of the synchronization event is similar to that in the embodiments shown in fig. 3 and 4, and is not described again here. The only difference is that the counter subtracts the count value from the initial count value (e.g. 5) after receiving the trigger instruction, and the counter increases the count value by the corresponding value after receiving the wait instruction, and the wait can continue to send the instruction only if the count value is less than the initial count value. In this manner, a synchronization event is also completed.
In the case where multiple synchronization events are mapped to a counter, a trigger instruction in a later synchronization event may false trigger a wait instruction in a previous synchronization event. Referring to fig. 5A and 5B, assume that there are two synchronization events, respectively: (1) instruction queues 1, 2 wait for instruction queues 3, 4, 5; and (2) instruction queues 1, 2 wait for instruction queue 3. The Trigger1 in the instruction queue 3, the instruction queue 4 and the instruction queue 5 and the Wait1 in the instruction queue 1 and the instruction queue 2 correspond to a first synchronous event, and the Trigger2 in the instruction queue 3 and the Wait2 in the instruction queue 1 and the instruction queue 2 correspond to a second synchronous event. The respective instruction queues obtained by inserting the Trigger instruction and the wait instruction in the foregoing embodiment are as shown in the case one in fig. 5A, and since the time for each instruction queue to send Trigger is random, in some cases, the Trigger instruction Trigger2 in the instruction queue 3 may be earlier than the time for the instruction queue 4 to send the Trigger instruction Trigger1, and the sending time sequence of the instructions is as shown in the instruction sending sequence of the case one in fig. 5B. For simplicity, only the order of sending trigger instructions in the instruction queues 3, 4, 5 is shown in the figure.
Assuming that the initial value of the count is 0, the counter increments the count by n every time the counter receives a trigger instruction, and decrements the count by m every time the counter receives a wait instruction, where n and m are the number of waiting queues and the number of queues to be waited in a synchronization event, respectively. In the first synchronization event, n is 2 and m is 3, that is, when the count value of the counter is greater than 5, the wait instruction in the wait queue and the execution instruction located after the wait instruction may be sent. In this embodiment, since Trigger2 of the instruction queue 3 is sent before Trigger1 of the instruction queue 4, after Trigger1 is sent by the instruction queue 4, the count value of the counter will reach 6, which triggers the wait queue to send the relevant instruction. However, in the actual situation, Trigger1 of instruction queue 5 has not yet been issued, and the relevant instructions in the wait queue do not satisfy the issue condition. It can be seen that Trigger2 in instruction queue 3 can falsely Trigger Wait for synchronization event 1 in the above case.
In order to solve the above problem, in the embodiments of the present disclosure, the plurality of instruction queues include a to-be-waited queue and a waiting queue; the waiting queue comprises a plurality of trigger instructions, each trigger instruction corresponds to a synchronous event, and the plurality of trigger instructions are used for adjusting the count value of the same counter; a target waiting instruction is also included after the first trigger instruction in the waiting queue; a target trigger instruction is also included after each first waiting instruction in the waiting queue; the ith first trigger instruction in the to-be-waited queue and the ith first waiting instruction in the waiting queue are instructions corresponding to the ith synchronous event, and i is a positive integer.
The number of waiting queues may be greater than or equal to 1, the number of queues to be waited may also be greater than or equal to 1, the first trigger instructions corresponding to different synchronization events may come from one or more queues to be waited, and the first waiting instructions corresponding to different synchronization events may come from one or more queues to be waited. Assuming that the total number of the synchronization events is N, the first trigger instruction corresponding to the 1 st synchronization event, the first trigger instruction corresponding to the 2 nd synchronization event, … …, and the first trigger instruction corresponding to the N-1 st synchronization event each include a target wait instruction; and a first wait instruction corresponding to the 1 st synchronous event, a first wait instruction corresponding to the 2 nd synchronous event … …, and a target trigger instruction after the first wait instruction corresponding to the N-1 th synchronous event. The first trigger instruction corresponding to the nth synchronization event may or may not include a target wait instruction, and the first wait instruction corresponding to the nth synchronization event may or may not include a target trigger instruction.
If the first trigger instruction corresponding to a certain synchronization event comes from a plurality of waiting queues, the first trigger instruction in each waiting queue of the plurality of waiting queues comprises a target waiting instruction. For example, if a synchronization event is that instruction 1 in instruction queue 2 waits for instruction 2 in instruction queue 3 and instruction 3 in instruction queue 4, then both instruction queue 3 and instruction queue 4 include a first trigger instruction corresponding to the synchronization event, so that the first trigger instruction in instruction queue 3 includes a target wait instruction, and the first trigger instruction in instruction queue 4 also includes a target wait instruction. Similarly, if the first wait instruction corresponding to a synchronization event comes from multiple wait queues, the first trigger instruction in each of the multiple wait queues includes a target trigger instruction. For example, if a synchronization event is instruction 1 in instruction queue 1 and instruction 1 in instruction queue 2 waits for instruction 2 in instruction queue 3, then both instruction 1 and instruction queue 2 include a first wait instruction corresponding to the synchronization event, so that the first wait instruction in instruction queue 1 includes a target trigger instruction, and the first wait instruction in instruction queue 2 also includes a target trigger instruction.
Referring to the instruction sending sequence of the second case in fig. 5A and the second case in fig. 5B, the first Trigger instruction is Trigger1 in the instruction queue 3, the target Wait instruction is Wait behind Trigger1 in the instruction queue 3, the first Wait instruction is Wait1 in the instruction queue 1 and Wait1 in the instruction queue 2, and the target Trigger instruction is Trigger behind Wait1 in the instruction queue 1 and Trigger behind Wait1 in the instruction queue 2. In the case that the instructions in the instruction queue 3 are sent faster, the Trigger1 in the instruction queue 3 may be sent first, but since Wait is inserted after the Trigger1 in the instruction queue 3, the Wait in the instruction queue 3 does not satisfy the sending condition when the Trigger1 in the instruction queue 3 is sent completely, and the Trigger1 in the instruction queue 4 and the instruction queue 5 is not sent completely, so that the Wait state is entered after the Trigger1 in the instruction queue 3 is sent completely. Likewise, Wait1 in instruction queue 1 and Wait1 in instruction queue 2 cause instruction queue 1 and instruction queue 2 to also enter a Wait state. Therefore, Trigger1 in instruction queue 4 and Trigger1 in instruction queue 5 are issued first. Therefore, after the Wait of the first synchronous event normally occurs, the Trigger of the second synchronous event can take effect.
In the embodiment shown in fig. 5A and 5B, the number of synchronization events mapped to the same counter is 2, i.e., there is at least one queue being waited (instruction queue 3 in the figure) corresponding to two synchronization events, respectively. In practical applications, the number of synchronization events mapped to the same counter may be greater than 2, and there may be more than one queue waiting for each of the plurality of synchronization events. In addition, although the waiting queues in the two synchronization events are shown as being the same (both instruction queue 1 and instruction queue 2), in practical applications, the waiting queues in different events may be partially the same or completely different. In addition, the position of the target wait instruction after the first trigger instruction does not have to be immediately adjacent to the first trigger instruction, as long as the target wait instruction is between the first trigger instruction and the next first trigger instruction after the first trigger instruction. Similarly, the position of the target trigger instruction after the first wait instruction is not necessarily adjacent to the first wait instruction, and may be between the first wait instruction and the next first wait instruction after the first wait instruction. For example, in the instruction queue 3 shown in case two of fig. 5A, Wait after Trigger1 may be located at any position between Trigger1 and Trigger 2. In the instruction queue 2 shown in the second case of fig. 5A, Trigger after Wait1 may be located at any position between Wait1 and Wait 2. In the above situation, the false triggering of the synchronization event may also be avoided by inserting the target wait instruction and the target trigger instruction, which is not described herein again.
In some embodiments, the number of counters 201 is greater than 1. In this case, the trigger instruction and the wait instruction included in each instruction queue may include identification information of a counter, which is used for the instruction queue to send the trigger instruction and the wait instruction included in the instruction queue to the corresponding counter. Or, the identification information of the trigger instruction and the identification information of the wait instruction may be bound to the identification information of the counter, respectively, so that the instruction queue sends the trigger instruction and the wait instruction to the corresponding counters.
In some embodiments, the instruction synchronization apparatus further comprises an execution unit 203 for executing the received execution instruction. The number of execution units may be greater than or equal to 1, and one execution unit may receive and process execution instructions of one or more instruction queues. An execution unit may be a sub-unit of a processing unit with instruction execution functionality, and the processing unit may be divided into multiple groups of execution units according to different granularities, where each group of execution units may be used to perform a processing task (e.g., an addition operation). Under different conditions, different partition granularities can be adopted according to different actual requirements. For example, it is assumed that the processing unit includes R execution units, and the R execution units may be divided into s1 groups, each group including R1 execution units, or s2 groups, each group including R2 execution units, where R1R 1 s 2R 2. The division mode has higher flexibility, and under the condition that the number of execution units required by one processing task is less, the execution units can be divided into more groups, so that the parallelism of task processing is improved. The execution unit may also return a response signal (ACK) to the arbitration unit in case the processing of the instruction is completed, so that the arbitration unit continues to send new instructions.
In some embodiments, the instruction synchronization apparatus further includes an arbitration unit 204, configured to send the execution instruction sent by each of the instruction queues to the execution unit according to a preset priority. The number of the arbitration units 204 may be greater than or equal to 1, and the figure shows that the number of the arbitration units is equal to the number of the instruction queues, but in practical application, the numbers of the arbitration units and the instruction queues may not be equal.
In some embodiments, the instruction synchronization apparatus further comprises a multiplexer 205 for sending the instruction to a corresponding instruction queue of the plurality of instruction queues. In some embodiments, the trigger instruction and the wait instruction each include identification information of an instruction queue, so that the multiplexer 205 sends the trigger instruction and the wait instruction to the corresponding instruction queue.
The present disclosure provides a dynamic deployment mechanism of instruction queue state synchronization counters implemented by hardware, which saves counter overhead and eliminates the risk of overflow; meanwhile, the dynamic deployment of the counter is realized by adopting hardware, and efficient and flexible multi-process scheduling is also realized. The embodiment of the disclosure has strong expansibility, and the number of the state counters, the number of the instruction queues and the number of the execution units can be adjusted according to requirements. The instruction synchronization device of the embodiment of the disclosure can be applied to processing chips such as artificial intelligence chips and graphic processing chips, and can realize efficient and flexible instruction queue deployment and scheduling, thereby improving the parallel efficiency of the execution unit.
The various instructions in the above embodiments, including the trigger instruction, the wait instruction, and the execute instruction, may be generated in advance by way of offline compilation. The instructions may be generated and sent to the instruction queue in order as needed at off-line compilation.
In some embodiments, the present disclosure further provides a chip including the instruction synchronization apparatus according to any one of the embodiments of the present disclosure. The chip can be an artificial intelligence chip or a graphic processing chip, and can also be other types of processing chips. The details of the instruction synchronization apparatus in this chip embodiment may refer to the foregoing embodiments of the instruction synchronization apparatus, and are not described herein again.
The embodiment of the disclosure also provides a computer device, which includes the chip of any embodiment of the disclosure. The specific functions of the chip may refer to the description of the above chip embodiments, and are not described herein again for brevity.
As shown in fig. 7, an embodiment of the present disclosure further provides a data processing method, which is applied to the instruction synchronization apparatus according to any embodiment of the present disclosure, where the method includes:
step 701: each instruction queue of the plurality of instruction queues stores instructions, the instructions including execution instructions and at least one of trigger instructions and wait instructions;
step 702: the counter performs first adjustment on the count value in response to receiving the trigger instruction, and performs second adjustment on the count value in response to receiving the waiting instruction; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment;
step 703: and each instruction queue sends the instruction behind the waiting instruction in the queue under the condition that the counting value meets a preset value condition, wherein the preset value condition is determined based on the initial counting value of the counter, the adjustment mode of the first adjustment and the adjustment mode of the second adjustment.
In some embodiments, the method further comprises: each instruction queue analyzes the stored instructions, sends the analyzed triggering instructions and waiting instructions to the counter, and sends the analyzed execution instructions to the execution unit.
In some embodiments, the counter performs a first adjustment of the count value in response to receiving a trigger instruction and a second adjustment of the count value in response to receiving a wait instruction, comprising: increasing the count value according to a first preset step length in response to receiving a trigger instruction, and decreasing the count value according to a second preset step length in response to receiving a waiting instruction; or, the count value is decreased according to a first preset step length in response to receiving a trigger instruction, and the count value is increased according to a second preset step length in response to receiving a waiting instruction.
In some embodiments, the first preset step size is determined based on a number of waiting queues of the plurality of instruction queues associated with a target synchronization event, and the second preset step size is determined based on a number of waiting queues of the plurality of instruction queues associated with the target synchronization event.
In some embodiments, the method further comprises: and the counter acquires the first preset step length carried in the trigger instruction and acquires the second preset step length carried in the waiting instruction.
In some embodiments, the first preset step is equal to the product of the number of waiting queues and a preset multiple, the second preset step is equal to the product of the number of waiting queues and the preset multiple, and the like.
In some embodiments, the preset numerical condition is determined based on the initial count value, the first preset step size, the second preset step size, and a preset multiple.
In some embodiments, the preset numerical condition is: the counting value and the target counting value meet a preset numerical value relationship, and the target counting value is as follows: n m a-1+ k 0; wherein n is the first preset step length, m is the second preset step length, a is the preset multiple, and k0 is the initial counting value.
In some embodiments, the method further comprises: determining, by each instruction queue, the numerical relationship that the count value is greater than the target count value when the first adjustment mode is to increase the count value and the second adjustment mode is to decrease the count value; and determining the numerical relationship of each instruction queue to be that the count value is smaller than the target count value when the first adjustment mode is to reduce the count value and the second adjustment mode is to increase the count value.
In some embodiments, the plurality of instruction queues includes a waited queue and a wait queue; the waiting queue comprises a plurality of trigger instructions, each trigger instruction corresponds to a synchronous event, and the plurality of trigger instructions are used for adjusting the count value of the same counter; a target waiting instruction is also included after the first trigger instruction in the waiting queue; a target trigger instruction is also included after each first waiting instruction in the waiting queue; the first trigger instruction and the first waiting instruction are corresponding instructions of other synchronous events except the last synchronous event.
In some embodiments, the number of counters is greater than 1; the method further comprises the following steps: and each instruction queue acquires the identification information of the counters included in the trigger instructions and the waiting instructions in the queue, and sends the trigger instructions and the waiting instructions in the queue to the corresponding counters based on the identification information of the counters included in the trigger instructions and the waiting instructions in the queue.
In some embodiments, sending the parsed execution instructions to the execution unit includes: and sending the analyzed execution instruction to an arbitration unit so that the arbitration unit sends the execution instruction sent by each instruction queue in the plurality of instruction queues to the execution unit according to the preset priority.
In some embodiments, the method further comprises: and each instruction queue acquires the instruction sent by the multiplexer and stores the instruction sent by the multiplexer.
In some embodiments, each instruction queue fetches instructions sent by a multiplexer, including: and each instruction queue acquires the instruction sent to the queue by the multiplexer based on the identification information of the instruction queue included in the instruction.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions. A typical implementation device is a computer, which may take the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email messaging device, game console, tablet computer, wearable device, or a combination of any of these devices.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, it is relatively simple to describe, and reference may be made to some descriptions of the method embodiment for relevant points. The above-described apparatus embodiments are merely illustrative, and the modules described as separate components may or may not be physically separate, and the functions of the modules may be implemented in one or more software and/or hardware when implementing the embodiments of the present disclosure. And part or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
The foregoing is only a specific embodiment of the embodiments of the present disclosure, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the embodiments of the present disclosure, and these modifications and decorations should also be regarded as the protection scope of the embodiments of the present disclosure.
Claims (16)
1. An instruction synchronization apparatus, the apparatus comprising:
a counter, and a plurality of instruction queues;
each instruction queue of the plurality of instruction queues is used for storing instructions, the instructions comprise execution instructions and at least one of triggering instructions and waiting instructions;
the counter is used for responding to the received trigger instruction to carry out first adjustment on the counting value and responding to the received waiting instruction to carry out second adjustment on the counting value; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment;
and sending the instruction after the waiting instruction in one instruction queue under the condition that the counting value meets a preset value condition, wherein the preset value condition is determined based on the initial counting value of the counter, the adjustment mode of the first adjustment and the adjustment mode of the second adjustment.
2. The apparatus according to claim 1, wherein each instruction queue is configured to parse stored instructions, send parsed trigger instructions and wait instructions to the counter, and send parsed execution instructions to an execution unit.
3. The instruction synchronization apparatus according to claim 1 or 2, wherein one of the first adjustment and the second adjustment is adjusted by increasing the count value by a first preset step, and the other is adjusted by decreasing the count value by a second preset step;
the first preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues, and the second preset step size is determined based on the number of waiting queues related to the target synchronous event in the plurality of instruction queues.
4. The apparatus according to claim 3, wherein the trigger instruction carries the first preset step size, and the wait instruction carries the second preset step size.
5. The instruction synchronization apparatus according to claim 3 or 4, wherein the first preset step size is equal to a product of the number of waiting queues and a preset multiple, and the second preset step size is equal to a product of the number of waiting queues and the preset multiple.
6. The apparatus of any of claims 3 to 5, wherein the predetermined numerical condition is determined based on the initial count value, the first predetermined step size, the second predetermined step size, and a predetermined multiple.
7. The instruction synchronization apparatus of claim 6, wherein the predetermined numerical condition is: the counting value and the target counting value meet a preset numerical value relationship, and the target counting value is as follows:
n*m*a-1+k0；
wherein n is the first preset step length, m is the second preset step length, a is the preset multiple, and k0 is the initial counting value;
when the first adjustment is to increase the count value and the second adjustment is to decrease the count value, the numerical relationship is that the count value is greater than the target count value;
and when the first adjustment is to decrease the count value and the second adjustment is to increase the count value, the numerical relationship is that the count value is smaller than the target count value.
8. The instruction synchronization apparatus according to any one of claims 1 to 7, wherein the plurality of instruction queues include a waited queue and a wait queue; the waiting queue comprises a plurality of trigger instructions, each trigger instruction corresponds to a synchronous event, and the plurality of trigger instructions are used for adjusting the count value of the same counter;
a target waiting instruction is also included after the first trigger instruction in the waiting queue;
a target trigger instruction is also included after each first waiting instruction in the waiting queue;
the ith first trigger instruction in the to-be-waited queue and the ith first waiting instruction in the waiting queue are instructions corresponding to the ith synchronous event, and i is a positive integer.
9. The instruction synchronization apparatus according to any one of claims 1 to 8, wherein the number of counters is greater than 1; the trigger instruction and the waiting instruction included in each instruction queue comprise:
and the identification information of the counter is used for the instruction queue to send the trigger instruction and the waiting instruction which are included by the instruction queue to the corresponding counter.
10. The instruction synchronization apparatus according to any one of claims 1 to 9, further comprising:
and the execution unit is used for executing the received execution instruction.
11. The instruction synchronization apparatus according to claim 10, further comprising:
and the arbitration unit is used for sending the execution instruction sent by each instruction queue in the plurality of instruction queues to the execution unit according to the preset priority.
12. The instruction synchronization apparatus according to any one of claims 1 to 11, further comprising:
and the multiplexer is used for sending the instruction to a corresponding instruction queue in the plurality of instruction queues.
13. The apparatus according to any one of claims 1 to 12, wherein the trigger instruction and the wait instruction each comprise:
and the identification information of the instruction queue is used for the multiplexer to send the trigger instruction and the waiting instruction to the corresponding instruction queue.
14. A chip, wherein the chip comprises:
instruction synchronization apparatus according to any one of claims 1 to 13.
15. A computer device comprising the chip of claim 14.
16. A data processing method applied to the instruction synchronization apparatus according to any one of claims 1 to 13, the method comprising:
each instruction queue of the plurality of instruction queues stores instructions, the instructions including execution instructions and at least one of trigger instructions and wait instructions;
the counter performs first adjustment on the count value in response to receiving the trigger instruction, and performs second adjustment on the count value in response to receiving the waiting instruction; the adjustment mode of the first adjustment is different from the adjustment mode of the second adjustment;
and each instruction queue sends the instruction behind the waiting instruction in the queue under the condition that the counting value meets a preset value condition, wherein the preset value condition is determined based on the initial counting value of the counter, the adjustment mode of the first adjustment and the adjustment mode of the second adjustment.
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| CN202111652996.0A CN114265717B (en) | 2021-12-30 | 2021-12-30 | Instruction synchronization device, chip and computer equipment, and data processing method |
| PCT/CN2022/124511 WO2023124370A1 (en) | 2021-12-30 | 2022-10-11 | Instruction synchronization apparatus, chip, computer device, and data processing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115145638A (en) * | 2022-06-30 | 2022-10-04 | 上海阵量智能科技有限公司 | Command distributor, command distribution method and system, chip, board card and equipment |
| CN115390569A (en) * | 2022-08-04 | 2022-11-25 | 上海布鲁可积木科技有限公司 | Instruction synchronous processing method and system in hunting toy |
| WO2023124370A1 (en) * | 2021-12-30 | 2023-07-06 | 上海商汤智能科技有限公司 | Instruction synchronization apparatus, chip, computer device, and data processing method |
| CN117112025A (en) * | 2023-10-18 | 2023-11-24 | 北京开源芯片研究院 | Instruction execution methods, devices, equipment and storage media of processing components |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103348318A (en) * | 2011-02-07 | 2013-10-09 | Arm有限公司 | Controlling the execution of adjacent instructions that are dependent upon a same data condition |
| US20170308384A1 (en) * | 2016-04-22 | 2017-10-26 | Microsoft Technology Licensing, Llc | Processor with instruction lookahead issue logic |
| CN110543395A (en) * | 2019-08-30 | 2019-12-06 | 北京中科寒武纪科技有限公司 | verification method, verification device and related product |
| CN110659070A (en) * | 2018-06-29 | 2020-01-07 | 赛灵思公司 | High-parallelism computing system and instruction scheduling method thereof |
| CN113138802A (en) * | 2021-04-29 | 2021-07-20 | 上海阵量智能科技有限公司 | Command distribution device, method, chip, computer equipment and storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6581089B1 (en) * | 1998-04-16 | 2003-06-17 | Sony Corporation | Parallel processing apparatus and method of the same |
| JP2011209905A (en) * | 2010-03-29 | 2011-10-20 | Sony Corp | Instruction fetch apparatus, processor and program counter addition control method |
| CN113778914B (en) * | 2020-06-09 | 2024-06-18 | 华为技术有限公司 | Apparatus, method, and computing device for performing data processing |
| CN113138801B (en) * | 2021-04-29 | 2023-08-04 | 上海阵量智能科技有限公司 | Command distribution device, method, chip, computer device and storage medium |
| CN114265717B (en) * | 2021-12-30 | 2025-09-16 | 上海阵量智能科技有限公司 | Instruction synchronization device, chip and computer equipment, and data processing method |
-
2021
- 2021-12-30 CN CN202111652996.0A patent/CN114265717B/en active Active
-
2022
- 2022-10-11 WO PCT/CN2022/124511 patent/WO2023124370A1/en not_active Ceased
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103348318A (en) * | 2011-02-07 | 2013-10-09 | Arm有限公司 | Controlling the execution of adjacent instructions that are dependent upon a same data condition |
| US20170308384A1 (en) * | 2016-04-22 | 2017-10-26 | Microsoft Technology Licensing, Llc | Processor with instruction lookahead issue logic |
| CN110659070A (en) * | 2018-06-29 | 2020-01-07 | 赛灵思公司 | High-parallelism computing system and instruction scheduling method thereof |
| CN110543395A (en) * | 2019-08-30 | 2019-12-06 | 北京中科寒武纪科技有限公司 | verification method, verification device and related product |
| CN113138802A (en) * | 2021-04-29 | 2021-07-20 | 上海阵量智能科技有限公司 | Command distribution device, method, chip, computer equipment and storage medium |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023124370A1 (en) * | 2021-12-30 | 2023-07-06 | 上海商汤智能科技有限公司 | Instruction synchronization apparatus, chip, computer device, and data processing method |
| CN115145638A (en) * | 2022-06-30 | 2022-10-04 | 上海阵量智能科技有限公司 | Command distributor, command distribution method and system, chip, board card and equipment |
| CN115145638B (en) * | 2022-06-30 | 2025-01-07 | 上海阵量智能科技有限公司 | Command distributor, command distribution method and system, chip, board, device |
| CN115390569A (en) * | 2022-08-04 | 2022-11-25 | 上海布鲁可积木科技有限公司 | Instruction synchronous processing method and system in hunting toy |
| CN115390569B (en) * | 2022-08-04 | 2024-10-29 | 上海布鲁可积木科技有限公司 | Method and system for synchronously processing instructions in hunting toy |
| CN117112025A (en) * | 2023-10-18 | 2023-11-24 | 北京开源芯片研究院 | Instruction execution methods, devices, equipment and storage media of processing components |
| CN117112025B (en) * | 2023-10-18 | 2023-12-22 | 北京开源芯片研究院 | Instruction execution methods, devices, equipment and storage media of processing components |
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|---|---|
| WO2023124370A1 (en) | 2023-07-06 |
| CN114265717B (en) | 2025-09-16 |
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