CN114185843A - Network-on-chip interface for distributed data fusion system - Google Patents

Network-on-chip interface for distributed data fusion system Download PDF

Info

Publication number
CN114185843A
CN114185843A CN202111446634.6A CN202111446634A CN114185843A CN 114185843 A CN114185843 A CN 114185843A CN 202111446634 A CN202111446634 A CN 202111446634A CN 114185843 A CN114185843 A CN 114185843A
Authority
CN
China
Prior art keywords
data
network
fusion
sensor
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111446634.6A
Other languages
Chinese (zh)
Inventor
姜书艳
何甜
黄乐天
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze River Delta Research Institute of UESTC Huzhou
Original Assignee
Yangtze River Delta Research Institute of UESTC Huzhou
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze River Delta Research Institute of UESTC Huzhou filed Critical Yangtze River Delta Research Institute of UESTC Huzhou
Priority to CN202111446634.6A priority Critical patent/CN114185843A/en
Publication of CN114185843A publication Critical patent/CN114185843A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825Globally asynchronous, locally synchronous, e.g. network on chip
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306Intercommunication techniques
    • G06F15/17312Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

The invention discloses a network-on-chip interface for a distributed data fusion system, which comprises a programmable module, a cache queue module and a packaging module, wherein the programmable module is sequentially connected with the cache queue module and the packaging module and is used for receiving and calculating transmission data of an external sensor node and transmitting a data packet to a network-on-chip through the packaging module, or receiving calculated return data from the network-on-chip and carrying out secondary processing on the received return data. The buffer queue module is used for storing current calculation data of the programmable module or original transmission data of the external sensor node. The interface is responsible for connecting the sensor and the network on chip, and can also perform preliminary processing on data acquired by the sensor. The method is beneficial to relieving the transmission and calculation burden of data fusion, and can ensure higher real-time performance of data processing while saving communication resources.

Description

Network-on-chip interface for distributed data fusion system
Technical Field
The invention relates to the field of sensor data interfaces, in particular to a network-on-chip interface for a distributed data fusion system.
Background
The traditional detection device adopts a 'calculation separation' mode to fuse or integrate data collected by the sensors, namely, transmission and processing are two mutually independent processes, and the data are not processed in the process of being transmitted to a fusion center. This mode will greatly increase the bandwidth pressure of the data transmission network, especially the convergence layer in the network, with the increase of the number of sensors, and also cannot respond in real time due to the increase of data processing delay caused by the accumulation of a large amount of data.
In order to alleviate the above problems, an intra-network computing method may be adopted, that is, a task or a part of tasks of the data fusion center are scheduled to a node in the network on chip for execution. But the network on chip has a limited number and variety of computational tasks that it can undertake due to the limited resources available for computation. Meanwhile, the existing in-network computing implementation scheme is bound with hardware. When a migration task is needed or a data stream transmission path is changed, application codes need to be rewritten, and rapid migration cannot be achieved. In addition, the economic cost of computing implementation within a network that is tightly coupled to the hardware is also high. Therefore, an interface with a data processing function can be designed to perform complex computation which is inconvenient to implement in a network on chip during data fusion.
Disclosure of Invention
In view of the above-mentioned deficiencies in the prior art, the present invention provides a network-on-chip interface for a distributed data fusion system.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
a network-on-chip interface for a distributed data fusion system includes a programmable module, a buffer queue module, and a packing module,
the programmable module is sequentially connected with the cache queue module and the packaging module and is used for receiving and calculating transmission data of external sensor nodes and transmitting data packets to the network on chip through the packaging module, or receiving calculated return data from the network on chip and carrying out secondary processing on the received return data;
the buffer queue module is used for storing current calculation data of the programmable module or original transmission data of the external sensor node.
Further, the programmable module includes multiple parallel computing sequences, and each parallel computing sequence is input single sensor data or a last fusion result received from the network interface.
Further, the specific calculation process of the programmable module is as follows:
a1, squaring the result of subtraction of the data collected by the sensor and the last fusion result, and then multiplying by a coefficient 1-alpha;
a2, adding the result of A1 and the result of the multiplication of the last variance by the coefficient alpha to obtain the current quasi variance;
a3, calculating the reciprocal of the current quasi variance.
Further, a packing module in the network-on-chip interface sends the current reciprocal result of the quasi-variance of the sensor connected with the interface to the network-on-chip, the network-on-chip calculates the reciprocal sum of the current quasi-variance of a plurality of parallel calculation sequences, and the result is returned to each network-on-chip interface through the router.
Furthermore, each network-on-chip interface takes out the temporarily stored sensor original data and the quasi-reciprocal variance of the current sensor from the cache queue, and performs data fusion calculation by combining the sum of the quasi-reciprocal variances of the current sensor data received and calculated from the network-on-chip.
Further, the specific manner of the data fusion calculation is as follows:
b1, calculating to obtain respective fusion weight by dividing the sum of the total pseudo-variances by the pseudo-variances of each sensor;
and B2, multiplying the weight by the sensor to acquire a raw data value, and sending the result to the network on chip by the packaging module.
7. The network-on-chip interface for a distributed data fusion system of claim 6, wherein the final result is expressed as:
Figure BDA0003384342560000031
wherein,
Figure BDA0003384342560000032
alpha is a memory attenuation factor and reflects the attenuation speed of the influence intensity of old data on the current fusion result; x is the number ofs(k) The original data collected by the s sensor in the k fusion process;
Figure BDA0003384342560000033
the variance of data acquired by the s sensor in the k-1 fusion process; xf(k-1) is a final fusion result value of the k-1 st fusion sensor data;
Figure BDA0003384342560000034
the variance estimation value of data collected by the s-th sensor in the k-th fusion process is also called as the standard variance; xs(k) Is the fusion contribution value of the s-th sensor data.
The invention has the following beneficial effects:
1) in the data fusion process, complicated calculation which is difficult to realize only by computing resources in the network-on-chip is allocated to the network interface, so that the computing pressure of the network is reduced, the number of computing devices in the network can be reduced, and the overall efficiency is improved.
2) The original data is processed primarily at the network interface, so that the transmission quantity of the network can be reduced, the communication pressure is relieved, and the power consumption of the system is reduced.
3) The flexibility of the system is improved due to the use of programmable devices within the network interface. The interface can be used for completing more data processing functions and realizing different data fusion algorithms in the network on chip.
Drawings
Fig. 1 is a schematic diagram of a network-on-chip interface structure for a distributed data fusion system according to the present invention.
Fig. 2 is a data flow diagram of an adaptive weighted fusion algorithm according to an embodiment of the present invention.
Fig. 3 is a process of the network interface executing the first operation according to the embodiment of the present invention.
Fig. 4 is a process of the network interface performing the second operation according to the embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
A network-on-chip interface for a distributed data fusion system, as shown in fig. 1, includes a programmable module, a buffer queue module, and a packing module, wherein,
the programmable module is sequentially connected with the cache queue module and the packaging module and is used for receiving and calculating transmission data of external sensor nodes and transmitting data packets to the network on chip through the packaging module, or receiving calculated return data from the network on chip and carrying out secondary processing on the received return data.
The buffer queue module is used for storing current calculation data of the programmable module or original transmission data of the external sensor node.
The interface mainly comprises a programmable module, a buffer queue and a packaging module. The sensors send the acquired data to the interface (NI) and the programmable device is responsible for processing the raw data according to preset steps. And then the programmable device sends the result of the data preliminary processing to a buffer queue for temporary storage or continuously forwards the result to a packaging module. And the packing module packs data required by the computing process in the network on chip and injects the data into the network on chip, and the network on chip is handed to execute the next computing task.
Since the network on chip is calculated, data may be sent back to each node device connected to the sensor. When the device node interfaces receive data sent by the network on chip, the interfaces start the programmable device to perform secondary processing on the data again. In addition, the interface may also receive data returned from the host, and complete the operation required for data fusion by combining the data taken out from the cache queue. The interface needs to inject the result of data processing into the network on chip according to a set step each time.
In the embodiment, the data fusion algorithm adopted by the invention firstly estimates the variance of the sensor by using the standard deviation of the data fusion value measured by the sensor based on the statistical data, and then introduces alpha-memory attenuation factor to improve the algorithm so as to reduce the adverse effect brought by the old data. The specific fusion algorithm formula is shown in formula (1) to formula (3).
Figure BDA0003384342560000051
Figure BDA0003384342560000052
Figure BDA0003384342560000053
Wherein alpha is a memory attenuation factor and reflects the attenuation speed of the influence intensity of old data on the current fusion result; x is the number ofs(k) The original data collected by the s sensor in the k fusion process;
Figure BDA0003384342560000054
the variance of data acquired by the s sensor in the k-1 fusion process; xf(k-1) is a final fusion result value of the k-1 st fusion sensor data;
Figure BDA0003384342560000055
the variance estimation value of data collected by the s-th sensor in the k-th fusion process is also called as the standard variance; xs(k) The fusion contribution value of the s-th sensor data in the k-th fusion process is obtained. Xf(k) The final fusion result value of the kth fusion sensor data is obtained; and n is the total number of sensors.
Due to the specific bottom hardware structure and the data processing mode of the network on chip, the algorithm is more favorably mapped to the network on chip to be realized by using the form representation algorithm of the data flow graph. According to the data fusion algorithm, a data flow graph as shown in fig. 3 can be obtained.
The data flow diagram is preliminarily observed, and four basic operations of addition, subtraction, multiplication and division are provided in the data flow diagram. And then carefully observing the data flow direction, the computing task can be distributed to the equipment network interface connected with the sensor and the internal computing resource of the on-chip network to realize:
the first half of the operations are all performed by a single sensor data as shown in the first black box at the left side of fig. 2, and other sensor data are not involved, so that the operations can be allocated to a network interface for execution. After the network interface receives the last fusion result sent from the host, the operation in the first black frame can be executed, and the specific operation process is as follows: firstly, squaring a result obtained by subtracting a last fusion result from data acquired by a sensor, and then multiplying the result by a coefficient 1-alpha; secondly, adding the result obtained by multiplying the previous variance by the coefficient alpha to obtain the current quasi variance; and finally, calculating the reciprocal of the quasi variance of the current time. The obtained result and the original data collected by the sensor need to be transmitted to a buffer queue for temporary storage, and then the buffer queue transmits the reciprocal of the quasi variance to a packing module for packing. And finally, the data packet is injected into the network on chip by the packaging module so as to carry out the following operation. The specific implementation of the network interface is shown in fig. 3.
The operation of summing the inverse variances of the plurality of sensor data in the second black box of the data flow diagram of fig. 2 may be performed using computational resources within the network on chip. After the execution is finished, the network on chip will send the result back to each network interface through the router. The network interface may then begin performing the operations of the third black box in fig. 2. The network interface firstly takes out the original data value temporarily stored before and the inverse quasi-variance of the sensor from an internal buffer queue, and then carries out the following operations: firstly, dividing the reciprocal of variance of each sensor by the sum of the reciprocal of total variance to obtain respective fusion weight; secondly, multiplying the weight by the value of the original data collected by the sensor. And after the network interface finishes the operation, the result is sent to a packaging module for packaging and then the data packet is injected into the network on chip. And finally, executing the operation in the fourth black frame by the network on chip, namely summing the results obtained by the calculation of each network interface to obtain the final result of the data fusion.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (7)

1. The network-on-chip interface for the distributed data fusion system is characterized by comprising a programmable module, a buffer queue module and a packaging module, wherein,
the programmable module is sequentially connected with the cache queue module and the packaging module and is used for receiving and calculating transmission data of external sensor nodes and transmitting data packets to the network on chip through the packaging module, or receiving calculated return data from the network on chip and carrying out secondary processing on the received return data;
the buffer queue module is used for storing current calculation data of the programmable module or original transmission data of the external sensor node.
2. The network-on-chip interface for a distributed data fusion system of claim 1, wherein the programmable module comprises a plurality of sets of parallel computing sequences, each set of parallel computing sequences being respectively an input single sensor data or a last fusion result received from the network interface.
3. The network-on-chip interface for a distributed data fusion system according to claim 2, wherein the specific calculation process of the programmable module is as follows:
a1, squaring the result of subtraction of the data collected by the sensor and the last fusion result, and then multiplying by a coefficient 1-alpha;
a2, adding the result of A1 and the result of the multiplication of the last variance by the coefficient alpha to obtain the current quasi variance;
a3, calculating the reciprocal of the current quasi variance.
4. The network-on-chip interface for the distributed data fusion system according to claim 3, wherein a packing module in the network-on-chip interface sends the current reciprocal result of the quasi variance of the sensor connected to the interface to the network-on-chip, and the network-on-chip calculates the reciprocal sum of the current quasi variance of a plurality of parallel calculation sequences and returns the result to each network-on-chip interface through a router.
5. The network-on-chip interface for a distributed data fusion system according to claim 4, wherein each network-on-chip interface takes out the temporarily stored sensor raw data and the inverse quasi-variance of the current sensor from the buffer queue, and performs data fusion calculation by combining a sum of the inverse quasi-variances of the current sensor data received from the network-on-chip after calculation.
6. The network-on-chip interface for a distributed data fusion system according to claim 5, wherein the data fusion calculation is performed by:
b1, calculating to obtain respective fusion weight by dividing the sum of the total pseudo-variances by the pseudo-variances of each sensor;
b2, multiplying the weight by the original data value acquired by the sensor;
and B3, summing the results obtained by the calculation of each network interface to obtain the final result of the data fusion.
7. The network-on-chip interface for a distributed data fusion system of claim 6, wherein the final result is expressed as:
Figure FDA0003384342550000021
Figure FDA0003384342550000022
wherein,
Figure FDA0003384342550000023
alpha is a memory attenuation factor; x is the number ofs(k) The original data collected by the s sensor in the k fusion process;
Figure FDA0003384342550000024
the variance of data acquired by the s sensor in the k-1 fusion process; xf(k-1) is a final fusion result value of the k-1 st fusion sensor data;
Figure FDA0003384342550000025
the variance estimation value of data collected by the s sensor in the k fusion process; xs(k) The fusion contribution value of the s-th sensor data in the k-th fusion process is obtained; xf(k) Is the final fusion result value of the k-th time fusion sensor data.
CN202111446634.6A 2021-11-30 2021-11-30 Network-on-chip interface for distributed data fusion system Pending CN114185843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111446634.6A CN114185843A (en) 2021-11-30 2021-11-30 Network-on-chip interface for distributed data fusion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111446634.6A CN114185843A (en) 2021-11-30 2021-11-30 Network-on-chip interface for distributed data fusion system

Publications (1)

Publication Number Publication Date
CN114185843A true CN114185843A (en) 2022-03-15

Family

ID=80603116

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111446634.6A Pending CN114185843A (en) 2021-11-30 2021-11-30 Network-on-chip interface for distributed data fusion system

Country Status (1)

Country Link
CN (1) CN114185843A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101141339A (en) * 2007-02-09 2008-03-12 江苏怡丰通信设备有限公司 Embedded SoC chip based wireless network industry monitoring management system
US20200364303A1 (en) * 2019-05-15 2020-11-19 Nvidia Corporation Grammar transfer using one or more neural networks
CN113190291A (en) * 2021-05-25 2021-07-30 电子科技大学 Configurable protocol conversion system and method based on network-on-chip data acquisition

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101141339A (en) * 2007-02-09 2008-03-12 江苏怡丰通信设备有限公司 Embedded SoC chip based wireless network industry monitoring management system
US20200364303A1 (en) * 2019-05-15 2020-11-19 Nvidia Corporation Grammar transfer using one or more neural networks
CN113190291A (en) * 2021-05-25 2021-07-30 电子科技大学 Configurable protocol conversion system and method based on network-on-chip data acquisition

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
单海蛟 等: ""多传感器自主跟踪中的数据融合方法"", 《液晶与显示》, 31 August 2016 (2016-08-31), pages 801 - 809 *
单海蛟 等: ""多传感器自主跟踪中的数据融合方法"", 《液晶与显示》, pages 801 - 809 *

Similar Documents

Publication Publication Date Title
CN106294897B (en) Implementation method suitable for electromagnetic transient multi-time scale real-time simulation interface
JP6981329B2 (en) Distributed deep learning system
CN109254946B (en) Image feature extraction method, device and equipment and readable storage medium
CN104899182A (en) Matrix multiplication acceleration method for supporting variable blocks
CN103248540B (en) Based on FPGA network traffics generation systems and the method for multi-fractal wavelet model
CN111260076B (en) Block chain-based edge node training method, block chain and storage medium
CN108304256A (en) The method for scheduling task and device of low overhead in a kind of edge calculations
CN115511086B (en) Distributed reasoning deployment system for oversized model
CN114185843A (en) Network-on-chip interface for distributed data fusion system
CN112395549A (en) Reconfigurable matrix multiplication accelerating system for matrix multiplication intensive algorithm
CN109981487B (en) Data scheduling method and device, electronic equipment and readable storage medium
Zhou et al. DRL-Based Workload Allocation for Distributed Coded Machine Learning
CN109450684B (en) Method and device for expanding physical node capacity of network slicing system
CN104933110B (en) A kind of data prefetching method based on MapReduce
CN109783575A (en) Data processing method and device
CN109246331A (en) A kind of method for processing video frequency and system
CN112001571B (en) Markov chain-based block chain performance analysis method and device
CN103986744B (en) Throughput-based file parallel transmission method
CN106789440A (en) A kind of IP bags packet header detection method and device
CN114168315A (en) Multi-core-based message processing method and device, electronic equipment and storage medium
CN114546645A (en) Data processing method and device based on secret sharing
CN106302231A (en) The method and device of traffic queue shaping
CN113255881B (en) Homomorphic encryption neural network framework of PS and PL cooperative architecture and inference method
CN114185842B (en) Distributed data level fusion system and method based on network on chip
CN109784226A (en) Face snap method and relevant apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination