CN114172523A - Segmented decoding method and system based on Viterbi decoder - Google Patents
Segmented decoding method and system based on Viterbi decoder Download PDFInfo
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- CN114172523A CN114172523A CN202111340111.3A CN202111340111A CN114172523A CN 114172523 A CN114172523 A CN 114172523A CN 202111340111 A CN202111340111 A CN 202111340111A CN 114172523 A CN114172523 A CN 114172523A
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Abstract
The invention relates to a segmented decoding method and a system based on a Viterbi decoder, wherein the method comprises the following steps: s1, sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded; s2, sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding by the Viterbi decoder to obtain a plurality of first decoded data; and S3, splicing the first decoded data according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data. The invention carries out segmented decoding on the data to be decoded by the Viterbi decoder, reduces the hardware storage resource and the software resource of the system and improves the decoding efficiency without changing the algorithm kernel.
Description
Technical Field
The invention relates to the field of GNSS satellite communication, in particular to a segmented decoding method and a segmented decoding system based on a Viterbi decoder.
Background
The Viterbi decoder is a type of decoder used to use convolutional coding in satellite navigation data modulation. In the conventional decoding process, after storing soft bit information of a certain length, decoding is started, usually in units of one frame data. For decoding satellite signals with ultra-long frames, in a traditional Viterbi decoding algorithm, a relatively large storage space is needed to store soft information for decoding, hardware storage resources can be greatly wasted, and meanwhile, a system is required to carry input data and output data back and forth during each decoding, so that software resources are wasted.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a segment decoding method and system based on a Viterbi decoder.
The invention discloses a segment decoding method based on a Viterbi decoder, which comprises the following technical scheme:
s1, sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
s2, sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding by the Viterbi decoder to obtain a plurality of first decoded data;
and S3, splicing the first decoded data according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data.
The segmented decoding method based on the Viterbi decoder has the following beneficial effects:
according to the invention, the preset decoding length is utilized to segment and intercept the first data to be decoded in sequence to obtain a plurality of second data to be decoded, each second data to be decoded is transmitted to the Viterbi decoder in sequence and decoded by the Viterbi decoder to obtain a plurality of first data to be decoded, and the plurality of first data to be decoded are spliced according to the sequence of segmenting and intercepting the first data to be decoded in sequence to obtain the final decoded data.
Based on the above scheme, the segmented decoding method based on the Viterbi decoder according to the present invention may be further improved as follows.
Further, before the S1, the method further includes:
and acquiring the first data to be decoded from an SRAM memory.
The beneficial effect of adopting the further scheme is that: when decoding is needed, the data to be decoded can be extracted and transmitted conveniently.
Further, before the S2, the method further includes:
storing all of the second data to be decoded in the SRAM memory;
the S2 specifically includes:
s21, acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
s22, sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and S23, decoding each received second data to be decoded in sequence through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
The beneficial effect of adopting the further scheme is that: and the data to be decoded is transmitted to a Viterbi decoder for decoding through the base address of each section of data to be decoded in the SRAM, so that the decoding efficiency is improved.
Further, before the S3, the method further includes:
transmitting a plurality of the first decoded data to the SRAM memory.
The beneficial effect of adopting the further scheme is that: and the decoded data after each decoding section is finished is transmitted back to the SRAM, so that the storage of the decoded data is promoted.
Further, before the S1, the method further includes:
and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
The beneficial effect of adopting the further scheme is that: the decoding scheme can be dynamically modified according to the requirements through the decoder parameters set by the user, so as to meet different user requirements.
The invention discloses a segmented decoding system based on a Viterbi decoder, which comprises the following technical scheme:
the method comprises the following steps: the system comprises a preprocessing module, an operation module and a processing module;
the preprocessing module is used for: sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
the operation module is used for: sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding through the Viterbi decoder to obtain a plurality of first decoded data;
the processing module is used for: and splicing the plurality of first decoded data according to the sequence of sequentially segmenting and intercepting the first to-be-decoded data to obtain final decoded data.
The segmented decoding system based on the Viterbi decoder has the following beneficial effects:
according to the invention, the preset decoding length is utilized to segment and intercept the first data to be decoded in sequence to obtain a plurality of second data to be decoded, each second data to be decoded is transmitted to the Viterbi decoder in sequence and decoded by the Viterbi decoder to obtain a plurality of first data to be decoded, and the plurality of first data to be decoded are spliced according to the sequence of segmenting and intercepting the first data to be decoded in sequence to obtain the final decoded data.
Based on the above scheme, the segmented decoding system based on the Viterbi decoder according to the present invention may be further improved as follows.
Further, the preprocessing module is further configured to: and acquiring the first data to be decoded from an SRAM memory.
The beneficial effect of adopting the further scheme is that: when decoding is needed, the data to be decoded can be extracted and transmitted conveniently.
Further, the operation module is further configured to: storing all of the second data to be decoded in the SRAM memory;
the operation module is specifically configured to:
acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and decoding each received second data to be decoded sequentially through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
The beneficial effect of adopting the further scheme is that: and the data to be decoded is transmitted to a Viterbi decoder for decoding through the base address of each section of data to be decoded in the SRAM, so that the decoding efficiency is improved.
Further, the processing module is further configured to:
transmitting a plurality of the first decoded data to the SRAM memory.
The beneficial effect of adopting the further scheme is that: and the decoded data after each decoding section is finished is transmitted back to the SRAM, so that the storage of the decoded data is promoted.
Further, still include: a configuration module;
the configuration module is configured to: and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
The beneficial effect of adopting the further scheme is that: the decoding scheme can be dynamically modified according to the requirements through the decoder parameters set by the user, so as to meet different user requirements.
Drawings
Fig. 1 is a flowchart illustrating a segment decoding method based on a Viterbi decoder according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of S2 in a segment decoding method based on a Viterbi decoder according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a segment decoding system based on a Viterbi decoder according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a segment decoding method based on a Viterbi decoder according to an embodiment of the present invention includes the following steps:
s1, sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
s2, sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding by the Viterbi decoder to obtain a plurality of first decoded data;
and S3, splicing the first decoded data according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data.
In this embodiment, the preset decoding length is used to sequentially segment and intercept the first data to be decoded to obtain a plurality of second data to be decoded, each second data to be decoded is sequentially transmitted to the Viterbi decoder, and is decoded by the Viterbi decoder to obtain a plurality of first decoded data, and the plurality of first decoded data are spliced according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data.
Specifically, in S1, first, a value of a preset decoding length is determined, and then the first length to be decoded and the size of the preset decoding length are determined, if the first length to be decoded is greater than the preset decoding length, the decoding data of the preset decoding length is intercepted from the first length to be decoded as a second data to be decoded, and the remaining first length to be decoded is updated, until the last second data to be decoded is intercepted when the first length to be decoded is less than or equal to the preset decoding length; at this time, a plurality of second data to be decoded are obtained.
In S2, each piece of second data to be decoded segmented in S1 is sequentially transferred from the memory to the Viterbi decoder for decoding, and after each segment of decoding is completed, each piece of first data to be decoded is transmitted back to the memory, and the above operations are repeated until all the second data to be decoded are decoded.
In S3, all the first decoded data after decoding are arranged in the order before the segmentation, and the final decoded data is obtained.
For example, taking Viterbi decoding of L Band signal data as an example, one frame of data 8192sym, the conventional decoding scheme requires a soft information storage ram 8K byte, decoding outputs 4096 bits, requires ram 512byte, path metric and survivor path storage ram 512 byte. The algorithm flow needs the cpu to load all 8K byte data of a frame of data in the storage area to the soft information storage ram, the cpu needs to read corresponding data from the storage area first, then in executing write operation to the internal ram of the Viterbi decoder, the decoding result also needs the cpu to read the internal ram of the Viterbi decoder first, in writing to the system storage area, two kinds of read-write operations need to be executed for each decoding, that is, the efficiency is wasted, and the software resource is wasted.
By adopting the method of the embodiment, the soft information storage ram can be reduced to 1K byte, the decoding result storage ram 64byte, the path metric and survival path storage ram 512byte, and the controller automatically divides 8192sym in the storage area into 8 sections for decoding. The scheme provided by the embodiment is that in the process of carrying soft information from a storage area to a soft information storage ram, 1K byte is carried each time, 8 times of decoding is carried, and 8 times of 8K byte is carried, compared with the traditional scheme, the operation of a system CPU is reduced, and when input data and output data are carried at each time, once reading or writing is also reduced.
Preferably, before the S1, the method further includes:
and acquiring the first data to be decoded from an SRAM memory.
Specifically, the storage area is stored by adopting an SRAM (static random access memory), so that when decoding is needed, data to be decoded can be extracted and transmitted conveniently.
Preferably, before the S2, the method further includes:
storing all of the second data to be decoded in the SRAM memory;
the S2 specifically includes:
s21, acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
s22, sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and S23, decoding each received second data to be decoded in sequence through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
Here, the base address is understood as a base address, which is a calculation reference of the relative offset.
Specifically, as shown in fig. 2, according to the actual decoding length of each segment and the base address of the input/output data in the SRAM memory, the controller automatically moves the data from the SRAM memory to the Viterbi internal storage area, and starts the ACS unit of the decoder core to decode, thereby improving the decoding efficiency.
Preferably, before the S3, the method further includes:
transmitting a plurality of the first decoded data to the SRAM memory.
Specifically, the decoded data after each decoding section is finished are transmitted back to the SRAM, so that the occupation rate of hardware is saved, and the storage of the decoded data is improved.
Preferably, before the S1, the method further includes:
and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
The RAM parameters for configuring the Viterbi decoder are equivalent to initializing the decoder and comprise initialization state, rolling machine coding polynomial length, decoding frame length and other parameters, and the decoding frame length is a preset decoding length.
Specifically, the decoding scheme can be dynamically modified according to the requirements through decoder parameters set by the user, so as to meet different user requirements. For example, the RAM of a Viterbi decoder can be reduced to 1K byte.
In the above embodiments, although the steps are numbered as S1, S2, etc., those skilled in the art may adjust the execution sequence of S1, S2, etc. according to the actual situation, which is also within the protection scope of the present invention, and it is understood that some embodiments may include some or all of the above embodiments.
As shown in fig. 3, a segment decoding system 200 based on a Viterbi decoder according to an embodiment of the present invention includes: a preprocessing module 210, an operation module 220, and a processing module 230;
the preprocessing module 210 is configured to: sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
the operation module 220 is configured to: sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding through the Viterbi decoder to obtain a plurality of first decoded data;
the processing module 230 is configured to: and splicing the plurality of first decoded data according to the sequence of sequentially segmenting and intercepting the first to-be-decoded data to obtain final decoded data.
In this embodiment, the preset decoding length is used to sequentially segment and intercept the first data to be decoded to obtain a plurality of second data to be decoded, each second data to be decoded is sequentially transmitted to the Viterbi decoder, and the Viterbi decoder decodes the first data to obtain a plurality of first decoded data, and the plurality of first decoded data are spliced according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data.
Preferably, the preprocessing module 210 is further configured to: and acquiring the first data to be decoded from an SRAM memory.
Preferably, the operation module 220 is further configured to: storing all of the second data to be decoded in the SRAM memory;
the operation module 220 is specifically configured to:
acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and decoding each received second data to be decoded sequentially through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
Preferably, the processing module 230 is further configured to:
transmitting a plurality of the first decoded data to the SRAM memory.
Preferably, the method further comprises the following steps: a configuration module;
the configuration module is configured to: and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
The above steps for realizing the corresponding functions of each parameter and each module in the Viterbi-decoder-based segmented decoding system 200 according to the present invention refer to the above parameters and steps in the embodiment of the Viterbi-decoder-based segmented decoding method, which are not described herein again.
An embodiment of the present invention provides a storage medium, including: the storage medium stores instructions, and when the instructions are read by the computer, the computer is caused to execute the steps of the Viterbi-decoder-based segment decoding method according to any one of the above embodiments, which may specifically refer to the parameters and the steps in the foregoing Viterbi-decoder-based segment decoding method, and details are not described here.
Computer storage media such as: flash disks, portable hard disks, and the like.
An electronic device provided in an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the computer program is executed by the processor, so that the computer executes the steps of the segment decoding method based on the Viterbi decoder according to any one of the above embodiments, and specifically, reference may be made to each parameter and step in the foregoing embodiment of the segment decoding method based on the Viterbi decoder, which is not described herein again.
Those skilled in the art will appreciate that the present invention may be embodied as methods, apparatus, storage media and electronic devices.
Thus, the present invention may be embodied in the form of: may be embodied entirely in hardware, entirely in software (including firmware, resident software, micro-code, etc.) or in a combination of hardware and software, and may be referred to herein generally as a "circuit," module "or" system. Furthermore, in some embodiments, the invention may also be embodied in the form of a computer program product in one or more computer-readable media having computer-readable program code embodied in the medium. Any combination of one or more computer-readable media may be employed. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. For example, a computer readable storage medium may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A segment decoding method based on a Viterbi decoder is characterized by comprising the following steps:
s1, sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
s2, sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding by the Viterbi decoder to obtain a plurality of first decoded data;
and S3, splicing the first decoded data according to the sequence of sequentially segmenting and intercepting the first data to be decoded to obtain final decoded data.
2. The method of claim 1, wherein before the step S1, the method further comprises:
and acquiring the first data to be decoded from an SRAM memory.
3. The method of claim 2, further comprising, before the step S2:
storing all of the second data to be decoded in the SRAM memory;
the S2 specifically includes:
s21, acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
s22, sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and S23, decoding each received second data to be decoded in sequence through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
4. The method of claim 3, further comprising, before the step of S3:
transmitting a plurality of the first decoded data to the SRAM memory.
5. A segmented decoding method based on Viterbi decoder according to any of claims 1 to 4 wherein, before the step S1, further comprising:
and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
6. A segmented decoding system based on Viterbi decoders, comprising: the system comprises a preprocessing module, an operation module and a processing module;
the preprocessing module is used for: sequentially segmenting and intercepting the first data to be decoded by using a preset decoding length to obtain a plurality of second data to be decoded;
the operation module is used for: sequentially transmitting each second data to be decoded to a Viterbi decoder, and decoding through the Viterbi decoder to obtain a plurality of first decoded data;
the processing module is used for: and splicing the plurality of first decoded data according to the sequence of sequentially segmenting and intercepting the first to-be-decoded data to obtain final decoded data.
7. The segmented decoding system of claim 6, wherein the preprocessing module is further configured to: and acquiring the first data to be decoded from an SRAM memory.
8. The Viterbi-decoder-based segment decoding system of claim 7, wherein the execution module is further configured to: storing all of the second data to be decoded in the SRAM memory;
the operation module is specifically configured to:
acquiring a base address corresponding to each second data to be decoded in the SRAM memory;
sequentially transmitting the second data to be decoded corresponding to each base address to the Viterbi decoder;
and decoding each received second data to be decoded sequentially through an ACS unit of the Viterbi decoder to obtain a plurality of first decoded data.
9. The Viterbi-decoder-based segment decoding system of claim 8, wherein the processing module is further configured to:
transmitting a plurality of the first decoded data to the SRAM memory.
10. A Viterbi decoder based segmented decoding system according to any one of claims 6 to 9, further comprising: a configuration module;
the configuration module is configured to: and configuring parameters of the RAM of the Viterbi decoder to obtain the preset decoding length.
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