CN114123095A - Circuit and method for controlling safety state of solid state power controller - Google Patents
Circuit and method for controlling safety state of solid state power controller Download PDFInfo
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- CN114123095A CN114123095A CN202111336709.5A CN202111336709A CN114123095A CN 114123095 A CN114123095 A CN 114123095A CN 202111336709 A CN202111336709 A CN 202111336709A CN 114123095 A CN114123095 A CN 114123095A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/05—Details with means for increasing reliability, e.g. redundancy arrangements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0061—Details of emergency protective circuit arrangements concerning transmission of signals
- H02H1/0084—Details of emergency protective circuit arrangements concerning transmission of signals by means of pilot wires or a telephone network; watching of these wires
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H1/00—Details of emergency protective circuit arrangements
- H02H1/0092—Details of emergency protective circuit arrangements concerning the data processing means, e.g. expert systems, neural networks
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- Safety Devices In Control Systems (AREA)
Abstract
The invention relates to a circuit for controlling the safety state of a solid-state power controller, which is used for controlling the safety state of individual uncontrollable channels in the solid-state power controller on an airplane and comprises a CPU (1), a discrete quantity acquisition circuit (2), a processor module (3) of an SSPC (single-phase programmable logic controller) and a CPLD (complex programmable logic device) logic module (4) of the SSPC. The invention also comprises a safety state control method for the safety state control circuit of the solid-state power controller. The invention can effectively identify the uncontrolled state of the channel and timely enable the channel to enter the corresponding on/off/hold safe state according to the back-end load, thereby improving the protection capability of the solid-state power controller on the back-end load and having high reliability.
Description
Technical Field
The invention belongs to the technical field of aeroelectricity, and relates to a circuit and a method for controlling a solid-state power controller in a safe state.
Background
The solid state power controller is an intelligent switch device with protection function, the function is similar to that of the traditional breaker, the combination body of the fuse and the relay in series or other control protectors, but the solid state power controller is greatly superior to the traditional devices in performance and function, can control the on-off of the direct current/alternating current load, and has the functions of overcurrent protection and short circuit protection. In addition, the solid-state power controller can collect the current and voltage values of the load and the opening/closing state, the tripping (protection) state, the light load/full load state and the like of the channel, and carry out channel self-detection according to the conditions of the states. The digital solid-state power controller is provided with a bus interface, and can receive a control command of an upper computer through the bus interface and upload current, voltage values and various state signals of a load. The functions of remote control, protection and information acquisition are realized.
When the working environment of the solid-state power controller on an airplane changes or the reliability of external discrete quantities on the airplane is reduced, the external bus, the internal bus and the discrete quantity acquisition function of a product can be induced to break down, so that certain channels of the solid-state power controller are not controlled, and when the SSPC is not controlled, the on-off state is uncertain, so that the rear-end load can be damaged, and the fly return can be caused.
Therefore, when individual channels in the solid-state power controller are not controlled by the bus and the discrete control at the same time, the uncontrolled state of the channels is effectively identified, and the channels are timely enabled to enter the corresponding on/off/kept safe states according to the back-end load, so that the method plays an important role in improving the reliability of products and protecting the back-end load.
Disclosure of Invention
The present invention is directed to solve the above problems, and provides a control circuit and a method for making individual channels in a solid-state power controller enter a safe state when the individual channels cannot be controlled in an aircraft.
The technical scheme of the invention is as follows:
a circuit for controlling the safety state of a solid-state power controller is used for controlling the safety state of individual uncontrollable channels in the solid-state power controller on an airplane, and comprises a CPU (1), a discrete quantity acquisition circuit (2), a processor module (3) of an SSPC and a CPLD logic module (4) of the SSPC;
the method is characterized in that discrete quantity BIT excitation is sent to a discrete quantity acquisition circuit (2) by a CPU (1), the discrete quantity acquisition circuit (2) responds to the discrete quantity BIT excitation, discrete quantity signals sent by an external discrete quantity interface are combined, discrete quantity acquisition information is formed after processing and sent to the CPU (1); the processor module (3) of the SSPC is in bus communication with the CPU (1) to receive discrete quantity acquisition information; meanwhile, the CPU (1) sends the discrete quantity acquisition information to the CPLD logic module (4) of the SSPC, the CPLD logic module (4) of the SSPC judges whether the control channel enters a safe state or not according to the received information, and sends an on-off control instruction to the driving module to control the on-off of the channel in the solid-state power controller.
The device is characterized in that the discrete magnitude acquisition circuit (2) receives discrete magnitude signals sent by an external high/open discrete magnitude interface and an earth/open discrete magnitude interface.
The method is characterized in that if the processor module (3) of the SSPC recognizes that bus communication is failed, the processor module (3) of the SSPC sends a communication failure instruction to the CPLD logic module (4).
The method is characterized in that the CPU (1) sends the discrete quantity acquisition information to a CPLD logic module (4) of the SSPC through pulses.
The voltage isolation circuit is characterized in that the voltage of the CPU (1) and the voltage of the CPLD logic module (4) of the SSPC are isolated through the isolation circuit.
The method is characterized in that the CPLD logic processing module (4) of the SSPC also receives discrete quantity acquisition information from the discrete quantity acquisition circuit (2).
A method for safe state control of a solid state power controller, the method comprising the steps of:
1) the method comprises the steps that after the CPU (1) is electrified, discrete magnitude self-inspection is carried out, BIT excitation is sent to a discrete magnitude acquisition circuit (2), recovery is carried out, whether the discrete magnitude acquisition circuit (2) works normally or not is detected, and a self-inspection result is sent to a CPLD logic processing module (4) of the SSPC through pulses;
2) the external discrete magnitude interface sends a discrete magnitude signal to the discrete magnitude acquisition circuit (2), the CPU (1) monitors the sent discrete magnitude signal in real time, and when the discrete magnitude signal state is identified to change, the discrete magnitude signal is sent to a CPLD logic processing module (4) of the SSPC corresponding to the discrete magnitude signal through pulses;
3) the processor module (3) of the SSPC judges whether the internal bus communication is normal in real time, and when the processor module (3) of the SSPC judges that the internal bus fails, a communication failure instruction of the channel is sent to the CPLD logic processing module (4) of the SSPC;
4) the CPLD logic processing module (4) of the SSPC collects the received information in real time, and when the self-checking result sent by the step 1) is received to be failed, the step 5) is carried out, otherwise, the step 6) is carried out;
5) the CPLD logic processing module (4) of the SSPC judges discrete magnitude faults, and when the CPLD logic processing module (4) of the SSPC receives a communication fault instruction sent by the processor module (3) of the SSPC, the CPLD logic processing module (4) of the SSPC sends an on-off control instruction to the driving module to control the solid-state power controller to enter a safe state;
6) the CPLD logic processing module (4) of the SSPC receives the discrete quantity signal sent by the CPU (1) in the step 2), the CPLD logic processing module (4) of the SSPC receives discrete quantity acquisition information from the discrete quantity acquisition circuit (2), the discrete quantity signal and the discrete quantity acquisition information are compared, if the comparison result is consistent, the next discrete quantity signal sent by the CPU (1) is continuously waited, if the comparison result is inconsistent, and when the CPLD logic processing module (4) of the SSPC receives a communication fault instruction sent by the processor module (3) of the SSPC, the CPLD logic processing module (4) of the SSPC sends an on-off control instruction to the driving module to control the SSPC to enter a safe state;
7) after the SSPC enters the safe state, if the normal working state of the SSPC needs to be recovered, the SSPC is powered off and then powered on, so that the SSPC recovers the normal working state.
The method is characterized in that the CPU (1) is connected with all SSPC circuits through a discrete magnitude bus, so that the chip selection pulse is sent to the discrete magnitude bus, and each SSPC identifies whether the chip selection pulse corresponds to the channel and receives a discrete magnitude signal.
The invention has the beneficial effects that:
the invention realizes the pulse signal sent by the CPU and identified by the CPLD logic through the cooperation of the discrete quantity acquisition of the CPU and the SSPC processor and the CPLD logic control device, and simultaneously realizes the safety state control of channels with different control modes by combining the instruction of the SSPC processor. The strategy can effectively identify the uncontrolled state of the channel and timely enable the channel to enter a corresponding on/off/hold safety state according to the back-end load. The protection capability of the solid-state power controller on the rear-end load is improved, and the reliability is high.
Drawings
Fig. 1 is a schematic circuit diagram of the present invention.
Detailed Description
The connection structure of the present invention will be described in detail with reference to the accompanying drawings and examples.
As shown in fig. 1, the circuit for controlling the safety state of the solid state power controller of the invention is used for controlling the safety state of individual uncontrollable channels in the solid state power controller on an airplane, and comprises a CPU (1), a discrete quantity acquisition circuit (2), a processor module (3) of an SSPC and a CPLD logic module (4) of the SSPC.
Discrete magnitude BIT excitation is sent to a discrete magnitude acquisition circuit (2) by a CPU (1), the discrete magnitude acquisition circuit (2) responds to the BIT excitation, discrete magnitude signals sent by an external discrete magnitude interface are combined, discrete magnitude acquisition information is formed after processing, and the discrete magnitude acquisition information is sent to the CPU (1); the processor module (3) of the SSPC is in bus communication with the CPU (1), and if the processor module (3) of the SSPC recognizes that the bus communication fails, the processor module (3) of the SSPC sends a communication failure instruction to the CPLD logic module (4); the CPU (1) sends discrete quantity acquisition information to the CPLD logic module (4) of the SSPC through pulses, the CPLD logic processing module (4) of the SSPC receives the discrete quantity acquisition information from the discrete quantity acquisition circuit (2), the CPLD logic module (4) of the SSPC judges whether a control channel enters a safe state or not, and sends an on-off control instruction to the driving module to control the on-off of the channel in the solid power controller.
When the circuit for controlling the safety state of the solid-state power controller is used for controlling the safety state, the CPU (1) is electrified and then carries out discrete quantity self-detection, whether the discrete quantity acquisition circuit (2) works normally is detected by giving excitation and carrying out recovery, and a self-detection result is sent to a CPLD logic processing module (4) of the SSPC through pulses; the CPU (1) can monitor each discrete quantity state in real time, and when the discrete quantity state is identified to change, the discrete quantity change information can be sent to the CPLD logic processing module (4) of the SSPC corresponding to the discrete quantity through pulses; the SSPC processor (3) stores the control mode of the channel and the on-off state of the channel when entering the safe state. Meanwhile, the processor (3) can judge whether the internal bus communication is normal or not and receive information of external bus faults or not in real time, when the processor judges that the internal bus faults or receives the information of the external bus faults, a bus fault instruction and a corresponding on-off instruction of the channel are sent to the CPLD logic module (4), and the CPLD logic module (4) latches and outputs a safety state control instruction through logic processing to enable the channel to enter a safety state.
Claims (8)
1. A circuit for controlling the safety state of a solid-state power controller is used for controlling the safety state of individual uncontrollable channels in the solid-state power controller on an airplane, and comprises a CPU (1), a discrete quantity acquisition circuit (2), a processor module (3) of an SSPC and a CPLD logic module (4) of the SSPC;
the method is characterized in that discrete quantity BIT excitation is sent to a discrete quantity acquisition circuit (2) by a CPU (1), the discrete quantity acquisition circuit (2) responds to the discrete quantity BIT excitation, discrete quantity signals sent by an external discrete quantity interface are combined, discrete quantity acquisition information is formed after processing and sent to the CPU (1); the processor module (3) of the SSPC is in bus communication with the CPU (1) to receive discrete quantity acquisition information; meanwhile, the CPU (1) sends the discrete quantity acquisition information to the CPLD logic module (4) of the SSPC, the CPLD logic module (4) of the SSPC judges whether the control channel enters a safe state or not according to the received information, and sends an on-off control instruction to the driving module to control the on-off of the channel in the solid-state power controller.
2. The circuit for the safe state control of the solid state power controller according to claim 1, wherein the discrete quantity acquisition circuit (2) receives discrete quantity signals sent by an external high/open discrete quantity interface and an earth/open discrete quantity interface.
3. A circuit for the safe state control of a solid state power controller according to claim 2, characterized in that if the processor module (3) of the SSPC recognizes a bus communication failure, the processor module (3) of the SSPC sends a communication failure instruction to the CPLD logic module (4).
4. A circuit for solid state power controller safe state control according to claim 3, characterized in that the CPU (1) pulses discrete amount acquisition information to the CPLD logic module (4) of the SSPC.
5. A circuit for the safe state control of a solid state power controller according to claim 4, characterized in that the voltages of the CPU (1) and the CPLD logic module (4) of the SSPC are isolated by an isolation circuit.
6. A circuit for solid state power controller safe state control according to claim 5, characterized in that the CPLD logic processing module (4) of the SSPC itself also receives discrete quantity acquisition information from the discrete quantity acquisition circuit (2).
7. A method of safety state control of a circuit for safety state control of a solid state power controller according to any of claims 1 to 6, wherein the method of safety state control comprises the steps of:
1) the method comprises the steps that after the CPU (1) is electrified, discrete magnitude self-inspection is carried out, BIT excitation is sent to a discrete magnitude acquisition circuit (2), recovery is carried out, whether the discrete magnitude acquisition circuit (2) works normally or not is detected, and a self-inspection result is sent to a CPLD logic processing module (4) of the SSPC through pulses;
2) the external discrete magnitude interface sends a discrete magnitude signal to the discrete magnitude acquisition circuit (2), the CPU (1) monitors the sent discrete magnitude signal in real time, and when the discrete magnitude signal state is identified to change, the discrete magnitude signal is sent to a CPLD logic processing module (4) of the SSPC corresponding to the discrete magnitude signal through pulses;
3) the processor module (3) of the SSPC judges whether the internal bus communication is normal in real time, and when the processor module (3) of the SSPC judges that the internal bus fails, a communication failure instruction of the channel is sent to the CPLD logic processing module (4) of the SSPC;
4) the CPLD logic processing module (4) of the SSPC collects the received information in real time, and when the self-checking result sent by the step 1) is received to be failed, the step 5) is carried out, otherwise, the step 6) is carried out;
5) the CPLD logic processing module (4) of the SSPC judges discrete magnitude faults, and when the CPLD logic processing module (4) of the SSPC receives a communication fault instruction sent by the processor module (3) of the SSPC, the CPLD logic processing module (4) of the SSPC sends an on-off control instruction to the driving module to control the solid-state power controller to enter a safe state;
6) the CPLD logic processing module (4) of the SSPC receives the discrete quantity signal sent by the CPU (1) in the step 2), the CPLD logic processing module (4) of the SSPC receives discrete quantity acquisition information from the discrete quantity acquisition circuit (2), the discrete quantity signal and the discrete quantity acquisition information are compared, if the comparison result is consistent, the next discrete quantity signal sent by the CPU (1) is continuously waited, if the comparison result is inconsistent, and when the CPLD logic processing module (4) of the SSPC receives a communication fault instruction sent by the processor module (3) of the SSPC, the CPLD logic processing module (4) of the SSPC sends an on-off control instruction to the driving module to control the SSPC to enter a safe state;
7) after the SSPC enters the safe state, if the normal working state of the SSPC needs to be recovered, the SSPC is powered off and then powered on, so that the SSPC recovers the normal working state.
8. The security state control method of claim 7, wherein the CPU (1) is connected to all SSPC circuits via a discrete magnitude bus, so that the chip select pulse is first sent to the discrete magnitude bus, and each SSPC identifies itself whether the chip select pulse corresponds to the channel and receives the discrete magnitude signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111336709.5A CN114123095A (en) | 2021-11-12 | 2021-11-12 | Circuit and method for controlling safety state of solid state power controller |
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| CN202111336709.5A CN114123095A (en) | 2021-11-12 | 2021-11-12 | Circuit and method for controlling safety state of solid state power controller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115180A (en) * | 2021-11-12 | 2022-03-01 | 天津航空机电有限公司 | Self-checking circuit and method for analog quantity acquisition |
| CN117741293A (en) * | 2023-11-30 | 2024-03-22 | 中航通飞华南飞机工业有限公司 | Aviation solid-state block terminal on-line measuring device |
-
2021
- 2021-11-12 CN CN202111336709.5A patent/CN114123095A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115180A (en) * | 2021-11-12 | 2022-03-01 | 天津航空机电有限公司 | Self-checking circuit and method for analog quantity acquisition |
| CN117741293A (en) * | 2023-11-30 | 2024-03-22 | 中航通飞华南飞机工业有限公司 | Aviation solid-state block terminal on-line measuring device |
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