CN114116586A - Serial port data processing method and device and electronic equipment - Google Patents
Serial port data processing method and device and electronic equipment Download PDFInfo
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Abstract
The application discloses a serial port data processing method, a device and electronic equipment, wherein the method comprises the following steps: receiving first serial port data sent by an operating system; forwarding the first serial port data to a substrate management controller and a rear IO interface; receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different; and sending the second serial port data to the operating system. According to the scheme, the operation system is separately connected with the substrate management controller and the rear IO interface through the field programmable gate array FPGA, and the communication between the rear IO interface and the operation system does not depend on the substrate management controller any more through the bridging effect of the field programmable gate array FPGA, so that when the substrate management controller breaks down, the external connection can still realize the communication with the operation system through the rear IO interface.
Description
Technical Field
The present application relates to the field of computers, and in particular, to a serial port data processing method and apparatus, and an electronic device.
Background
In the current server requirement, the operating system needs to provide serial port data to both the baseboard management controller and the host computer. In some implementation schemes, the outward transmission of serial port data of the operating system is realized by depending on the baseboard management controller no matter a path passing through the baseboard management controller or a post-IO path of the host; the serial port data of the post IO path of the host computer needs to be transferred through the substrate management controller, so that the dependence on the substrate management controller is formed. Therefore, when the baseboard management controller fails, the operating system cannot interact with the outside, and normal use of the user is affected.
Disclosure of Invention
In view of this, the present application provides the following technical solutions:
a serial port data processing method is applied to a Field Programmable Gate Array (FPGA), and comprises the following steps:
receiving first serial port data sent by an operating system;
forwarding the first serial port data to a substrate management controller and a rear IO interface;
receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different;
and sending the second serial port data to the operating system.
Optionally, forwarding the first serial port data to the baseboard management controller and the post IO interface includes:
and forwarding the first serial port data to a substrate management controller and a rear IO interface through a multiplexer.
Optionally, the receiving the first serial data sent by the operating system includes:
and receiving first serial port data sent by the operating system under the condition that the data sending serial port of the operating system is monitored to be converted from a first level to a second level.
Optionally, the sending the second serial port data to the operating system includes:
and sending the second serial port data to a data receiving serial port of the operating system through a multiplexer.
Optionally, the receiving, based on the first policy, the second serial port data sent by the baseboard management controller or the backend IO interface includes:
when the substrate management controller or the rear IO interface sends data independently, second serial port data sent by the substrate management controller or the rear IO interface is directly received;
when the substrate management controller or the rear IO interface simultaneously sends data, a communicable path is determined based on set priority, and second serial port data transmitted by the communicable path is received, wherein the communicable path represents the substrate management controller or the rear IO interface.
Optionally, the level value of the data sending serial port of the baseboard management controller is monitored to determine whether the data sending serial port of the baseboard management controller sends out data.
Optionally, when the serial port to network port function of the baseboard management controller is turned on or turned off, the level value of the data sending serial port of the baseboard management controller changes.
A serial port data processing device is applied to a Field Programmable Gate Array (FPGA), and comprises:
the downlink data receiving module is used for receiving first serial port data sent by an operating system;
the downlink data sending module is used for forwarding the first serial port data to the substrate management controller and the rear IO interface;
the uplink data receiving module is used for receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, and the data transmission directions of the first serial port data and the second serial port data are different;
and the uplink data sending module is used for sending the second serial port data to the operating system.
Optionally, the uplink data receiving module is specifically configured to: when the substrate management controller or the rear IO interface sends data independently, second serial port data sent by the substrate management controller or the rear IO interface is directly received; when the substrate management controller or the rear IO interface simultaneously sends data, a communicable path is determined based on set priority, and second serial port data transmitted by the communicable path is received, wherein the communicable path represents the substrate management controller or the rear IO interface.
An electronic device, comprising:
a processor;
a memory for storing executable instructions of the processor;
wherein the executable instructions comprise: receiving first serial port data sent by an operating system; forwarding the first serial port data to a substrate management controller and a rear IO interface; receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different; and sending the second serial port data to the operating system.
Compared with the prior art, the embodiment of the application discloses a serial port data processing method, a device and an electronic device, and the method comprises the following steps: receiving first serial port data sent by an operating system; forwarding the first serial port data to a substrate management controller and a rear IO interface; receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different; and sending the second serial port data to the operating system. According to the scheme, the operation system is separately connected with the substrate management controller and the rear IO interface through the field programmable gate array FPGA, and the communication between the rear IO interface and the operation system does not depend on the substrate management controller any more through the bridging effect of the field programmable gate array FPGA, so that when the substrate management controller breaks down, the external connection can still realize the communication with the operation system through the rear IO interface.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a serial port data processing method disclosed in an embodiment of the present application;
fig. 2 is a schematic diagram of an implementation architecture of a serial port data processing method disclosed in the embodiment of the present application;
fig. 3 is a flowchart of another serial port data processing method disclosed in the embodiment of the present application;
fig. 4 is a schematic structural diagram of a serial port data processing apparatus disclosed in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application can be applied to electronic equipment, the product form of the electronic equipment is not limited by the application, and the electronic equipment can include but is not limited to a smart phone, a tablet computer, wearable equipment, a Personal Computer (PC), a netbook and the like, and can be selected according to application requirements.
Fig. 1 is a flowchart of a serial port data processing method disclosed in an embodiment of the present application. The method shown in fig. 1 can be applied to a field programmable gate array FPGA. Referring to fig. 1, the serial port data processing method may include:
step 101: and receiving first serial port data sent by an operating system.
In this implementation, the field programmable gate array FPGA is used as a transfer structure for transferring serial data, and is used to transfer the serial data sent by the operating system to the BMC and/or the post IO interface of the substrate management controller, and also used to transfer the serial data sent by the BMC or the post IO interface of the substrate management controller to the field programmable gate array FPGA. In the process of transmitting serial port data, the FPGA does not process any essential content of the data to be transmitted, and is only responsible for shunting and forwarding the data. The back IO interface therein is typically provided on the host backplane, such as the currently existing DB9 interface.
The CPU converts the parallel data characters into continuous serial data flow through the serial interface and sends the serial data flow to the FPGA, and the FPGA carries out forwarding control on the received serial data. In this realization, the field programmable gate array FPGA independently connects base plate management controller BMC and rearmounted IO interface simultaneously, therefore, FPGA can say that the serial port data that CPU sent sends alone and send to base plate management controller BMC, also can send alone to rearmounted IO interface. Certainly, the FPGA may also send the received serial port data to the BMC and the post IO interface simultaneously.
Step 102: and forwarding the first serial port data to a substrate management controller and a rear IO interface.
After receiving serial data sent by a CPU through a serial interface, based on serial port output requirements, the field programmable gate array FPGA sends the serial data to a Baseboard Management Controller (BMC) through an interface connected with the BMC, and simultaneously sends the serial data to a rear IO interface through an interface connected with the rear IO interface.
Specifically, the forwarding the first serial port data to the baseboard management controller and the post IO interface may include, but is not limited to: and forwarding the first serial port data to a substrate management controller and a rear IO interface through a multiplexer. In this application, serial data sent by the CPU is referred to as first serial data.
Step 103: and receiving second serial port data sent by the substrate management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different.
The second serial port data refers to serial port data sent to the CPU from the outside.
An operating system (CPU) sends serial port data to the outside and receives the serial port data from the outside, so that the transmission direction of the serial port data is bidirectional. In the realization, the FPGA is simultaneously connected with the BMC and the rear IO interface, the CPU only has one data receiving serial port, and only one path of serial port data can be transmitted in one time period. Therefore, in implementation, it is required to determine whether to transmit the second serial port data sent by the BMC of the baseboard management controller to the CPU or to transmit the second serial port data sent by the post IO interface to the CPU based on the first policy.
Step 104: and sending the second serial port data to the operating system.
After the second serial port data needing to be transmitted to the CPU is determined, the communication path corresponding to the second serial port data is directly communicated, so that the second serial port data is transmitted to the operating system, that is, the aforementioned CPU.
According to the serial port data processing method, the independent connection between the operating system and the substrate management controller and the rear IO interface is achieved through the field programmable gate array FPGA, the communication between the rear IO interface and the operating system is not dependent on the substrate management controller any more through the bridging effect of the field programmable gate array FPGA, and therefore when the substrate management controller breaks down, the external connection can still achieve communication with the operating system through the rear IO interface.
Fig. 2 is a schematic diagram of an implementation architecture of a serial port data processing method disclosed in the embodiment of the present application. Among them, the CPU0 may be understood as an operating system; the UART is a serial port, wherein the UART is a data output serial port with a _TXmark, and the UART is a data input serial port with a _RXmark; the MUX is a multiplexer in the field programmable gate array FPGA; a URAT (Universal Asynchronous Receiver/Transmitter) controller is a controller related to serial port management in a substrate management controller; route (SOL) is a module for realizing the function of converting a serial port into a network; MAX3232 is a chip for level conversion; the RearIO can be understood as a post IO interface.
Referring to fig. 2, in an implementation scheme, a field programmable gate array FPGA serves as a transfer station, and a CPU, a baseboard management controller BMC, and a reader IO are all connected to the FPGA. One implementation may include:
1. after the UART0_ TX of the CPU is connected to the FPGA, the FPGA converts the UART0_ TX into two, and the two are simultaneously output to the UART1_ RX of the BMC and the RX of the REAR IO, so that the BMC and the REAR IO can simultaneously receive data. .
2. The input source of CPU's UART0_ RX needs to switch, and when SOL active, REAR IO and SOL are arbitrated by FPGA inside, and when having data output, who is connected to UART0_ RX, and when having data, SOL priority is high simultaneously, only links up the TX of SOL.
3. When BMC is abnormal, FPGA can receive serial port command through REAR IO, switches REAR IO to CPU RX side, guarantees that system UART link is unblocked.
Therefore, through the scheme, one path of serial port of the system can realize interaction with the BMC and simultaneously communicate with the REAR IO serial port; the system debugging does not depend on BMC any more, and when the BMC is abnormal, the BMC can still be switched through the FPGA and is communicated with the system through REAR IO; and the realization can solve the conflict problem when the REAR IO and the BMC simultaneously output data to the system, and the FPGA realizes arbitration.
Based on the above, in one implementation, the receiving the first serial data sent by the operating system may include: and receiving first serial port data sent by the operating system under the condition that the data sending serial port of the operating system is monitored to be converted from a first level to a second level.
The FPGA can constantly monitor the level value of the serial port connected with the CPU. It can be understood that the level value of the serial port is different between the case of data transmission and the case of no data transmission, and the level value of the serial port is higher than the level value of the serial port without data transmission under normal conditions; and the approximate ranges of these level values may be determined based on experimentation or experience.
Therefore, if the field programmable gate array FPGA detects that the level value of the serial port connected with the CPU corresponds to the numerical value range of data transmission, the field programmable gate array FPGA can determine that the operating system sends the first serial port data to the field programmable gate array FPGA.
In one implementation, the sending the second serial port data to the operating system may include: and sending the second serial port data to a data receiving serial port of the operating system through a Multiplexer (MUX).
The multiplexer can divide one path of serial data received from the CPU into multiple paths of serial data and respectively send the multiple paths of serial data to different destinations. It should be noted that, one path of serial data is divided into multiple paths of serial data, and one path of serial data is not divided into different parts, but rather is equivalent to "copying" one path of serial data into the same multiple paths of serial data. Therefore, the serial port data received by the baseboard management controller BMC and the post IO interface are completely the same.
Fig. 3 is a flowchart of another serial port data processing method disclosed in the embodiment of the present application, and referring to fig. 3, the data processing method may include:
step 301: and receiving first serial port data sent by an operating system.
Step 302: and forwarding the first serial port data to a baseboard management controller and a rear IO interface, and entering step 302 or step 303.
Step 303: when the substrate management controller or the post IO interface sends out data alone, the second serial port data sent by the substrate management controller or the post IO interface is directly received, and step 305 is performed.
When only the baseboard management controller BMC or the rear IO interface sends data, the data sent to the CPU serial port does not conflict, the second serial port data sent by the baseboard management controller or the rear IO interface can be directly received, and the second serial port data are determined to be the data needing to be sent to the CPU serial port.
Step 304: when the baseboard management controller or the post IO interface simultaneously sends out data, a communicable path is determined based on a set priority, and second serial data transmitted by the communicable path is received, and step 305 is performed.
Wherein the communicable path characterizes the baseboard management controller or the post IO interface.
When the baseboard management controller BMC or the rear IO interface sends data simultaneously, only one path of data can be sent to the CPU serial port, so that arbitration judgment needs to be carried out by the field programmable gate array FPGA, and whether the second serial port data from the baseboard management controller BMC or the rear IO interface is sent to the CPU serial port is determined.
In the present implementation, the communicable paths are determined based on the set priorities. Of course, the determination of the communicable paths may also be based on other rules, e.g. in the first case, determining which path to switch on; in the second case, the communicable paths are determined based on the set priority.
Step 305: and sending the second serial port data to the operating system.
The embodiment introduces a detailed implementation of transmitting serial port data from the outside to the CPU, so that those skilled in the art can better understand the implementation of the present application.
In the implementation, whether the data sending serial port of the baseboard management controller sends out data or not can be determined by monitoring the level value of the data sending serial port of the baseboard management controller. When the function of the serial port to the network port of the substrate management controller is turned on or turned off, the level value of the data sending serial port of the substrate management controller changes. When the function of a serial port to a network port of the substrate management controller is started, representing that the BMC of the substrate management controller sends serial port data to the FPGA; and when the serial port to network port function of the substrate management controller is closed, the characteristic substrate management controller BMC does not send serial port data to the FPGA.
While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present application is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
The method is described in detail in the embodiments disclosed in the present application, and the method of the present application can be implemented by various types of apparatuses, so that an apparatus is also disclosed in the present application, and the following detailed description is given of specific embodiments.
Fig. 4 is a schematic structural diagram of a serial port data processing apparatus disclosed in an embodiment of the present application. The device shown in fig. 4 is applied to a field programmable gate array FPGA. As shown in fig. 4, the serial data processing apparatus 40 may include:
the downlink data receiving module 401 is configured to receive first serial port data sent by an operating system.
A downlink data sending module 402, configured to forward the first serial port data to the baseboard management controller and the post IO interface.
An uplink data receiving module 403, configured to receive, based on a first policy, second serial data sent by the baseboard management controller or the backend IO interface, where data transmission directions of the first serial data and the second serial data are different.
An uplink data sending module 404, configured to send the second serial port data to the operating system.
According to the serial port data processing device, the independent connection between the operating system and the substrate management controller and the rear IO interface is achieved through the FPGA, the communication between the rear IO interface and the operating system does not depend on the substrate management controller any more through the bridging effect of the FPGA, and therefore when the substrate management controller breaks down, the external connection can still achieve communication with the operating system through the rear IO interface.
In one implementation, the downlink data sending module 402 is specifically configured to: and forwarding the first serial port data to a substrate management controller and a rear IO interface through a multiplexer.
In one implementation, the downlink data receiving module 401 may be specifically configured to: and receiving first serial port data sent by the operating system under the condition that the data sending serial port of the operating system is monitored to be converted from a first level to a second level.
In one implementation, the uplink data sending module is specifically configured to: and sending the second serial port data to a data receiving serial port of the operating system through a multiplexer.
In one implementation, the uplink data receiving module is specifically configured to: when the substrate management controller or the rear IO interface sends data independently, second serial port data sent by the substrate management controller or the rear IO interface is directly received; when the substrate management controller or the rear IO interface simultaneously sends data, a communicable path is determined based on set priority, and second serial port data transmitted by the communicable path is received, wherein the communicable path represents the substrate management controller or the rear IO interface.
In one implementation, whether the data sending serial port of the baseboard management controller sends out data is determined by monitoring the level value of the data sending serial port of the baseboard management controller.
In one implementation, when the serial port to network port function of the baseboard management controller is turned on or turned off, the level value of the data sending serial port of the baseboard management controller changes.
The serial data processing device in any one of the above embodiments includes a processor and a memory, where the downlink data receiving module, the downlink data sending module, the uplink data receiving module, the uplink data sending module, and the like in the above embodiments are all stored in the memory as program modules, and the processor executes the program modules stored in the memory to implement corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program module from the memory. The kernel can be provided with one or more, and the processing of the return visit data is realized by adjusting the kernel parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
The embodiment of the application provides a storage medium, wherein a program is stored on the storage medium, and when the program is executed by a processor, the serial port data processing method in the embodiment is realized.
The embodiment of the application provides a processor, wherein the processor is used for running a program, and the serial port data processing method in the embodiment is executed when the program runs.
Further, the present embodiment provides an electronic device, which includes a processor and a memory. The memory is used for storing executable instructions of the processor, and the processor is configured to execute the serial port data processing method in the above embodiment by executing the executable instructions.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A serial port data processing method is applied to a Field Programmable Gate Array (FPGA), and comprises the following steps:
receiving first serial port data sent by an operating system;
forwarding the first serial port data to a substrate management controller and a rear IO interface;
receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different;
and sending the second serial port data to the operating system.
2. The serial port data processing method according to claim 1, wherein the forwarding the first serial port data to a baseboard management controller and a back IO interface comprises:
and forwarding the first serial port data to a substrate management controller and a rear IO interface through a multiplexer.
3. The serial port data processing method according to claim 2, wherein the receiving of the first serial port data sent by the operating system includes:
and receiving first serial port data sent by the operating system under the condition that the data sending serial port of the operating system is monitored to be converted from a first level to a second level.
4. The serial port data processing method according to claim 3, wherein the sending the second serial port data to the operating system includes:
and sending the second serial port data to a data receiving serial port of the operating system through a multiplexer.
5. The serial port data processing method according to claim 1, wherein the receiving of the second serial port data sent by the baseboard management controller or the backend IO interface based on the first policy includes:
when the substrate management controller or the rear IO interface sends data independently, second serial port data sent by the substrate management controller or the rear IO interface is directly received;
when the substrate management controller or the rear IO interface simultaneously sends data, a communicable path is determined based on set priority, and second serial port data transmitted by the communicable path is received, wherein the communicable path represents the substrate management controller or the rear IO interface.
6. The serial port data processing method according to claim 5, wherein it is determined whether the data transmission serial port of the baseboard management controller transmits data by monitoring a level value of the data transmission serial port of the baseboard management controller.
7. The serial port data processing method according to claim 6, wherein when a serial port to network port function of the baseboard management controller is turned on or off, a level value of a data transmission serial port of the baseboard management controller changes.
8. A serial port data processing device is applied to a Field Programmable Gate Array (FPGA), and comprises:
the downlink data receiving module is used for receiving first serial port data sent by an operating system;
the downlink data sending module is used for forwarding the first serial port data to the substrate management controller and the rear IO interface;
the uplink data receiving module is used for receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, and the data transmission directions of the first serial port data and the second serial port data are different;
and the uplink data sending module is used for sending the second serial port data to the operating system.
9. The serial port data processing device according to claim 8, wherein the uplink data receiving module is specifically configured to: when the substrate management controller or the rear IO interface sends data independently, second serial port data sent by the substrate management controller or the rear IO interface is directly received; when the substrate management controller or the rear IO interface simultaneously sends data, a communicable path is determined based on set priority, and second serial port data transmitted by the communicable path is received, wherein the communicable path represents the substrate management controller or the rear IO interface.
10. An electronic device, comprising:
a processor;
a memory for storing executable instructions of the processor;
wherein the executable instructions comprise: receiving first serial port data sent by an operating system; forwarding the first serial port data to a substrate management controller and a rear IO interface; receiving second serial port data sent by the baseboard management controller or the rear IO interface based on a first strategy, wherein the data transmission directions of the first serial port data and the second serial port data are different; and sending the second serial port data to the operating system.
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| CN102281254A (en) * | 2010-06-10 | 2011-12-14 | 鸿富锦精密工业（深圳）有限公司 | Design system and method of server serial port |
| WO2016101408A1 (en) * | 2014-12-24 | 2016-06-30 | 中兴通讯股份有限公司 | Server serial port switching apparatus and method, and server |
| CN112015689A (en) * | 2019-05-29 | 2020-12-01 | 阿里巴巴集团控股有限公司 | Serial port output path switching method, system and device and switch |
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