CN113970697B - Analog circuit state evaluation method and device - Google Patents
Analog circuit state evaluation method and device Download PDFInfo
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Abstract
The invention discloses a method and a device for evaluating the state of an analog circuit, which solve the problem that the existing method and device cannot identify element parameters. The method comprises the following steps: injecting pulse signals into the analog circuit to enable element parameters to change from a nominal value, collecting output response signals of any element parameter change moment, and carrying out normalization processing to obtain normalization response signals corresponding to the element; respectively establishing a feature extraction model for each element; taking the normalized response signals as input and output parameters, constructing a self-coding network, and training a feature extraction model to obtain element feature values; constructing a maximum mapping relation and a minimum mapping relation for each element; and calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit. The invention realizes accurate and rapid evaluation of the analog circuit state.
Description
Technical Field
The present invention relates to the field of circuit state evaluation, and in particular, to a method and apparatus for evaluating an analog circuit state.
Background
With the use of the circuit, component parameters in the circuit gradually drift, the drift of parameter values leads to the reduction of circuit performance, and the final result of the reduction of the circuit performance can lead to the occurrence of circuit faults. It is therefore necessary to extract the characteristic values of the circuit performance variations due to the drift of the circuit element parameter values. The existing method comprises the steps of analyzing the dimensionality of a data set extraction feature value by using a maximum likelihood method, and extracting features by using a self-coding neural network; providing a distribution of cumulative damage using a distribution of load parameters and input variables measured in a Monte-Carlo simulation, estimating health using regression analysis of the cumulative damage distribution; and projecting the extracted feature vector into a high-dimensional space by using a kernel-based learning algorithm, and distinguishing a healthy state from a fault state by using likelihood estimation and a global optimization algorithm. The disadvantage of the above method is that the degradation degree of the component parameters or the parameter values cannot be identified.
Disclosure of Invention
The invention provides a method and a device for evaluating the state of an analog circuit, which solve the problem that the existing method and device cannot identify element parameters.
To solve the above problems, the present invention is achieved as follows:
The embodiment of the invention provides an analog circuit state evaluation method, which comprises the following steps: injecting pulse signals into the analog circuit to enable element parameters to change from a nominal value, collecting output response signals of any element parameter change moment, and carrying out normalization processing to obtain normalization response signals corresponding to the element. And respectively establishing a characteristic extraction model for each element, wherein signals flow from an input layer to an LSTM (Long Short Term Memory, long-term memory) network layer, a full-connection layer to an output layer in the characteristic extraction model. And constructing a self-coding network by taking the normalized response signals as input and output parameters, taking a loss value of the self-coding network smaller than a preset loss value as a termination condition, and training the feature extraction model to obtain an output signal of the LSTM network layer as an element feature value. And respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output, and constructing a maximum mapping relation and a minimum mapping relation for each element. And calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
Preferably, in the feature extraction model, the number of nodes of each layer of the input layer, the LSTM network layer, the full connection layer and the output layer is the same, and all the nodes are the number of the normalized response signals.
Preferably, the step of training the feature extraction model further includes: and taking the normalized response signal as an input parameter, and transmitting the normalized response signal to the LSTM network layer by the input layer. And calculating the forgetting door forward propagation signal, the updating door forward propagation signal and the cell state intermediate signal at the current moment according to the normalized response signal at the current moment and the LSTM network layer hiding output state at the last moment. And calculating the cell state signal at the current moment according to the forgetting gate forward propagation signal at the current moment, the updating gate forward propagation signal, the cell state intermediate signal and the cell state signal at the last moment. And calculating the forward propagation signal of the output gate at the current moment according to the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment. And calculating the hidden output state of the LSTM network layer at the current moment according to the forward propagation signal of the output gate at the current moment and the cell state signal. And calculating the forward propagation signal of the full-connection layer at the current moment according to the hidden output state of the LSTM network layer at the current moment. Transmitting all the full-connection layer forward propagation signals at all the acquisition moments to the output layer, calculating loss values, iteratively updating all model parameters by adopting a random gradient method until the termination condition is met, and taking the LSTM network layer hidden output states at all the acquisition moments as the element characteristic values.
Preferably, the method for judging the state of the analog circuit is as follows: if the deviation between the element evaluation value and the element nominal value is within a first tolerance setting range of the element parameter, the analog circuit is in a health state; if the deviation between the element evaluation value and the element nominal value is within a second tolerance setting range of the element parameter, the analog circuit is in a degraded state; otherwise, the analog circuit is in a fault state.
Preferably, the method of calculating the component evaluation value further includes: and calculating the absolute difference value of the element parameters in the maximum mapping relation and the minimum mapping relation of each element. And finding out the element corresponding to the minimum value in all the absolute differences, and calculating an element evaluation value.
Further, the output response signal at the moment of changing the parameter of any element is normalized.
Further, the step of injecting pulse signals into the analog circuit to change the element parameters from the nominal value and collecting the output response signals of any element parameter change moment further comprises the following steps: setting an element parameter acquisition initial value, an element parameter acquisition end value and an element parameter acquisition step value. Pulse signals are injected into the analog circuit so that the element parameters start to change from the nominal value, and the change range is between the initial value and the end value of the element parameter collection. And acquiring and outputting a response signal according to the element parameter acquisition stepping value.
Preferably, the first tolerance setting range is 5% or less of the nominal value, and the second tolerance setting range is more than 5% and less than 50% of the nominal value.
An embodiment of the present invention further provides an analog circuit state evaluation device, using any one of the above methods, including: the system comprises an acquisition processing module, a feature extraction module, a mapping module and an evaluation module. The acquisition processing module is used for acquiring the output response signal of any element parameter change moment in the analog circuit, and carrying out normalization processing to obtain a normalization response signal corresponding to the element. And the feature extraction module is used for respectively establishing a feature extraction model comprising an input layer, an LSTM network layer, a full connection layer and an output layer for each element, taking the normalized response signals as input and output parameters, and carrying out model training to obtain corresponding element feature values. And the mapping module is used for respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output and constructing a maximum mapping relation and a minimum mapping relation for each element. And the evaluation module is used for calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
Preferably, the LSTM network layer includes: forget gate, update gate, cell status update gate and output gate. And the forgetting gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a forgetting gate forward propagation signal at the current moment. And the updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting the forward propagation signal of the updating gate at the current moment. And the cell state updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a cell state intermediate signal at the current moment. And the output gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting the forward propagation signal of the output gate at the current moment. The LSTM network layer is used for calculating the hidden output state of the LSTM network layer at the current moment according to the forward propagation signal of the output gate at the current moment and the cell state signal.
The embodiment of the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the method according to any one of the embodiments.
The embodiment of the invention also provides electronic equipment, which comprises a memory, a processor and a computer program stored in the memory and capable of being run by the processor, wherein the scheme of any embodiment is realized when the processor executes the computer program.
The beneficial effects of the invention include: according to the invention, through impulse response of the analog circuit and combining with excellent feature extraction capability of LSTM on time sequence, a feature extraction model is established, feature values of the analog circuit are extracted, element parameters are identified according to maximum and minimum feature values and an interpolation algorithm, and the state of the analog circuit is deduced according to comparison of element parameter values and nominal values. The invention can automatically extract the characteristic value of the analog circuit and identify the parameters of the circuit elements, thereby deducing the health state of the circuit and improving the accuracy of state evaluation; and the element parameters are rapidly identified according to the output response, so that the detection efficiency is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIG. 1 is a flow chart of an analog circuit state evaluation method;
FIG. 2 is a feature extraction model embodiment;
FIG. 3 is an embodiment of an analog circuit state estimation device;
FIG. 4 is an LSTM network layer structure embodiment;
FIG. 5 (a) is a block diagram of a bandpass filter of an analog circuit evaluation embodiment;
FIG. 5 (b) is a graph of maximum eigenvalues of an analog circuit evaluation embodiment;
fig. 5 (c) is a graph of minimum eigenvalues of an analog circuit evaluation embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments of the present invention and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The innovation point of the invention is that: according to the invention, the LSTM algorithm in the deep learning is used for rapidly extracting the characteristic value of the output response of the analog circuit, and the element parameter is identified according to the extracted characteristic value, so that the state of the analog circuit can be evaluated through the element parameter.
The following describes in detail the technical solutions provided by the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a flowchart of an analog circuit state evaluation method, which provides a method with a higher component parameter identification rate for an analog circuit, as an embodiment of the invention, the method specifically includes the following steps 101 to 105:
In step 101, before the pulse signal is injected into the analog circuit, each element parameter in the circuit is a nominal value, and after the pulse signal is injected into the analog circuit, each element parameter in the circuit starts to change, and according to the characteristics of the injected pulse signal, the element parameter is larger or smaller than the nominal value.
In the embodiment of the present invention, the output response signal of the element parameter refers to the response signal at the element node, which may be a time domain signal, and is not particularly limited.
In the embodiment of the invention, the normalized response signal is used as a training sample of a model, pulse signals can be injected into an analog circuit for many times in order to increase the number of the training samples, and the normalized response signal is obtained by adopting the same signal sampling and processing mode.
In the embodiment of the invention, an equal-time sampling method or an equal-parameter change interval sampling method can be adopted.
An equal parameter variation interval sampling method, for example, setting an element parameter acquisition initial value, an element parameter acquisition end value and an element parameter acquisition stepping value; injecting pulse signals into the analog circuit to enable element parameters to change from a nominal value, wherein the change range is between an initial value and a termination value of element parameter acquisition; and acquiring and outputting a response signal according to the element parameter acquisition stepping value.
In the embodiment of the invention, the method for carrying out normalization processing on the output response signal at the moment of changing the parameter of any element comprises the following steps:
wherein x is (t) For the normalized response signal at the current instant,
for the output response signal at the present moment, +.>
For outputting the maximum value of the response signal, namely the maximum value of the output response signal obtained in the data acquisition process>
And t is the current moment, namely the moment of any element parameter change, for the minimum value of the output response signal, namely the minimum value of the output response signal obtained in the current data acquisition process.
And 102, respectively establishing a characteristic extraction model for each element, wherein in the characteristic extraction model, a signal flows from an input layer to an LSTM network layer and a full connection layer to an output layer.
In step 102, the number of nodes in each of the input layer, the LSTM network layer, the full connection layer, and the output layer is the same, and the number is the number of the normalized response signals.
And 103, constructing a self-coding network by taking the normalized response signals as input and output parameters, taking element parameter tolerance set values as termination conditions, training the feature extraction model, and taking the obtained output signals of the LSTM network layer as element feature values.
In step 103, the element feature value includes element feature values at each acquisition time, specifically, hidden output state of LSTM network layer at each acquisition time, namely a (1) ,a (2) ,...,a (t-1) ,a (t) ,...,a (n) . Wherein t-1 is the last time, t is the current time, and n is the normalized response signalNumber of the pieces.
In step 103, a model training method is provided, comprising the following steps 103A to 103G:
in step 103, the training process of the feature extraction model includes forward propagation and reverse training, and steps 103B to 103F are all forward propagation processes, and step 103G is a reverse training process, i.e. repeated iteration is performed on each parameter in the forward propagation process by combining the loss value calculated in the reverse training process, thereby obtaining a trained feature extraction model.
Step 103A, using the normalized response signal as an input parameter, and transferring the normalized response signal to the LSTM network layer by the input layer.
In the feature extraction model, the LSTM network layer includes a forget gate, a refresh gate, a cell refresh gate, and an output gate
Step 103B, calculating the forgetting gate forward propagation signal, the updating gate forward propagation signal and the cell state intermediate signal at the current moment according to the normalized response signal at the current moment and the LSTM network layer hidden output state at the last moment.
f (t) ＝σ f (W fa a (t-1) +W fx x (t) +b f ) (2)
i (t) ＝σ i (W ia a (t-1) +W ix x (t) +b i ) (3)
Wherein f (t) 、i (t) 、
A is respectively the forgetting door forward propagation signal, the updating door forward propagation signal and the cell state intermediate signal at the current moment (t-1) Concealing the output state, x, for the LSTM network layer at the previous time (t) The normalized response signal of the current moment is t is the current moment and sigma f 、σ i Respectively forgetting door activation functionsUpdating the gate activation function, W fa 、W fx Respectively obtaining first and second weight coefficients of the forgetting door, b f Bias for forgetting door, W ia 、W ix Respectively updating the first weight coefficient and the second weight coefficient of the door, b i To update the gate bias, W ca 、W cx Respectively a first weight coefficient and a second weight coefficient of the cell state, b c For cell state bias, tanh c The activation function is updated for the cell state.
A is that (t-1) Hiding the output state for the LSTM network layer at the previous time, namely the element characteristic value at the previous time.
In step 103B, the forgetting gate activation function and the updating gate activation function may be sigmoid functions, which are not particularly limited herein.
In step 103B, it should be noted that the hidden output state of the LSTM network layer is the element feature value of the present invention.
Step 103C, calculating a cell state signal at the current moment according to the forgetting gate forward propagation signal at the current moment, the updating gate forward propagation signal, the cell state intermediate signal and the cell state signal at the last moment.
Wherein c (t) For the current time cell status signal c (t-1) Is the cell status signal at the previous time.
And 103D, calculating the forward propagation signal of the output gate at the current moment according to the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment.
o (t) ＝σ o (W oa a (t-1) +W ox x (t) +b o ) (6)
Wherein o is (t) Outputting a gate forward propagating signal, sigma, for the current time o To output the gate activation function, W oa 、W ox Respectively outputting first and second weight coefficients of the gate, b o For outputting the gate bias.
Step 103E, calculating the hidden output state of the LSTM network layer at the current time according to the forward propagation signal and the cell state signal of the output gate at the current time:
a (t) ＝o (t) ×tanh o (c (t) ) (7)
Wherein a is (t) Hiding the output state for the LSTM network layer at the current moment, namely the element characteristic value at the current moment, and obtaining the tanh o The function is activated for the output gate.
Step 103F, calculating a forward propagation signal of the full-connection layer at the current moment according to the hidden output state of the LSTM network layer at the current moment:
wherein z is (t) For the forward propagation signal of the full connection layer at the current moment, W zr Input weight for the r of the full connection layer, b r And the r bias is the full connection layer, r is the input sequence number of the full connection layer, and n is the number of LSTM network cell units.
Note that in equation 8, n represents the LSTM network cell unit number, that is, the number of the normalized response signals.
Step 103G, transmitting all the full-connection layer forward propagation signals at all the acquisition moments to the output layer, calculating a loss value, iteratively updating all the model parameters by adopting a random gradient method until the termination condition is met, and taking the hidden output state of the LSTM network layer at all the acquisition moments as the element characteristic value:
wherein L is (t) For the current time loss value, y (t) For the normalized response signal of the element at the current instant,
for outputting layer output signal at current moment, W j The j model parameter is the model parameter serial number, beta j Is the j-th gradient attenuation coefficient.
Y is as follows (t) Is the actual value of the input signal of the current time model,
and the output signal of the current moment model is the forward propagation signal of the full connection layer.
In step 103G, a loss value is calculated for each acquisition time until a termination condition is satisfied. In the embodiment of the invention, the loss value of the self-coding network is smaller than the preset loss value which is 0.1 as the termination condition. The self-coding network refers to that in the feature extraction model of the embodiment of the present invention, the input signal and the output signal are the same signal.
The magnitude of the preset loss value is not particularly limited.
In the embodiment of the invention, the training of the feature extraction model can be performed off-line or on-line. The off-line training means that a group of normalized response signals of the elements are acquired as training samples, and model training is not performed until termination conditions are met. On-line training means that the normalized response signal of each element is collected as a training sample and training is performed while the training sample is not collected and the training is performed until the termination condition is satisfied.
In step 103G, each model parameter is iteratively updated, where the model parameters to be updated are specifically: the first weight coefficient of the forgetting gate, the second weight coefficient of the forgetting gate, the forgetting gate bias, the first weight coefficient of the updating gate, the second weight coefficient of the updating gate, the gate bias, the first weight coefficient of the cell state, the second weight coefficient of the cell state, the cell state bias, the first weight coefficient of the output gate, the second weight coefficient of the output gate and the output gate bias are mentioned in the above steps. And setting initial values of the parameters, and carrying out iterative updating on each parameter by combining the loss values and a random gradient method until the termination condition is reached.
And 104, respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output, and constructing a maximum mapping relation and a minimum mapping relation for each element.
In step 104, a mapping relationship between the element parameters and the element feature values is obtained, and the output of the LSTM network of the trained feature extraction model in step 103 under each different element parameter is extracted, where each output value is the feature value under the element parameter.
In step 104, when a model training is performed on an element, a plurality of element feature values can be obtained, the maximum feature value is taken as input, element parameters are taken as output, and the maximum mapping relation is constructed; when the element is subjected to model training for many times, a plurality of maximum characteristic values can be obtained, and the maximum characteristic values can be used for constructing the maximum mapping relation. Similarly, the minimum mapping relationship can be constructed.
And establishing a mapping relation with the element parameter as output and the element characteristic value as input by an interpolation algorithm through the maximum value and the minimum value in the characteristic values.
The mapping of the maximum eigenvalue and the minimum eigenvalue to the element parameters obtained by the interpolation algorithm is as follows:
M k,max ＝f k,max (a k,max ) (12)
M k,min ＝f k,min (a k,min ) (13)
equation 12 characterizes the maximum mapping of the kth element, where k is the element number of the analog circuit, M k,max A is the maximum element parameter set of the kth element k,max Maximum element that is the kth elementFeature value set, f k,max Is the maximum mapping relationship of the kth element.
Equation 13 characterizes the minimum mapping of the kth element, where M k,min A is the minimum element parameter set of the kth element k,min A minimum element characteristic value set for the kth element, f k,min Is the minimum mapping relationship of the kth element.
The pulse signal is injected into the analog circuit for multiple times, and the model training is performed for multiple times, so that the maximum/minimum element parameter set and the maximum/minimum element characteristic value set can be obtained.
The interpolation method is not particularly limited in the present invention.
And 105, calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
In step 105, the step of calculating the component evaluation value specifically includes steps 105A to 105B:
step 105A, calculating absolute differences of element parameters in the maximum mapping relationship and the minimum mapping relationship of each element:
ΔM k ＝|M k,max -M k,min (14)
wherein DeltaM k The absolute difference value corresponding to the kth element is k is the element number of the analog circuit, M k,max M is the element parameter corresponding to the maximum mapping relation of the kth element k,min Element parameters corresponding to the k-th element minimum mapping relation.
Step 105B, finding the element corresponding to the minimum value of all absolute differences, and calculating an element evaluation value:
M pro ＝(M kmin,max +M kmin,min )/2 (15)
wherein k is min Element number M corresponding to minimum value of absolute difference pro And evaluating the element.
In step 105, the analog circuit state is determined according to the component evaluation value and the component nominal value, and the following determination criteria may be adopted:
if the deviation between the element evaluation value and the element nominal value is within a first tolerance setting range of the element parameter, the analog circuit is in a health state; if the deviation between the element evaluation value and the element nominal value is within a second tolerance setting range of the element parameter, the analog circuit is in a degraded state; otherwise, the analog circuit is in a fault state.
Preferably, the first tolerance setting range is 5% or less of the nominal value, and the second tolerance setting range is more than 5% and less than 50% of the nominal value.
The embodiment of the invention provides an analog circuit evaluation method, which can realize the rapid extraction of the characteristic value of the output response of an analog circuit through an LSTM algorithm in deep learning, can be used for any analog circuit diagnosis, can obtain the evaluation value of element parameters, and has better engineering applicability.
FIG. 2 is an example of a feature extraction model that may be used to construct the feature extraction model of the present invention.
As an embodiment of the invention, a feature extraction model comprises an input layer, an LSTM network layer, a full connection layer and an output layer.
And the number of nodes of each layer of the input layer, the LSTM network layer, the full-connection layer and the output layer is the same, and the nodes are the number n of the normalized response signals.
The input layer receives the normalized response signal of each sampling time as x (1) 、x (2) 、……、x (n-1) 、x (n) Transmitting to the LSTM network layer; the LSTM network layer calculates a hidden output state as a (1) 、a (2) 、……、a (n-1) 、a (n) Transmitting to the full connection layer; the full connection layer calculates the forward propagation signal of the full connection layer as z (1) 、z (2) 、……、z (n-1) 、z (n) Transmitting to the output layer; the output layer calculates and obtains normalized response signals
In the feature extraction model, a normalized response signal at each sampling moment is transmitted to an LSTM network layer through an output layer, forward propagation and reverse training are carried out in the LSTM network layer, and the LSTM network layer conceals the output state as an element feature value and is used for establishing a mapping relation between element parameters and the element feature value.
And the full-connection layer receives the current hidden output state output by the LSTM network layer, outputs the forward propagation signal of the full-connection layer and transmits the forward propagation signal to the output layer.
Comparing the normalized response signal of each sampling moment actually received by the output layer with the normalized response signal evaluation value of each sampling moment obtained through model training, calculating a loss value, and carrying out iterative updating on each parameter by adopting a random gradient method so as to obtain a trained feature extraction model for extracting element feature values.
FIG. 3 is a schematic diagram of an embodiment of an analog circuit state evaluation device, which can be used in the analog circuit state evaluation method of the present invention, and specifically includes: the system comprises an acquisition processing module 1, a feature extraction module 2, a mapping module 3 and an evaluation module 4.
The acquisition processing module is used for acquiring the output response signal of any element parameter change moment in the analog circuit, and carrying out normalization processing to obtain a normalization response signal corresponding to the element.
The feature extraction module is used for respectively establishing a feature extraction model comprising an input layer, an LSTM network layer, a full connection layer and an output layer for each element, taking the normalized response signals as input and output parameters, and performing model training to obtain corresponding element feature values.
The mapping module is used for respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output, and constructing a maximum mapping relation and a minimum mapping relation for each element.
The evaluation module is used for calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating the element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
Specific methods for implementing the functions of the acquisition processing module, the feature extraction module, the mapping module and the evaluation module are described in the embodiments of the methods of the present application, and are not described herein.
FIG. 4 is an embodiment of an LSTM network layer structure, which provides an LSTM network layer internal structure, comprising: forget gate 21, update gate 22, cell status update gate 23, output gate 24.
The forgetting gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a forgetting gate forward propagation signal at the current moment.
The updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting the forward propagation signal of the updating gate at the current moment.
The cell state updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a cell state intermediate signal at the current moment. And calculating the cell state signal at the current moment according to the forgetting gate forward propagation signal at the current moment, the updating gate forward propagation signal, the cell state intermediate signal and the cell state signal at the last moment.
The output gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting the forward propagation signal of the output gate at the current moment.
The LSTM network layer is used for calculating the hidden output state of the LSTM network layer at the current moment according to the forward propagation signal of the output gate at the current moment and the cell state signal.
Fig. 5 (a) is a structure diagram of a band-pass filter of an analog circuit evaluation embodiment, fig. 5 (b) is a maximum eigenvalue curve of the analog circuit evaluation embodiment, and fig. 5 (c) is a minimum eigenvalue curve of the analog circuit evaluation embodiment.
Fig. 5 provides an evaluation procedure of a specific analog circuit, a mullen-key band-pass filter, and in fig. 5 (a), the mullen-key band-pass filter includes elements and nominal values of parameters of the elements are: the resistor comprises a first resistor R1, a resistor value of 1k ohms, a second resistor R2, a resistor value of 3k ohms, a third resistor R3, a resistor value of 2k ohms, a fourth resistor R4, a resistor value of 4k ohms, a fifth resistor R5, a resistor value of 4k ohms, a first capacitor C1, a capacitor value of 5nF, a second capacitor C2 and a capacitor value of 5nF.
In the mullen-key band-pass filter, the input of the circuit is a pulse signal with amplitude of 5V, rising time of 1us, duration of 10us and falling time of 1 us.
For a first tolerance setting range in which the circuit setting resistance tolerance is set to 5% as an element parameter of the element, the setting capacitance tolerance is set to 10% as the first tolerance setting range of the element parameter of the element. The tolerance setting for the circuit is set to 5% to 50% as a second tolerance setting range for the element parameters of the element. The output of the circuit is sampled with equal time, the sampling period is 0.1us, the total sampling time is 50us, and 500 sampling points are acquired.
A certain element, for example the first resistor, is changed from 50% of the nominal value to 150% of the nominal value, i.e. from 500 ohms to 1500 ohms, each time by 0.5% of the nominal value, data are collected each time.
Fig. 5 (b) is a graph of the maximum eigenvalues of all the elements of the mullen-key band-pass filter, and the maximum mapping relationship between the element parameters and the element eigenvalues is obtained by adopting the method of the invention.
In fig. 5 (b), the abscissa represents the number of sampling points of the maximum eigenvalue curve, that is, the total number of model training times, and the ordinate represents the maximum eigenvalue. In fig. 5 (b), the number of sampling points is 95 to 105, and the maximum eigenvalues include R1, R2, R3, C1, and C2, which are marked with different symbols, respectively.
Fig. 5 (c) is a minimum eigenvalue curve of all elements of the mullen-key band-pass filter, and the minimum mapping relationship between element parameters and element eigenvalues is obtained by adopting the method of the invention.
In fig. 5 (c), the abscissa represents the number of sampling points of the minimum feature value curve, and the ordinate represents the minimum feature value. In fig. 5 (C), the number of sampling points is 95 to 105, and the minimum feature values include R1, R2, R3, C1 and C2, which are marked with different symbols, respectively.
Subtracting the longitudinal label data in fig. 5 (b) and fig. 5 (c) correspondingly, and taking the absolute value to obtain the absolute difference value of the element parameters under different mappings. And calculating the mapping output with the minimum absolute difference value, obtaining an evaluation value of the element parameter as the element evaluation value, comparing the element evaluation value with the element parameter nominal value, and evaluating the health state of the circuit.
It should be noted that, fig. 5 (b) and fig. 5 (c) do not fully draw all the sampling points in the embodiments of the present invention, and only a part of the sampling points in the embodiments of the present invention are shown for the sake of observation.
For the analog circuit of the mullen-key band-pass filter of the embodiment of the invention, the evaluation criterion is as follows: if the deviation between the element evaluation value and the element nominal value is within a first tolerance setting range of the element parameter, the analog circuit is in a health state; if the deviation between the element evaluation value and the element nominal value is within a second tolerance setting range of the element parameter, the analog circuit is in a degradation state; otherwise, the analog circuit is in a fault state.
Taking the first resistor R1 as an example, table 1 below is a result of parameter identification, and the mapping error refers to a minimum value of absolute differences of the component parameters.
TABLE 1 parameter identification results
As can be seen from table 1, the mapping error of the first resistor R1 is the smallest, and the element evaluation value of the first resistor is 515.48 ohms calculated according to equation 15.
The first resistance element parameter nominal value is 1k ohm, the deviation of the first resistance element evaluation value from the element nominal value is 484.52 ohm, and at this time, the deviation of the first resistance element evaluation value from the element nominal value is 48.45% of the first resistance element nominal value.
In the embodiment of the invention, the deviation is 48.45 percent, more than 5 percent and less than 50 percent, and the analog circuit state of the band-pass filter with the circuit state of the SALLN-key is estimated to be degraded.
In the embodiment of the invention, the state of the analog circuit of the mullen-key band-pass filter is evaluated by adopting any analog circuit evaluation method, and the evaluation accuracy can reach 99.8%.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present invention and is not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are to be included in the scope of the claims of the present invention.
Claims (10)
1. A method for evaluating the status of an analog circuit, comprising the steps of:
injecting pulse signals into the analog circuit to enable element parameters to change from a nominal value, collecting output response signals of any element parameter change moment, and carrying out normalization processing to obtain normalization response signals corresponding to the element;
Respectively establishing a characteristic extraction model for each element, wherein in the characteristic extraction model, a signal flows from an input layer to an LSTM network layer and a full connection layer to an output layer;
constructing a self-coding network by taking the normalized response signals as input and output parameters, taking a loss value of the self-coding network smaller than a preset loss value as a termination condition, and training the feature extraction model to obtain an output signal of the LSTM network layer as an element feature value;
respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output, and constructing a maximum mapping relation and a minimum mapping relation for each element;
and calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
2. The method for evaluating the state of an analog circuit according to claim 1, wherein in said feature extraction model, the number of nodes of each of said input layer, LSTM network layer, full connection layer and output layer is the same, and the number is the number of said normalized response signals.
3. The method of evaluating the state of an analog circuit according to claim 1, wherein the step of training the feature extraction model further comprises:
transmitting the normalized response signal as an input parameter from the input layer to the LSTM network layer;
calculating forgetting the forward propagation signal of the door, updating the forward propagation signal of the door and the intermediate signal of the cell state at the current moment according to the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment:
f (t) ＝σ f (W fa a (t-1) +W fx x (t) +b f )
i (t) ＝σ i (W ia a (t-1) +W ix x (t) +b i )
wherein f (t) 、i (t) 、
A is respectively the forgetting door forward propagation signal, the updating door forward propagation signal and the cell state intermediate signal at the current moment (t-1) Concealing the output state, x, for the LSTM network layer at the previous time (t) The normalized response signal of the current moment is t is the current moment and sigma f 、σ i Respectively a forgetting gate activation function and an updating gate activation function, W fa 、W fx Respectively obtaining first and second weight coefficients of the forgetting door, b f Bias for forgetting door, W ia 、W ix Respectively updating the first weight coefficient and the second weight coefficient of the door, b i To update the gate bias, W ca 、W cx Respectively a first weight coefficient and a second weight coefficient of the cell state, b c For cell state bias, tanh c Updating the activation function for the cell state;
calculating a cell state signal at the current moment according to the forgetting door forward propagation signal at the current moment, the updating door forward propagation signal, the cell state intermediate signal and the cell state signal at the last moment:
Wherein c (t) For the current time cell status signal c (t-1) A cell status signal at the previous time;
calculating a forward propagation signal of an output gate at the current moment according to the normalized response signal at the current moment and the LSTM network layer hiding output state at the last moment:
o (t) ＝σ o (W oa a (t-1) +W ox x (t) +b o )
wherein o is (t) Outputting a gate forward propagating signal, sigma, for the current time o To output the gate activation function, W oa 、W ox Respectively outputting first and second weight coefficients of the gate, b o Offset for the output gate;
calculating the hidden output state of the LSTM network layer at the current moment according to the forward propagation signal of the output gate at the current moment and the cell state signal:
a (t) ＝o (t) ×tanh o (c (t) )
wherein a is (t) Hiding the output state, tanh, for the LSTM network layer at the current moment o Activating a function for the output gate;
calculating a forward propagation signal of the full-connection layer at the current moment according to the hidden output state of the LSTM network layer at the current moment:
wherein z is (t) For the forward propagation signal of the full connection layer at the current moment，W zr Input weight for the r of the full connection layer, b r The r bias is the full connection layer, r is the input sequence number of the full connection layer, and n is the number of LSTM network cell units;
transmitting all-connection-layer forward propagation signals at all acquisition moments to the output layer, calculating loss values, iteratively updating all model parameters by adopting a random gradient method until the termination condition is met, and taking the LSTM network layer hidden output states at all acquisition moments as the element characteristic values:
Wherein L is (t) For the current time loss value, y (t) For the normalized response signal of the element at the current instant,
for outputting layer output signal at current moment, W j The j model parameter is the model parameter serial number, beta j Is the j-th gradient attenuation coefficient.
4. The method for evaluating the status of an analog circuit according to claim 1, wherein the method for judging the status of the analog circuit comprises:
if the deviation between the element evaluation value and the element nominal value is within a first tolerance setting range of the element parameter, the analog circuit is in a health state;
if the deviation between the element evaluation value and the element nominal value is within a second tolerance setting range of the element parameter, the analog circuit is in a degraded state;
otherwise, the analog circuit is in a fault state.
5. The analog circuit state evaluation method according to claim 1, wherein the method of calculating a component evaluation value further comprises:
calculating absolute difference values of element parameters in the maximum mapping relation and the minimum mapping relation of each element:
ΔM k ＝|M k,max -M k,min |
wherein DeltaM k The absolute difference value corresponding to the kth element is k is the element number of the analog circuit, M k,max M is the element parameter corresponding to the maximum mapping relation of the kth element k,min Element parameters corresponding to the k-th element minimum mapping relation;
finding the element corresponding to the minimum value in all absolute differences, and calculating an element evaluation value:
wherein k is min Element number M corresponding to minimum value of absolute difference pr o is the element evaluation value.
6. The method for evaluating the state of an analog circuit according to claim 1, wherein the method for normalizing the output response signal at the time of the change of the parameter of any element comprises:
wherein x is (t) For the normalized response signal at the current instant,
for the output response signal at the present moment, +.>
The maximum value and the minimum value of the output response signals respectively.
7. The method of evaluating the status of an analog circuit according to claim 1, wherein the step of injecting a pulse signal into the analog circuit so that the element parameter changes from a nominal value and collecting the output response signal at the time of any element parameter change, further comprises:
setting an element parameter acquisition initial value, an element parameter acquisition termination value and an element parameter acquisition stepping value;
injecting pulse signals into the analog circuit to enable element parameters to change from a nominal value, wherein the change range is between an initial value and a termination value of element parameter acquisition;
And acquiring and outputting a response signal according to the element parameter acquisition stepping value.
8. The analog circuit state evaluation method of claim 4, wherein the first tolerance setting range is 5% or less of a nominal value, and the second tolerance setting range is greater than 5% and less than 50% of the nominal value.
9. An analog circuit state evaluation device using the method according to any one of claims 1 to 8, comprising:
the acquisition processing module is used for acquiring an output response signal of any element parameter change moment in the analog circuit, and carrying out normalization processing to obtain a normalization response signal corresponding to the element;
the feature extraction module is used for respectively establishing a feature extraction model comprising an input layer, an LSTM network layer, a full connection layer and an output layer for each element, taking the normalized response signals as input and output parameters, and carrying out model training to obtain corresponding element feature values;
the mapping module is used for respectively taking the maximum value and the minimum value in the element characteristic values as input, taking element parameters as output and constructing a maximum mapping relation and a minimum mapping relation for each element;
and the evaluation module is used for calculating the mapping difference value of each element according to the maximum mapping relation and the minimum mapping relation, finding out the element corresponding to the minimum mapping difference value, calculating an element evaluation value, comparing the element evaluation value with the element nominal value, and judging the state of the analog circuit.
10. The analog circuit state evaluation device of claim 9, wherein the LSTM network layer comprises:
the forgetting gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a forward propagation signal of the forgetting gate at the current moment;
the updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a forward propagation signal of the updating gate at the current moment;
the cell state updating gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a cell state intermediate signal at the current moment;
the output gate is used for receiving the normalized response signal at the current moment and the hidden output state of the LSTM network layer at the last moment and outputting a forward propagation signal of the output gate at the current moment;
the LSTM network layer is used for calculating the hidden output state of the LSTM network layer at the current moment according to the forward propagation signal of the output gate at the current moment and the cell state signal.
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