CN113921409A - Packaging mold, packaging body and packaging method - Google Patents
Packaging mold, packaging body and packaging method Download PDFInfo
- Publication number
- CN113921409A CN113921409A CN202110696634.5A CN202110696634A CN113921409A CN 113921409 A CN113921409 A CN 113921409A CN 202110696634 A CN202110696634 A CN 202110696634A CN 113921409 A CN113921409 A CN 113921409A
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- packaging
- semiconductor chip
- mold
- grooves
- package
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
- H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a packaging mold, a packaging body and a packaging method, wherein the packaging mold comprises: an inner cavity for accommodating a semiconductor chip; a passage for communicating the inner chamber; a material injection hole communicated with the channel; and a plurality of grooves arranged on the top and/or the side wall of the inner cavity and corresponding to the region of the semiconductor chip, wherein the packaging material is injected into the inner cavity through the material injection hole and the channel, after the inner cavity is filled with the packaging material, the packaging material encapsulates the semiconductor chip to form a packaging body, and a fin-shaped heat dissipation structure is formed in the plurality of grooves. The invention can increase the heat dissipation area of the packaging body, improve the heat dissipation capability of the packaging body, and is beneficial to reducing the temperature saving of chip packaging, and meanwhile, the universality and operability of the packaging method are higher.
Description
Technical Field
The invention relates to the technical field of semiconductor heat dissipation packaging, in particular to a packaging mold, a packaging body and a packaging method.
Background
In a conventional semiconductor package structure, a semiconductor chip (referred to as a chip herein for short) needs to be injection-molded and packaged by a package mold during a manufacturing process, and the packaged chip is encapsulated in a package body. Semiconductor packages have two major challenges for electrical performance and heat dissipation control, and particularly for heat dissipation control, the semiconductor packages are required to effectively dissipate the heat generated by the chip.
The heat dissipation of the chip is directly related to whether the finally formed packaging structure can work normally, and the temperature saving is a very important parameter for evaluating risks in the practical application of the chip packaging. For the existing design of reducing the chip temperature by optimizing the heat dissipation structure of the chip package, the design optimization is generally performed only for a certain type of package structure, for example, for an FC (flip chip) structure, the design structure of the substrate is mainly optimized; for the TO package (single-side pin package), the pad design structure is mainly optimized. These design optimizations are not versatile for other different package configurations.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a packaging mold, a packaging body and a packaging method, which can increase the heat dissipation area of the packaging body, improve the heat dissipation capacity of the packaging body, contribute to reducing the temperature saving of chip packaging, and have higher universality and operability.
According to a first aspect of the present disclosure, there is provided a packaging mold for packaging a semiconductor chip, the packaging mold comprising:
an inner cavity for accommodating a semiconductor chip;
a passage for communicating with the lumen;
the material injection hole is communicated with the channel; and
a plurality of grooves disposed on the top and/or sidewalls of the inner cavity corresponding to regions of the semiconductor chip,
and after the inner cavity is filled with the packaging material, the packaging material encapsulates the semiconductor chip to form a packaging body, and a fin-shaped heat dissipation structure is formed in the plurality of grooves.
Optionally, the grooves on the top of the inner cavity among the grooves are a plurality of strip-shaped grooves parallel to each other.
Optionally, the semiconductor chip includes a plurality of leads located at opposite sides of the package body, and the plurality of bar-shaped grooves extend between the opposite sides.
Optionally, the grooves on the top of the inner cavity among the grooves are a plurality of columnar grooves spaced from each other.
Optionally, the groove located at the top of the inner cavity among the plurality of grooves is a grid-shaped groove or a plurality of nested square-shaped grooves.
Optionally, the grooves in the side walls of the inner cavity among the grooves are a plurality of strip-shaped grooves parallel to each other.
Optionally, the semiconductor chip includes a plurality of leads located on a lower surface of the package body, and the plurality of bar-shaped grooves extend between the upper surface and the lower surface of the package body.
Optionally, a first distance is provided between a lower surface of the plurality of grooves located at the top of the inner cavity and an upper surface of the semiconductor chip accommodated in the inner cavity.
Optionally, a second distance is provided between an outer surface of the plurality of grooves on the sidewall of the inner cavity and a side surface of the semiconductor chip accommodated in the inner cavity.
According to a second aspect of the present disclosure, there is provided a package body formed via the package mold package as described above, wherein the package body includes:
a substrate;
the semiconductor chip is arranged on the substrate and is electrically connected with the substrate;
and the packaging colloid is used for coating the semiconductor chip, and a fin-shaped heat dissipation structure is integrally formed on the upper surface and/or the side surface of the packaging colloid.
Optionally, the heat dissipation structure on the upper surface of the encapsulant is a heat sink extending in a horizontal direction, or the heat dissipation structure is a heat dissipation column extending in a vertical direction;
the heat dissipation structure located on the side face of the packaging colloid is a heat dissipation sheet extending along the vertical direction.
According to a third aspect of the present disclosure, there is provided a chip packaging method, including: providing a substrate;
arranging a semiconductor chip on the substrate and electrically connecting the semiconductor chip with the substrate;
placing a substrate mounted with a semiconductor chip in an inner cavity of a packaging mold according to any one of claims 1 to 6, and injecting a packaging material into the packaging mold;
and pressing the packaging material into an inner cavity of the packaging mold to integrally form the packaging colloid with the fin-shaped heat dissipation structure.
Optionally, the heat dissipation structure is located on the upper surface and/or the side surface of the encapsulant,
the heat dissipation structure on the upper surface of the packaging colloid is a heat dissipation fin extending along the horizontal direction, or the heat dissipation structure is a heat dissipation column extending along the vertical direction;
the heat dissipation structure located on the side face of the packaging colloid is a heat dissipation sheet extending along the vertical direction.
The invention has the beneficial effects that: the invention discloses a packaging mold, a packaging body and a packaging method, wherein grooves are designed on the upper surface and/or the side surface of an inner cavity of the packaging mold, so that after packaging materials are injected, the heat dissipation area of the packaging body of a semiconductor chip can be increased, the heat dissipation capacity is improved, and the temperature saving of chip packaging is facilitated to be reduced. Meanwhile, the heat dissipation structure of the packaging body is integrally formed with the packaging main body of the packaging colloid during the injection molding of the packaging material, so that the packaging method is simpler, and the universality and the operability are higher.
On the other hand, based on the fin-shaped heat dissipation structure formed by the parallel strip-shaped grooves or the nested square-shaped grooves arranged in the inner cavity of the packaging mold on the surface of the packaging body of the chip, the reinforcing ribs can be formed on the surface of the semiconductor chip, so that the semiconductor chip can better take the requirements of heat dissipation and stress into account.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
Fig. 1a to 1d illustrate a flow chart of packaging a semiconductor chip by a packaging mold provided according to an embodiment of the present disclosure;
FIG. 2 illustrates a close-up view of a top structure of an internal cavity of a package mold provided in accordance with an embodiment of the present disclosure;
FIG. 3 illustrates a cross-sectional view of a package mold cavity top groove provided in accordance with an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram illustrating a molding of a heat dissipation structure on an upper surface of a package according to an embodiment of the disclosure.
Fig. 5 is a schematic structural diagram illustrating a heat dissipation structure on an upper surface of a package according to an embodiment of the disclosure;
fig. 6 illustrates a cross-sectional view of a heat dissipation structure of an upper surface of a package provided in accordance with an embodiment of the present disclosure;
fig. 7 shows a schematic structural diagram of a heat dissipation structure on a side surface of a package according to an embodiment of the present disclosure.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The present invention will be described in detail below with reference to the accompanying drawings.
The invention discloses a packaging mold which is used for packaging a semiconductor chip. Compared with the traditional packaging mold, the packaging mold has the advantages that the plurality of grooves are formed in the smooth area at the top of the traditional packaging mold, and then after the semiconductor chip is packaged by the packaging mold, the plurality of fin-shaped heat dissipation structures can be formed on the surface of the packaging body of the semiconductor chip, so that the area of the heat dissipation area of the packaging body is increased, the heat dissipation capacity of the packaging body is improved, and the temperature saving of the packaging of the semiconductor chip is facilitated to be reduced. Wherein, a plurality of recesses can be directly processed and formed on the basis of former inner chamber top degree of depth, also can be for thickening the inner chamber top earlier, processes the formation again, specifically can carry out the rational selection according to actual conditions.
In the present disclosure, the encapsulation mold includes an inner cavity, a channel, and an injection hole. The inner cavity is used for accommodating a semiconductor chip; the channel is used for communicating two or more than two inner cavities; the material injection hole is communicated with the channel and is used for providing an injection channel of the packaging material. An encapsulant for encapsulating the semiconductor chip may be injected into the cavity through the injection hole and the channel.
Optionally, the encapsulating material may be epoxy resin, and a heat conductive filler such as aluminum oxide, aluminum nitride, silicon carbide, graphene, or a carbon nanotube may be added to the epoxy resin to improve the heat conductive performance of the encapsulated semiconductor chip.
Optionally, the cavity and/or the channel in the package mold may be completely formed in the package mold, or may be formed finally after the plurality of package mold parts are closed. Exemplarily, in an embodiment of the present invention, referring to fig. 1a to 1d, the package mold 1 includes a mold cover 11, an upper mold 12, a lower mold 13, and the like. Wherein, the lower surface of the upper die 12 is provided with a first groove, the upper surface of the lower die 12 is provided with a second groove opposite to the first groove, and after the upper die 12 and the lower die 13 are closed, the first groove and the second groove can form an inner cavity 14 for accommodating the semiconductor chip 3. Meanwhile, when the upper mold 12 and the lower mold 13 are closed, a passage 121 for communicating two or more cavities 14 may be formed.
Further, in the present embodiment, the top and/or the sidewall of the inner cavity 14 are provided with a plurality of grooves 141 corresponding to the accommodating area of the semiconductor chip 3, and after the inner cavity 14 is filled with the encapsulating material 2, the encapsulating material 2 encapsulates the semiconductor chip 3 to form an encapsulation body, and a fin-shaped heat dissipation structure for dissipating heat from the semiconductor chip 3 can be formed in the plurality of grooves 141.
In this embodiment, a first distance is provided between the lower surfaces of the plurality of grooves 141 located at the top of the cavity 14 and the upper surface of the semiconductor chip 3 accommodated in the cavity 14. A second distance is provided between the outer surfaces of the plurality of grooves 141 at the side walls of the cavity 14 and the side surfaces of the semiconductor chip 3 accommodated in the cavity 14. Thus, when the encapsulating material 2 is pressed in, the encapsulating material 2 can uniformly flow on the surface of the semiconductor chip 3, and the semiconductor chip 3 can be sufficiently encapsulated.
In one embodiment of the present disclosure, the grooves at the top of the inner cavity 14 among the plurality of grooves 141 each extend along a first direction, and the first direction is a horizontal direction or a vertical direction. It can be understood that when the extending direction of the plurality of grooves 141 is a horizontal direction, the plurality of grooves 141 are a plurality of strip-shaped grooves parallel to each other, and referring to fig. 2 and 3, the cross section of the plurality of grooves 141 is rectangular. In addition, the cross section of the plurality of grooves 141 may also be trapezoidal, triangular, arc-shaped, or other shapes or combinations thereof. Further, in order to satisfy both the heat dissipation and stress requirements of the semiconductor chip 3, when the leads of the semiconductor chip 3 are located at the opposite sides of the package, the plurality of strip-shaped grooves are disposed to extend between the opposite sides of the package where the leads are located, so that when the semiconductor chip 3 is packaged based on the cavity 14, the fin-shaped heat dissipation structure formed on the surface of the package of the semiconductor chip 3 can be used as a reinforcing rib to satisfy both the heat dissipation and stress requirements of the semiconductor chip 3.
On the other hand, in this embodiment, when the extending direction of the plurality of grooves 141 is a vertical direction, the plurality of grooves 141 are a plurality of columnar grooves spaced apart from each other, and at this time, the cross section of the plurality of grooves 141 may be another shape such as a rectangle, a circle, a semicircle, a triangle, an arbitrary polygon, or a combination thereof.
In another embodiment of the present disclosure, the groove located at the top of the inner cavity 14 among the plurality of grooves 141 extends in both the second direction and the third direction, and both the second direction and the third direction are horizontal directions. It is understood that, at this time, the groove at the top of the inner cavity 14 among the plurality of grooves 141 is a grid-shaped groove or a plurality of nested square-shaped grooves. Thus, when the semiconductor chip 3 is packaged based on the cavity 14, the fin-shaped heat dissipation structure formed on the surface of the package of the semiconductor chip 3 can be used as a reinforcing rib to satisfy both the heat dissipation and stress requirements of the semiconductor chip 3.
Further, a plurality of grooves 141 at the side wall of the inner cavity 14 each extend in the vertical direction. It is understood that, at this time, the plurality of grooves 141 located on the sidewall of the inner cavity 14 are also a plurality of strip-shaped grooves parallel to each other, and the cross-sectional shapes of the plurality of strip-shaped grooves may be other shapes such as rectangular, trapezoidal, triangular, arc-shaped, and the like, or a combination thereof. And further, this scheme is applicable to the case where the pins of the semiconductor chip 3 are located on the lower surface of the package, and at this time, the plurality of strip-shaped grooves are arranged to extend between the upper surface and the lower surface of the package, so that when the semiconductor chip 3 is packaged based on the inner cavity 14, the fin-shaped heat dissipation structure formed on the surface of the package of the semiconductor chip 3 does not affect the pin function of the semiconductor chip, and the separation operation between the packaged package and the packaging mold is facilitated.
In the present disclosure, the cross-sectional shapes of each of the plurality of grooves 141 may be the same or different, and the cross-sectional sizes of any two grooves 141 may be the same or different.
Further, in the present disclosure, the package mold 1 further includes a pressurizing device 15 in the mold cover 11. After the molten-state encapsulant 2 is injected into the material injection hole 122, the encapsulant in the material injection hole 122 can be pressed into at least one inner cavity 14 by the pressurizing device 15, so as to ensure the sufficient encapsulation of the semiconductor chip 3, and ensure that the encapsulant can sufficiently flow into the groove 141 in the inner cavity 14, so that the heat dissipation structure on the encapsulation structure of the semiconductor chip 3 can be accurately molded. At the same time, the size of the pressurizing device 15 should fit the size of the material injection hole 122 as much as possible to avoid the encapsulant 2 from overflowing during pressurization.
In the present disclosure, a packaging process when the semiconductor chip 3 is packaged by using the packaging mold 1 is shown in fig. 1a to 1d, and the specific process is as follows:
first, a substrate 4 is provided; arranging the semiconductor chip 3 on the substrate 4 and electrically connecting the semiconductor chip with the substrate 4; the substrate 4 with the semiconductor chip 3 mounted thereon is then placed in the cavity 14 of the aforementioned package mold 1, and the encapsulant 2 is injected into the package mold 1. Optionally, in this process, the molten encapsulant 2 may be directly injected into the injection hole 122 of the package mold 1, or the solid encapsulant 2 may be first placed into the package mold 1, and the encapsulant 2 is heated to a molten state in the package mold 1 and then pressed into the inner cavity 14.
Then, the molten encapsulant 2 in the injection hole 122 is gradually pressed into the cavity 14 of the package mold 1 and the plurality of grooves 141 in the cavity 14 by the pressing device 15, as shown in fig. 1d, so as to integrally form an encapsulant with a heat dissipation structure, and the semiconductor chip 3 is covered by the encapsulant, thereby completing the chip package.
Furthermore, the chip packaging method also comprises the step of cutting along the position of the preset plane size of the semiconductor chip package so as to remove useless parts in the package and finally form a package body meeting the specification.
In the present disclosure, the formed package includes: a substrate 4, a semiconductor chip and a packaging colloid. The semiconductor chip is disposed on the substrate 4 and electrically connected to the substrate 4. The packaging colloid comprises a packaging colloid main body and an integrated fin-shaped heat dissipation structure formed on the outer surface of the packaging colloid main body, the packaging colloid main body wraps the semiconductor chip 3, and the fin-shaped heat dissipation structure is used for increasing the heat dissipation capacity of the semiconductor chip 3.
Further, the heat dissipation structure is located on the upper surface and/or the side surface of the encapsulant, and the specific structure follows the actual structure of the top of the cavity 14 and/or the sidewall groove 141 in the package mold 1.
Illustratively, in one embodiment of the present invention, as shown in fig. 5 and 6, the heat dissipation structure 311 on the upper surface of the encapsulant 31 is a plurality of strip-shaped heat sinks (or fins) extending in a horizontal direction and parallel to each other, and each heat sink has a rectangular cross-sectional shape. In addition, the cross section of each heat sink may also be in other shapes such as trapezoid, triangle, arc, etc., or a combination thereof, which is not limited by the present invention. Further, the heat dissipation structure 311 on the upper surface of the encapsulant 31 may also be a grid-shaped heat sink extending along the horizontal direction, or a plurality of nested rectangular heat sinks extending along two different horizontal directions. Thus, the heat sink can be used as a reinforcing rib to satisfy the heat dissipation and stress requirements of the semiconductor chip 3.
In another embodiment of the present invention, the heat dissipation structure 311 is a plurality of columnar heat dissipation columns extending in a vertical direction and spaced apart from each other. In this case, the cross section of each heat sink may be rectangular, circular, arc, triangular, any polygon, or other shapes or combinations thereof, which is not limited in the present invention.
Further, as shown in fig. 7, the heat dissipation structure 311 located on the side of the encapsulant 31 is a plurality of strip-shaped heat sinks extending in the vertical direction and parallel to each other, and each heat sink has a rectangular cross-sectional shape. In addition, the cross section of each heat sink may also be in other shapes such as trapezoid, triangle, arc, etc., or a combination thereof, which is not limited by the present invention. It should be noted that, when the heat dissipation structure 311 is located on the side surface of the package colloid 31, the heat dissipation structure 311 should be disposed in a region where the side surface of the package body does not conflict with the leads of the semiconductor chip, for example, this scheme is applicable to a case where the leads of the semiconductor chip 3 are located on the lower surface of the package body.
It is understood that the cross-sectional shape of each fin or heat-dissipating stud in the heat-dissipating structure 311 may be the same or different, and the cross-sectional dimensions of any two fins or heat-dissipating studs may be the same or different.
Here, the package body 31 on the package body is made into a fin-shaped heat dissipation structure, which can increase the area of the heat dissipation area on the top and/or side thereof, and it can be understood that the larger the sum of the area of the side surface and the area of the top surface of the heat dissipation plate or the heat dissipation column in the fin-shaped heat dissipation structure 311 is, the stronger the heat dissipation capability of the semiconductor chip is.
In conclusion, the grooves are designed on the upper surface and/or the side surface of the inner cavity of the packaging mold, so that after the packaging material is injected, the heat dissipation area of the packaging body of the semiconductor chip can be increased, the heat dissipation capability is improved, and the temperature conservation of chip packaging is facilitated to be reduced. Meanwhile, the heat dissipation structure of the packaging body is integrally formed with the packaging main body of the packaging colloid during the injection molding of the packaging material, so that the packaging method is simpler, and the universality and the operability are higher.
On the other hand, based on the fin-shaped heat dissipation structure formed by the parallel strip-shaped grooves or the nested square-shaped grooves arranged in the inner cavity of the packaging mold on the surface of the packaging body of the chip, the reinforcing ribs can be formed on the surface of the semiconductor chip, so that the semiconductor chip can better take the requirements of heat dissipation and stress into account.
It should be noted that, herein, a direction parallel to the upper surface of the cavity 14 in the package mold may be defined as a horizontal direction, and a direction perpendicular to the upper surface of the cavity 14 in the package mold may be defined as a vertical direction.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (11)
1. A packaging mold for packaging a semiconductor chip, wherein the packaging mold comprises:
an inner cavity for accommodating a semiconductor chip;
a passage for communicating with the lumen;
the material injection hole is communicated with the channel; and
a plurality of grooves disposed on the top and/or sidewalls of the inner cavity corresponding to regions of the semiconductor chip,
and after the inner cavity is filled with the packaging material, the packaging material encapsulates the semiconductor chip to form a packaging body, and a fin-shaped heat dissipation structure is formed in the plurality of grooves.
2. The packaging mold of claim 1, wherein the grooves at the top of the inner cavity of the plurality of grooves are a plurality of strip-shaped grooves parallel to each other.
3. The package mold of claim 2, wherein the semiconductor chip comprises a plurality of leads at opposite sides of the package body, the plurality of strip-shaped grooves extending between the opposite sides.
4. The package mold of claim 1, wherein the recess of the plurality of recesses at the top of the cavity is a plurality of cylindrical recesses spaced apart from each other.
5. The package mold of claim 1, wherein the grooves of the plurality of grooves at the top of the cavity are grid grooves or a plurality of nested square grooves.
6. The packaging mold of claim 1, wherein the grooves in the sidewalls of the cavity are strip-shaped grooves parallel to each other.
7. The package mold of claim 6, wherein the semiconductor chip comprises a plurality of leads on a lower surface of the package body, the plurality of strip-shaped grooves extending between the upper surface and the lower surface of the package body.
8. The packaging mold of any of claims 1-5, wherein a first distance is provided between a lower surface of the plurality of recesses at the top of the cavity and an upper surface of the semiconductor chip received in the cavity.
9. The package mold of any of claims 1, 6, and 7, wherein a second distance is provided between an outer surface of the plurality of grooves located on the sidewall of the cavity and a side of the semiconductor chip received in the cavity.
10. A package formed via the package mold package of any one of claims 1-9, wherein the package comprises:
a substrate;
the semiconductor chip is arranged on the substrate and is electrically connected with the substrate;
and the packaging colloid is used for coating the semiconductor chip, and a fin-shaped heat dissipation structure is integrally formed on the upper surface and/or the side surface of the packaging colloid.
11. A chip packaging method comprises the following steps:
providing a substrate;
arranging a semiconductor chip on the substrate and electrically connecting the semiconductor chip with the substrate;
placing a substrate mounted with a semiconductor chip in an inner cavity of a packaging mold according to any one of claims 1 to 9, and injecting a packaging material into the packaging mold;
and pressing the packaging material into the inner cavity of the packaging mold to integrally form the packaging colloid with the heat dissipation structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202110696634.5A CN113921409A (en) | 2021-06-23 | 2021-06-23 | Packaging mold, packaging body and packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110696634.5A CN113921409A (en) | 2021-06-23 | 2021-06-23 | Packaging mold, packaging body and packaging method |
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| CN113921409A true CN113921409A (en) | 2022-01-11 |
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| CN202110696634.5A Pending CN113921409A (en) | 2021-06-23 | 2021-06-23 | Packaging mold, packaging body and packaging method |
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| CN104409368A (en) * | 2014-12-17 | 2015-03-11 | 大连泰一精密模具有限公司 | Method for packaging semiconductor combination device by packaging mould |
| CN109065511A (en) * | 2018-08-15 | 2018-12-21 | 王晓勇 | A kind of semiconductor package part and heat dissipating method with radiator structure |
| CN210897249U (en) * | 2019-11-20 | 2020-06-30 | 深圳市可易亚半导体科技有限公司 | MOS pipe packaging structure of high stability |
| CN112420628A (en) * | 2019-08-22 | 2021-02-26 | 三星电子株式会社 | Semiconductor package |
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2021
- 2021-06-23 CN CN202110696634.5A patent/CN113921409A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0686347U (en) * | 1993-05-14 | 1994-12-13 | 株式会社三協精機製作所 | Heat dissipation package such as IC |
| JP2005116556A (en) * | 2003-10-02 | 2005-04-28 | Fuji Electric Fa Components & Systems Co Ltd | Manufacturing method and installation method of resin-encapsulated semiconductor device |
| CN101303983A (en) * | 2007-05-11 | 2008-11-12 | 矽品精密工业股份有限公司 | Heat dissipation type semiconductor package structure and manufacturing method thereof |
| JP2008124522A (en) * | 2008-02-21 | 2008-05-29 | Fuji Electric Fa Components & Systems Co Ltd | Installation method for resin-encapsulated semiconductor device |
| CN104409368A (en) * | 2014-12-17 | 2015-03-11 | 大连泰一精密模具有限公司 | Method for packaging semiconductor combination device by packaging mould |
| CN109065511A (en) * | 2018-08-15 | 2018-12-21 | 王晓勇 | A kind of semiconductor package part and heat dissipating method with radiator structure |
| CN112420628A (en) * | 2019-08-22 | 2021-02-26 | 三星电子株式会社 | Semiconductor package |
| CN210897249U (en) * | 2019-11-20 | 2020-06-30 | 深圳市可易亚半导体科技有限公司 | MOS pipe packaging structure of high stability |
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Application publication date: 20220111 |