CN113885394B - Airborne data comprehensive acquisition and recording system and method - Google Patents
Airborne data comprehensive acquisition and recording system and method Download PDFInfo
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- CN113885394B CN113885394B CN202111219953.3A CN202111219953A CN113885394B CN 113885394 B CN113885394 B CN 113885394B CN 202111219953 A CN202111219953 A CN 202111219953A CN 113885394 B CN113885394 B CN 113885394B
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Abstract
The invention relates to an airborne data comprehensive acquisition and recording system and method, comprising a comprehensive data acquisition device, a cache recording card and a protection recorder which are positioned on an airborne part, wherein the comprehensive data acquisition device is electrically connected with the protection recorder through an Ethernet, the comprehensive data acquisition device is electrically connected with an on-board power supply, the input end of the comprehensive data acquisition device is used for acquiring on-board signals on the airborne part, the on-board signals comprise a switching signal, a frequency signal, a voltage signal, a vibration signal, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, an audio signal and a video signal, and the acquired data of the on-board signals are packaged according to an IRIG-106 standard and then are sent to the cache recording card and the protection recorder for recording.
Description
Technical Field
The invention relates to an airborne data comprehensive acquisition and recording system and method.
Background
The traditional aircraft mainly uses a mechanical aircraft control and simulation operation system, is gradually replaced by full electronic transmission and control equipment along with the rapid development of technology, and is faced with a large number of mechanical instruments when a pilot, especially a pilot operates the aircraft, and is often required to have abundant personal experiences for acquisition and recording of various complex data, so that the workload is large and the accurate acquisition and analysis of the data are not facilitated.
The comprehensive data acquisition and recording system mainly acquires signals such as on-board switching signals, frequency signals, voltage signals, vibration signals, ARINC429 bus, RS422 bus, MIL-STD-155B bus, AFDX bus, audio signals, video signals and the like, and performs data recording according to IRIG-106 standards.
The CN20110255010. X-type onboard computer data acquisition and recording system provides a system which comprises a computer acquisition recorder, a track guiding display and an onboard power module, wherein the computer acquisition recorder, the track guiding display and the onboard power module are connected to a bus, the computer acquisition recorder comprises a first embedded processor module, an analog parameter acquisition module and a serial data acquisition module which are respectively connected with the bus, the first embedded processor module is also connected with a detachable reinforcement electronic disc, the track guiding display comprises a digital I/O parameter acquisition module and a second embedded processor module which are respectively connected with the bus, the digital I/O parameter acquisition module is connected with a keyboard control interface, and the second embedded processor module is connected with an EL display screen. However, the structure is complex, the test precision is low, and effective recording cannot be realized.
Disclosure of Invention
The invention aims to provide an airborne data comprehensive acquisition and recording system and an airborne data comprehensive acquisition and recording method.
In order to solve the problems, the invention adopts the following technical scheme:
the comprehensive airborne data acquisition and recording system comprises a comprehensive data acquisition device, a cache recording card and a protection recorder which are positioned on an airborne part, wherein the comprehensive data acquisition device is electrically connected with the protection recorder through an Ethernet;
The system comprises an on-board part, a comprehensive data acquisition unit, a cache recording card, a protection recorder, a comprehensive data acquisition unit, a protection recorder and a control unit, wherein the input end of the comprehensive data acquisition unit is electrically connected with an on-board power supply, and is used for acquiring on-board signals on the on-board part, wherein the on-board signals comprise a switch signal, a frequency signal, a voltage signal, a vibration signal, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, an audio signal and a video signal;
the cache record card adopts SATA bus to crosslink with the comprehensive data collector to complete the record of all collected data;
The protection recorder adopts a gigabit Ethernet bus to crosslink with the comprehensive data acquisition unit to complete the recording of important data, wherein the important data comprises data for accident analysis;
an unloading checker and a flying parameter data ground comprehensive analysis processing system are arranged on the ground;
the output end of the unloading checker is electrically connected with the input end of the ground comprehensive analysis processing system of the flying parameter data so as to import data.
As a further improvement of the above technical scheme:
the chassis structure form of the comprehensive data acquisition device adopts a backboard-free form, and communication and power supply among the modules are interconnected through an inter-board connector;
The comprehensive data acquisition device comprises a power supply module, a main control module adopting an integratable cache recording card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switching signal acquisition module, a vibration signal acquisition module, a bus acquisition module and an audio and video acquisition module;
The main control module, the voltage signal acquisition module I, the voltage signal acquisition module II, the switching signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module are respectively provided with
The BIT test capability module is provided with three self-checking modes, including PBIT power-on self-checking, CBIT period self-checking and IBIT maintenance self-checking;
The fault log-in module is used for providing a fault log-in means through the LAN bus, fault information is stored in the nonvolatile memory, and each piece of fault record information must contain time stamp information;
and each module realizes time synchronization by using IRIG-B codes, and time marks are marked by using hardware, so that the time synchronization precision is 100ns.
In the comprehensive data collector, a power supply module comprises a PCU power supply conversion unit, wherein a normal power supply and an emergency power supply are combined and input, and a direct current 28V input voltage is converted into a direct current 24Vd bottom plate voltage;
The voltage range of the normal power supply is 22V-30V, and the voltage range of the emergency power supply is 18V-30V;
the power supply comprises a PSA power supply, an output voltage monitoring and switching control module, a power supply control module and a power supply control module, wherein the PSA power supply is provided with the output voltage monitoring and switching control module which is crosslinked with the NIU module and works under the control of the NIU module, and the output voltage monitoring and switching control module is responsible for switching on, switching off and monitoring different power supply outputs of other modules in the rack;
The system comprises a frame, a NIU module, a CPU module and a PHY module, wherein the NIU module is used for managing power supply in the frame and detecting power distribution faults through internal MII signal crosslinking, the CPU module is used for controlling PSA according to information received from the system so as to provide power for a desired module, and the PHY module is communicated with the system through a LAN channel.
The PCU power supply conversion unit comprises an energy storage capacitor, a holding module, a filtering module and a DC-DC module I, wherein the input end of the filtering module is connected with an external power supply, and the input end of the holding module is respectively connected with the output ends of the energy storage capacitor and the filtering module;
The system comprises a voltage signal acquisition module I for inputting 32 paths of voltage signals, a voltage signal acquisition module II for inputting 32 paths of voltage signals, a switching signal acquisition module for inputting switching signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and/or AFDX signals, and an audio/video acquisition module for inputting audio signals and video signals, wherein the exchange of acquired data is completed through a PCIe bus and a main control module, and the exchange of maintenance information is completed through a LAN bus and the main control module, wherein the maintenance information comprises self-checking information, software upgrading, log information and parameter monitoring;
The main control module is internally integrated with an FPGA integrated circuit, a LAN switch chip, a PCIe switch chip, a CPU, a synchronous signal module and an RTC chip, wherein the PCIe switch chip is respectively exchanged with the voltage signal acquisition module I, the voltage signal acquisition module II, the switching signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module through an IRIG-B channel through a PCIe bus and the input end of the synchronous signal module;
the LAN exchanger chip is used for crosslinking the maintenance information with the unloading verifier through the LAN, and the maintenance log information is stored in the SATA hard disk integrated on the main control module;
the PCIe switch chip exchanges with the CPU through a PCIe bus, and the CPU is electrically connected with the cache record card through a SATA channel;
The synchronous signal module receives an RTC time service signal of the RTC chip;
In the physical link of the PCIe bus, the PCIe link uses an end-to-end data transmission mode, and the sending end and the receiving end both contain TX sending logic and RX receiving logic;
A transmitting link of the receiving end, namely a receiving link of the receiving end, wherein a TX component of the transmitting end is connected with an RX component of the receiving end by using a group of differential signals;
The RX part of the transmitting end is connected to the TX part of the receiving end using another set of differential signals, which link is also called the receiving link of the transmitting end, i.e. the transmitting link of the receiving end;
The PCIe link carries out data transmission through differential signals, the differential signals comprise D+ and D-, and a signal receiving end judges whether a logic 1 or a logic 0 is transmitted by a transmitting end through comparing the difference value of the D+ and D-signals;
The voltage signal acquisition module is provided with a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, CPU and a port PHYI;
The input end of the voltage signal conditioning module is input with 32 paths of voltage signals; the self-checking circuit is respectively and electrically connected with the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit I and the CPU1;
The FPGA integrated circuit I receives the IRIG-B synchronous signal and crosslinks a PCIe bus;
CPU1 cross links LAN signals through port PHYI;
the switch signal acquisition module comprises a switch signal conditioning module, a frequency signal conditioning module, a switch signal self-checking circuit, a switch signal CPU, a switch signal port and a switch signal integrated circuit;
the input end of the switch signal conditioning module receives 96 paths of switch signal inputs, and the output end of the switch signal conditioning module is electrically connected with the switch signal integrated circuit;
the frequency signal conditioning module receives 6 paths of frequency signal input, is crosslinked with the switch signal conditioning module, and the output end of the frequency signal conditioning module is electrically connected with the switch signal integrated circuit.
A switching signal integrated circuit which receives the IRIG-B synchronous signal and links the PCle bus;
A switching signal CPU, which is crosslinked with the switching signal integrated circuit and is connected with the LAN port through a switching signal port;
The switching signal self-checking circuit comprises a switching signal self-checking module, a frequency signal conditioning module and a switching signal CPU;
The vibration data acquisition module is used for receiving a vibration signal, and comprises a vibration signal conditioning module for receiving a receiver azimuth signal, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;
The vibration signal conditioning module is connected with the input end of the vibration circuit FPGA module through the vibration data AD sampling module, and the output end of the azimuth signal conditioning module is connected with the input end of the vibration circuit FPGA module;
the vibration data self-checking circuit self-checking vibration signal conditioning module, the azimuth signal conditioning module, the vibration data AD sampling module and the vibration data CPU.
The bus acquisition module comprises an RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module, a bus FPGA module, a bus self-checking circuit, a bus CPU and a bus PHY;
The input end of the RS422 interface conditioning module is connected with an RS422 bus, the ARINC429 interface conditioning module is connected with an ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected with a MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected with an AFDX bus;
The output end of the RS422 interface conditioning module, the ARINC429 interface conditioning module, the MIL-STD-1553B interface conditioning module and the AFDX bus interface conditioning module is connected with the input end of the bus FPGA module;
the bus FPGA module is connected with the IRIG-B synchronous signal, the PCIe bus and the bus CPU, and the bus CPU is connected with the LAN channel through the bus PHY;
the bus self-checking circuit self-checking RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module and bus CPU;
The audio and video data acquisition module comprises a video signal conditioning module for receiving video signals, an audio signal conditioning module for receiving audio signals, a video acquisition module, an audio and video AD sampling module, an audio and video self-checking circuit, an audio and video FPGA module, an audio and video self-checking circuit, an audio and video CPU and an audio and video PHY;
The audio/video FPGA module is used for receiving an output signal of the video signal conditioning module through the video acquisition module; the audio/video FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU, and the audio/video CPU is connected with the LAN channel through an audio/video PHY;
The audio and video self-checking circuit self-checking video signal conditioning module, the audio signal conditioning module and the audio and video CPU.
The system comprises a main control module, a cache recording card, a data processing module and a data processing module, wherein the cache recording card is integrated on the main control module and is communicated with the main control module by adopting a SATA bus;
The protection recorder adopts a fixed memory, adopts a recording mode of cyclic recording and is provided with a gigabit Ethernet interface;
the system comprises a main control module, a cache recording card, a data processing module and a data processing module, wherein the cache recording card is integrated on the main control module and is communicated with the main control module by adopting a SATA bus;
The protection recorder adopts a fixed memory, and the recording mode adopts cyclic recording and has a gigabit Ethernet interface.
The collector comprises a plurality of box bodies, perforations on the box bodies, and the box bodies are detachably connected in a separated way, wherein the collector comprises one of the following schemes;
the first scheme is that a connecting rod penetrates through the through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between the box bodies;
the upper and lower parts of the outer side walls at two sides of the box body are respectively and transversely provided with a transverse clamping groove, a transverse connecting block is arranged between the side walls of the adjacent box bodies, two sides of the transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and the transverse clamping grooves are provided with clamping groove holes for connecting positioning bolts through threads;
The third scheme is that a connecting rod penetrates through the through hole, a gasket is sleeved on the connecting rod, and the gasket is arranged between the box bodies; the end parts of the connecting rods are provided with nuts and washers, the upper and lower parts of the outer side walls at two sides of the box body are respectively and transversely provided with a transverse clamping groove, a transverse connecting block is arranged between the side walls of the adjacent box bodies, two sides of the transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, and the transverse clamping grooves are provided with clamping groove holes for connecting positioning bolts through threads;
The four scheme is that transverse clamping grooves are respectively and transversely formed in the upper side wall and the lower side wall of the outer side of the two sides of the box body, transverse connecting blocks are arranged between the side walls of the adjacent box bodies, two sides of each transverse connecting block are respectively inserted into the corresponding transverse clamping grooves, clamping holes are formed in the transverse clamping grooves and are connected with positioning bolts in a threaded mode, the lower ends of the positioning bolts are connected to the transverse connecting blocks, a plurality of alternative double-sided transverse clamping grooves which are the same as the width of the box bodies are reserved, and when a certain collector is taken down, the collector is installed at the position through the double-sided transverse clamping grooves, so that the position of the whole module is kept unchanged.
An airborne data comprehensive acquisition and recording method, by means of an airborne data comprehensive acquisition and recording system,
Firstly, the on-board signal is sent to the comprehensive data collector, then the collector stores the signal in the cache record card and is crosslinked with the unloading verifier, and finally, the unloading verifier leads the data into the ground comprehensive analysis processing system of the flight parameters.
As a further improvement of the above technical scheme:
In the work of the comprehensive data acquisition device, the main control module executes a PCIe switch function to exchange data, performs a LAN switch function, performs a maintenance function, realizes a time synchronization function module, generates IRIG-B code output through RTC or GPS time service, realizes a hardware time marking function through an FPGA, exchanges data with the main control module through a PCIe bus, and realizes module self-checking and software upgrading through a LAN;
the voltage signal acquisition module is used for acquiring voltage signals, the voltage signal input range is set through software, the hardware time marking function is realized through an FPGA, the data exchange with the main control module is realized through a PCIe bus, and the module self-checking and the software upgrading are realized through a LAN;
The switching signal acquisition module acquires switching signals, acquires frequency signals, performs a hardware time marking function through an FPGA, realizes data exchange with the main control module through a PCIe bus, and realizes module self-checking and software upgrading through a LAN;
The vibration data acquisition module acquires azimuth angle signals, acquires vibration signals, realizes a hardware time marking function through an FPGA, realizes data exchange with the main control module through a PCIe bus, and realizes module self-checking and software online upgrading through a LAN;
The bus acquisition module is used for acquiring an RS422 bus, 8 ARINC429 buses, dual-redundancy MIL-STD-1553B buses and dual-redundancy AFDX buses, realizing a hardware time marking function through an FPGA, realizing data exchange with a main control module through a PCIe bus, realizing module self-checking and software online upgrading through a LAN;
The audio and video data acquisition module is used for acquiring video signals, 4 paths of audio signals, realizing a hardware time marking function through an FPGA, realizing data exchange with the main control module through a PCIe bus, and realizing module self-checking and software online upgrading through a LAN.
The invention has reasonable design, low cost, firmness, durability, safety, reliability, simple operation, time and labor saving, fund saving, compact structure and convenient use.
Drawings
Fig. 1 is a block diagram of the system components of the present invention.
Fig. 2 is a cross-linked block diagram of the internal modules of the harvester of the invention.
FIG. 3 is a physical link diagram of the PCIe bus of the present invention.
FIG. 4 is a diagram of PCIe bus specification versus bus frequency and encoding of the present invention.
FIG. 5 is a peak bandwidth diagram of the PCIe bus of the present invention.
Fig. 6 is an IRIG B code diagram of the present invention.
Fig. 7 is a cross-sectional view of the internal maintenance bus of the harvester of the invention.
Fig. 8 is a schematic block diagram of a voltage signal acquisition module of the present invention.
Fig. 9 is a functional block diagram of a power conversion module of the present invention.
Fig. 10 is a schematic block diagram of a master control module of the present invention.
Fig. 11 is a schematic diagram of a switching signal acquisition module according to the present invention.
Fig. 12 is a schematic block diagram of a vibration data acquisition module of the present invention.
Fig. 13 is a schematic block diagram of a bus acquisition module of the present invention.
Fig. 14 is a schematic block diagram of an audio/video data acquisition module according to the present invention.
FIG. 15 is a schematic block diagram of a cache memory card of the present invention.
FIG. 16 is a table diagram of a flight parameter recording system of the present invention.
FIG. 17 is a table diagram of an in-flight integrated data acquisition system and vibration monitoring system of the present invention.
Fig. 18 is a schematic view of the collector structure of the present invention.
Fig. 19 is a schematic view of the collector connection structure of the present invention.
Wherein, 1, a box body, 2, a perforation, 3, a connecting rod, 4, a transverse clamping groove, 5, a transverse connecting block, 6, a positioning bolt, 7, and a clamping groove hole.
Detailed Description
1-19, The comprehensive data acquisition and recording system of the embodiment comprises a comprehensive data acquisition device, a cache recording card and a protection recorder which are positioned on an onboard part, wherein the comprehensive data acquisition device is electrically connected with the protection recorder through an Ethernet;
The system comprises an on-board part, a comprehensive data acquisition unit, a cache recording card, a protection recorder, a comprehensive data acquisition unit, a protection recorder and a control unit, wherein the input end of the comprehensive data acquisition unit is electrically connected with an on-board power supply, and is used for acquiring on-board signals on the on-board part, wherein the on-board signals comprise a switch signal, a frequency signal, a voltage signal, a vibration signal, an ARINC429 bus, an RS422 bus, an MIL-STD-155B bus, an AFDX bus, an audio signal and a video signal;
the cache record card adopts SATA bus to crosslink with the comprehensive data collector to complete the record of all collected data;
The protection recorder adopts a gigabit Ethernet bus to crosslink with the comprehensive data acquisition unit to complete the recording of important data, wherein the important data comprises data for accident analysis;
an unloading checker and a flying parameter data ground comprehensive analysis processing system are arranged on the ground;
The output end of the unloading checker is electrically connected with the input end of the ground comprehensive analysis processing system of the flying parameter data so as to import data;
The case structure of the comprehensive data collector adopts a backboard-free form, and communication and power supply among modules are interconnected through an inter-board connector. This approach presents challenges for high speed buses, which require multiple connectors from the main control board to the most remote acquisition board, and signal integrity presents certain difficulties.
One embodiment of the invention adopts long screws for mutual fixation, and the mode has better maintainability. Each module adopts a structural sealing design, and the EMC performance is relatively good.
The comprehensive data acquisition device is based on a modularized case and comprises a power supply module, a main control module adopting an integratable cache recording card, a voltage signal acquisition module I, a voltage signal acquisition module II, a switching signal acquisition module, a vibration signal acquisition module, a bus acquisition module and an audio and video acquisition module;
The main control module, the voltage signal acquisition module I, the voltage signal acquisition module II, the switching signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module are respectively provided with
The BIT test capability module is provided with three self-checking modes, including PBIT power-on self-checking, CBIT period self-checking and IBIT maintenance self-checking;
The fault log-in module is used for providing a fault log-in means through the LAN bus, fault information is stored in the nonvolatile memory, and each piece of fault record information must contain time stamp information;
The time synchronization module is used for realizing time synchronization by using IRIG-B codes, and time marks are marked by using hardware, so that the time synchronization precision is 100ns;
The power module comprises a PCU power supply conversion unit, wherein a normal power supply and an emergency power supply are combined and input, and a direct current 28V input voltage is converted into a direct current 24Vd bottom plate voltage;
The voltage range of the normal power supply is 22V-30V, and the voltage range of the emergency power supply is 18V-30V;
the power supply comprises a PSA power supply, an output voltage monitoring and switching control module, a power supply control module and a power supply control module, wherein the PSA power supply is provided with the output voltage monitoring and switching control module which is crosslinked with the NIU module and works under the control of the NIU module, and the output voltage monitoring and switching control module is responsible for switching on, switching off and monitoring different power supply outputs of other modules in the rack;
The system comprises an NIU module, a CPU module, a PHY module, a Local Area Network (LAN) module, a power supply module and a control module, wherein the NIU module is crosslinked through an internal MII signal, and the CPU module and the PHY module are used for managing the power supply in the rack and detecting the power supply distribution fault;
The PCU power supply conversion unit comprises an energy storage capacitor, a holding module, a filtering module and a DC-DC module I, wherein the input end of the filtering module is connected with an external power supply, and the input end of the holding module is respectively connected with the output ends of the energy storage capacitor and the filtering module;
The system comprises a voltage signal acquisition module I for inputting 32 paths of voltage signals, a voltage signal acquisition module II for inputting 32 paths of voltage signals, a switching signal acquisition module for inputting switching signals and frequency signals, a vibration signal acquisition module for inputting vibration signals, a bus acquisition module for inputting ARINC429, RS422, MIL-STD-1553B and/or AFDX signals, and an audio/video acquisition module for inputting audio signals and video signals, wherein the exchange of acquired data is completed through a PCIe bus and a main control module, and the exchange of maintenance information is completed through a LAN bus and the main control module, wherein the maintenance information comprises self-checking information, software upgrading, log information and parameter monitoring;
The main control module is internally integrated with an FPGA integrated circuit, a LAN switch chip, a PCIe switch chip, a CPU, a synchronous signal module and an RTC chip, wherein the PCIe switch chip is respectively exchanged with the voltage signal acquisition module I, the voltage signal acquisition module II, the switching signal acquisition module, the vibration signal acquisition module, the bus acquisition module and the audio and video acquisition module through an IRIG-B channel through a PCIe bus and the input end of the synchronous signal module;
the LAN exchanger chip is used for crosslinking the maintenance information with the unloading verifier through the LAN, and the maintenance log information is stored in the SATA hard disk integrated on the main control module;
the PCIe switch chip exchanges with the CPU through a PCIe bus, and the CPU is electrically connected with the cache record card through a SATA channel;
The synchronous signal module receives an RTC time service signal of the RTC chip;
In the physical link of the PCIe bus, the PCIe link uses an end-to-end data transmission mode, and the sending end and the receiving end both contain TX sending logic and RX receiving logic;
A transmitting link of the receiving end, namely a receiving link of the receiving end, wherein a TX component of the transmitting end is connected with an RX component of the receiving end by using a group of differential signals;
The RX part of the transmitting end is connected to the TX part of the receiving end using another set of differential signals, which link is also called the receiving link of the transmitting end, i.e. the transmitting link of the receiving end;
The PCIe link carries out data transmission through differential signals, the differential signals comprise D+ and D-, and the signal receiving end judges whether logic '1' or logic '0' is sent by the sending end by comparing the difference value of the D+ and D-signals.
The main control module realizes PCIe exchanger functions, namely, data exchange with other functional modules, ports are not less than 7, LAN exchanger functions, namely, maintenance functions are realized, ports are not less than 8, 3) a CPU adopts a PowerPC series processor, an operating system adopts VxWorks of a wind river, one path of gigabit Ethernet is realized for interfacing with a protection recorder, two paths of SATA are realized, one path of SATA is used for interfacing with a cache record card, the other path of SATA is used for storing log information and the like, a time synchronization functional module is realized, namely, 8 paths of IRIG-B codes are generated for other functional modules through RTC or GPS time service, a hardware time marking function is realized through an FPGA, the time synchronization precision can reach 100ns, data exchange with the main control module is realized through a PCIe bus, and functions such as module self-checking and software upgrading are realized through a LAN.
The high-speed differential signal electrical specification requires that its transmitting end be connected in series with a capacitor for AC coupling. This capacitance is also referred to as AC coupling capacitance. Differential signals are more resistant to interference than single-ended signals because they require "equal length", "equal width", "close together" and are on the same layer when routed. Thus the external noise will be "co-valued" and "simultaneously" loaded onto both the D + and D-signals, the difference value of which is ideally 0, with less impact on the logical value of the signals. So that the differential signal can use a higher bus frequency.
In addition, the differential signal is used to effectively suppress electromagnetic interference EMI (Electro MAGNETIC INTERFERENCE). Since the differential signal D + is very close to D-, and the signals are equal in amplitude and opposite in polarity. The amplitude of the coupling electromagnetic field between the two wires and the ground wire is equal, and the coupling electromagnetic fields cancel each other, so that the differential signal has smaller electromagnetic interference to the outside. The disadvantages of differential signals are, of course, apparent, in that one differential signal uses two signals to carry one bit of data, and in that the wiring of the differential signal is relatively strict.
The bus frequencies used by different PCIe bus specifications are not the same, and the data encoding modes used by the PCIe bus specifications are also different. The PCIe buses V1.X and V2.0 specification use 8/10b encoding in the physical layer, i.e., 8 bits of valid data are contained in 10 bits on the PCIe link, while the V3.0 specification uses 128/130b encoding, i.e., 128 bits of valid data are contained in 130 bits on the PCIe link. As shown by the graph, the V3.0 specification uses a bus frequency of only 4GHz, but has an effective bandwidth twice that of V2. X. Taking the v2.x specification as an example, the peak bandwidth that can be provided by PCIe links of different widths is illustrated.
The effective bandwidth provided by the PCIe bus is still much higher than the PCI bus. PCIe buses also have their weaknesses, with the most prominent problem being transfer latency. PCIe links use a serial approach to data transfer, however, the data buses are still parallel within the chip, so PCIe link interfaces require serial-to-parallel conversion, which creates a large latency. In addition, the data packets of the PCIe bus need to pass through the transaction layer, the data link layer and the physical layer, and these data packets will also cause delay when traversing these layers.
The data transfer between physical links of the PCIe bus uses a clock-based synchronous transfer mechanism, but there is no clock line on the physical link, the receiving end of the PCIe bus contains a clock recovery module CDR (Clock Data Recovery), and the CDR extracts the receive clock from the receive message, so that synchronous data transfer is performed.
The master control module receives GPS signals or adopts a built-in RTC clock to form unified synchronous signals, the unified synchronous signals are sent to other modules for use, and the synchronous signals adopt IRIG-B codes.
Since the Global Positioning System (GPS) has become a time distribution system which is globally shared and has extremely high accuracy, GPS-based time synchronization signals are widely used in various fields. Currently, many manufacturers have introduced GPS-based synchronous time synchronization devices. These devices provide accurate time signals in a variety of ways, such as pulse synchronization, serial information synchronization, IRIG-B code information synchronization, etc., which each have advantages and disadvantages. The IRIG-B code is used as an international universal time code, time is accurately timed, a time-timed loop is simplified, and complete absolute time scale information is contained, so that the IRIG-B code is widely applied. The code is widely applied to missile, aerospace, telemetry and other system equipment, and has high implementation precision and high stability.
IRIG codes have a total of 4 parallel binary time code formats and 6 serial binary time code formats, of which the most commonly used is the IRIG-B time code format, which transmits time information at a frequency once per second, including not only second pulse information but also absolute time information including year, day, time, minute, second, binary second day, etc.
As shown, it is a serial time code of one frame per second, each symbol having a total width of 10ms, and one time frame period including 100 symbols is pulse width coded. Each symbol has 3 patterns of binary 0, 1 and position identifier. The method is divided into 3 fields and is characterized in that the 1 st field is annual time (year, day, time, minute and second), the 2 nd field is a control function field, the 3 rd field is time information in one day which is directly expressed by a binary second symbol, and the cycle is 1 time every 24 hours. The "on time" reference point of the symbol is its pulse leading edge, the reference mark of the time frame is composed of a position identification mark and adjacent reference symbols, the pulse width is 8ms, every 10 symbols have a position identification mark, so that 10 position identification marks in 1 second are respectively P1, P2, P3, P9 and P0, which are 8ms pulse width, PR is the frame reference point, and the pulse widths of binary "1" and "0" are respectively 5ms and 2ms.
The voltage signal acquisition module is provided with a voltage signal conditioning module, an AD sampling module, a self-checking circuit, an FPGA integrated circuit I, CPU and a port PHYI;
The input end of the voltage signal conditioning module is input with 32 paths of voltage signals; the self-checking circuit is respectively and electrically connected with the voltage signal conditioning module, the AD sampling module, the FPGA integrated circuit I and the CPU1;
The FPGA integrated circuit I receives the IRIG-B synchronous signal and crosslinks a PCIe bus;
CPU1 cross links LAN signals through port PHYI;
the voltage signal acquisition module has the implementation functions of 1) acquiring 32 paths of voltage signals, 2) enabling the voltage signal input range to be set by software, 3) achieving a hardware time marking function through an FPGA, enabling the time synchronization precision to be 100ns, 4) achieving data exchange with a main control module through a PCIe bus, and 5) achieving the functions of module self-checking, software upgrading and the like through a LAN.
The switch signal acquisition module comprises a switch signal conditioning module, a frequency signal conditioning module, a switch signal self-checking circuit, a switch signal CPU, a switch signal port and a switch signal integrated circuit;
the input end of the switch signal conditioning module receives 96 paths of switch signal inputs, and the output end of the switch signal conditioning module is electrically connected with the switch signal integrated circuit;
The frequency signal conditioning module receives 6 paths of frequency signal input, is crosslinked with the switch signal conditioning module, and the output end of the frequency signal conditioning module is electrically connected with the switch signal integrated circuit;
a switching signal integrated circuit which receives the IRIG-B synchronous signal and links the PCle bus;
A switching signal CPU, which is crosslinked with the switching signal integrated circuit and is connected with the LAN port through a switching signal port;
The switching signal self-checking circuit comprises a switching signal self-checking module, a frequency signal conditioning module and a switching signal CPU;
The switch signal acquisition module has the implementation functions of 1) acquiring 96 paths of switch signals, 2) acquiring 6 paths of frequency signals, 3) realizing a hardware time marking function through an FPGA, wherein the time synchronization precision can reach 100ns, 4) realizing data exchange with a main control module through a PCIe bus, and 5) realizing functions of module self-checking, software upgrading and the like through a LAN.
The vibration data acquisition module is used for receiving a vibration signal, and comprises a vibration signal conditioning module for receiving a receiver azimuth signal, a vibration data AD sampling module, a vibration data self-checking circuit, a vibration circuit FPGA module, an oscillation data CPU and a vibration data PHY port;
The vibration signal conditioning module is connected with the input end of the vibration circuit FPGA module through the vibration data AD sampling module, and the output end of the azimuth signal conditioning module is connected with the input end of the vibration circuit FPGA module;
The oscillation data CPU is crosslinked with the vibration circuit FPGA module and is connected with the LAN channel through the vibration data PHY port; the vibration circuit FPGA module receives the IRIG-B synchronous signal and crosslinks the PCle bus, and the vibration data self-checking circuit self-checking vibration signal conditioning module, azimuth signal conditioning module, vibration data AD sampling module and vibration data CPU;
The vibration data acquisition module has the implementation functions of 1) acquiring 4 paths of azimuth signals, 2) acquiring 16 paths of vibration signals, 3) realizing a hardware time marking function through an FPGA, wherein the time synchronization precision can reach 100ns, 4) realizing data exchange with a main control module through a PCIe bus, 5) realizing the functions of module self-checking, software online upgrading and the like through a LAN.
The bus acquisition module comprises an RS422 interface conditioning module, an ARINC429 interface conditioning module, an MIL-STD-1553B interface conditioning module, an AFDX bus interface conditioning module, a bus FPGA module, a bus self-checking circuit, a bus CPU and a bus PHY;
The input end of the RS422 interface conditioning module is connected with an RS422 bus, the ARINC429 interface conditioning module is connected with an ARINC429 bus, the MIL-STD-1553B interface conditioning module is connected with a MIL-STD-1553B bus, and the AFDX bus interface conditioning module is connected with an AFDX bus;
The output end of the RS422 interface conditioning module, the ARINC429 interface conditioning module, the MIL-STD-1553B interface conditioning module and the AFDX bus interface conditioning module is connected with the input end of the bus FPGA module;
the bus FPGA module is connected with the IRIG-B synchronous signal, the PCIe bus and the bus CPU, and the bus CPU is connected with the LAN channel through the bus PHY;
the bus self-checking circuit self-checking RS422 interface conditioning module, ARINC429 interface conditioning module, MIL-STD-1553B interface conditioning module, AFDX bus interface conditioning module and bus CPU;
the implementation functions are that 1) 8 paths of RS422 buses are collected, 2) 8 paths of ARINC429 buses are collected, 3) 1 paths of dual-redundancy MIL-STD-1553B buses are collected, 4) 1 paths of dual-redundancy AFDX buses are collected, 5) a hardware time marking function is achieved through an FPGA, time synchronization accuracy can reach 100ns, 6) data exchange with a main control module is achieved through a PCIe bus, and 7) functions of module self-checking, software online upgrading and the like are achieved through a LAN.
The audio and video data acquisition module comprises a video signal conditioning module for receiving video signals, an audio signal conditioning module for receiving audio signals, a video acquisition module, an audio and video AD sampling module, an audio and video self-checking circuit, an audio and video FPGA module, an audio and video self-checking circuit, an audio and video CPU and an audio and video PHY;
The audio/video FPGA module is used for receiving an output signal of the video signal conditioning module through the video acquisition module; the audio/video FPGA module is connected with an IRIG-B synchronous signal, a PCIe bus and a bus CPU, and the audio/video CPU is connected with the LAN channel through an audio/video PHY;
the audio and video self-checking circuit self-checking video signal conditioning module, the audio signal conditioning module and the audio and video CPU;
The audio and video data acquisition module has the implementation functions of 1) acquiring 2 paths of video signals, 2) acquiring 4 paths of audio signals, 3) realizing a hardware time marking function through an FPGA, wherein the time synchronization precision can reach 100ns, 4) realizing data exchange with a main control module through a PCIe bus, and 5) realizing the functions of module self-checking, software online upgrading and the like through a LAN.
The system comprises a main control module, a cache recording card, a data processing module and a data processing module, wherein the cache recording card is integrated on the main control module and is communicated with the main control module by adopting a SATA bus;
The memory capacity is not less than 256G. Because the cache record card is often required to unload record data, the cache record card is required to be frequently plugged and unplugged, and the common SATA connector does not have such durability, the SATA connector is converted into the HJ30J-18 high-reliability rectangular connector through the adapter plate, the HJ30J-18 transmission speed can reach 3Gbps, and the SATA signal transmission requirement is met. And the FLASH hard disk selects aluminum alloy for reinforcement of the shell, so that the reliability of the product is improved.
The protection recorder adopts a fixed memory, the recording mode adopts a cyclic recording mode, a gigabit Ethernet interface is provided, and the crash resistance accords with TSO-C123b and TSO-C124b standards or other related standards.
The system software architecture is characterized in that an operating system adopts VxWorks6.6 or more, a data recording format adopts IRIG-106 standard, and a PCIe communication protocol is adopted to realize data exchange between an acquisition module and a main control module in the acquisition device, so that the aim of plug and play is realized.
The collector comprises a plurality of box bodies 1, perforations 2 on the box bodies 1, and the box bodies 1 are detachably connected in a separated mode;
according to the scheme I, the connecting rod 3 penetrates through the through hole 2, the gasket is sleeved on the connecting rod 3 and arranged between the box bodies 1, and nuts and the gasket are arranged at the end parts of the connecting rod 3, so that the modularized design is realized, and the assembly, disassembly and maintenance are convenient.
In the scheme II, transverse clamping grooves 4 are respectively and transversely formed in the upper and lower parts of the outer side walls of two sides of the box body 1, transverse connecting blocks 5 are arranged between the side walls of the adjacent box bodies 1, two sides of each transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, clamping groove holes 7 are formed in the transverse clamping grooves 4 and are connected with positioning bolts 6 through threads, and the lower ends of the positioning bolts 6 are connected to the transverse connecting blocks 5. Scheme one, there is when a certain collector module damages, needs take off whole, needs reserve lateral part connecting rod removal space moreover, uses inconveniently.
The third scheme is that a connecting rod 3 penetrates through the through hole 2, a gasket is sleeved on the connecting rod 3 and is arranged between the box bodies 1, nuts and gaskets are arranged at the end parts of the connecting rod 3, transverse clamping grooves 4 are respectively and transversely arranged on the upper side and the lower side of the outer side walls of the two sides of the box bodies 1, transverse connecting blocks 5 are arranged between the side walls of the adjacent box bodies 1, the two sides of each transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, clamping grooves 7 are arranged on the transverse clamping grooves 4 and are connected with positioning bolts 6 through threads, and the lower ends of the positioning bolts 6 are connected with the transverse connecting blocks 5. When the requirement on stability is high, the first scheme and the second scheme are combined for use, so that the overall stability of the box body is enhanced, and meanwhile, the convenient detachability is maintained.
The four scheme is that transverse clamping grooves 4 are respectively and transversely formed in the upper side wall and the lower side wall of the outer side of the two sides of the box body 1, transverse connecting blocks 5 are arranged between the side walls of the adjacent box bodies 1, two sides of each transverse connecting block 5 are respectively inserted into the corresponding transverse clamping grooves 4, clamping groove holes 7 are formed in the transverse clamping grooves 4 and are connected with positioning bolts 6 in a threaded mode, the lower ends of the positioning bolts 6 are connected to the transverse connecting blocks 5, a plurality of alternative double-sided transverse clamping grooves which are equal in width to the box body 1 are reserved, and after a certain collector is taken down, the collector is installed at the position through the double-sided transverse clamping grooves, so that the position of the whole module is kept unchanged.
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| CN114995887A (en) * | 2022-05-26 | 2022-09-02 | 中国航空工业集团公司沈阳飞机设计研究所 | Synchronous starting recording method for double data cards |
| CN115577663A (en) * | 2022-07-12 | 2023-01-06 | 天津津航计算技术研究所 | A VPX architecture integrated display device with BIT detection |
| CN117671817B (en) * | 2024-01-31 | 2024-04-16 | 珠海遥测科技有限公司 | IRIG 106-based information display method, device, system and medium |
| CN118610834A (en) * | 2024-05-27 | 2024-09-06 | 济南腊山航空科技有限公司 | A special situation recorder processing system |
| CN119135823A (en) * | 2024-11-12 | 2024-12-13 | 西安中飞航空测试技术发展有限公司 | An airborne CameraLink optical fiber video to network transmission device |
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