CN113643992A

CN113643992A - Method for manufacturing semiconductor device and method for manufacturing power conversion device

Info

Publication number: CN113643992A
Application number: CN202110435484.2A
Authority: CN
Inventors: 石川悟
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 2020-04-27
Filing date: 2021-04-22
Publication date: 2021-11-12
Also published as: JP7308788B2; JP2021174894A

Abstract

The present application relates to a method for manufacturing a semiconductor device and a method for manufacturing a power conversion device. Generation of solder shrinkage cavity directly under the insulating substrate at the position of the semiconductor element is suppressed. In a method for manufacturing a semiconductor device, a semiconductor element is bonded to an upper surface of an insulating substrate via a 1 st bonding material, a heat dissipation plate is bonded to a lower surface of the insulating substrate via a 2 nd bonding material, a heat conduction jig is disposed in contact with the lower surface of the heat dissipation plate, the 1 st bonding material and the 2 nd bonding material are heated, the heat conduction jig is cooled in a state where the heat conduction jig is in contact with the lower surface of the heat dissipation plate, the heat conduction jig has a low heat conduction portion which is disposed at a position not overlapping with the semiconductor element in a plan view and has a lower heat conductivity than other portions of the heat conduction jig.

Description

Method for manufacturing semiconductor device and method for manufacturing power conversion device

Technical Field

The technology disclosed in the present specification relates to a method for manufacturing a semiconductor device and a method for manufacturing a power conversion device.

Background

As a semiconductor device, there is a semiconductor device having an insulating substrate, a plurality of upper surface metal patterns formed on an upper surface of the insulating substrate, a lower surface metal pattern formed on a lower surface of the insulating substrate, and a semiconductor element bonded to an upper surface of the upper surface metal pattern through a bonding material.

The lower surface metal pattern among the above is bonded to the upper surface of the susceptor plate with the cooling fins by a bonding material. Further, a case for housing the semiconductor element is bonded to the upper surface of the base plate having the cooling fins via an adhesive.

Further, an electrode terminal is connected to the upper surface of the semiconductor element via a bonding material. Further, the electrode terminal is also connected to the upper surface of the upper surface metal pattern via a bonding material.

The electrode terminals are connected to or integrated with external electrode terminals provided on the upper surface of the case.

Patent document 1: japanese laid-open patent publication No. 2010-087072

In the semiconductor device having the above-described structure, as a bonding material for bonding the semiconductor element and the insulating substrate and the base plate with the cooling fin, respectively, a non-eutectic solder mainly composed of Sn — Cu, Sn — Ag, Sn — Sb, Sn-In, or Sn — Bi is used In order to ensure high reliability. However, depending on the conditions of the soldering process of the bonding material, solder craters are likely to occur.

In recent years, development of a semiconductor device capable of operating at high temperatures has been actively performed, and miniaturization, high withstand voltage, high current density, and the like of the semiconductor device have been advanced. In particular, a wide bandgap semiconductor such as SiC or GaN has a larger bandgap than a Si semiconductor, and is expected to contribute to higher breakdown voltage, miniaturization, higher current density, higher temperature operation, and the like of a semiconductor device. Here, the wide band gap semiconductor generally refers to a semiconductor having a band gap of about 2eV or more, and known examples include group 3 nitrides such as gallium nitride (GaN), group 2 oxides such as zinc oxide (ZnO), group 2 sulfur compounds such as zinc selenide (ZnSe), diamond, silicon carbide (SiC), and the like.

If the solder shrinkage cavity is generated just below the insulating substrate corresponding to the position where the semiconductor element is disposed, the thermal resistance of the corresponding portion increases. Therefore, the temperature of the semiconductor device may increase during operation of the semiconductor device, which may degrade the characteristics of the semiconductor device including the wide band gap semiconductor.

Disclosure of Invention

The technology disclosed in the present specification has been made in view of the above-described problems, and is a technology for suppressing the occurrence of solder craters directly below an insulating substrate corresponding to the position where a semiconductor element is disposed.

A first aspect of the technology disclosed in the present specification relates to a method of manufacturing a semiconductor device, wherein at least 1 semiconductor element is bonded to an upper surface of an insulating substrate via a first bonding material, a heat sink is bonded to a lower surface of the insulating substrate via a second bonding material, a heat conduction jig is disposed in contact with at least a part of the lower surface of the heat sink, the first bonding material and the second bonding material are heated, and the heat conduction jig is cooled in a state where the heat conduction jig is in contact with the lower surface of the heat sink, the heat conduction jig including a low thermal conduction portion that is disposed at a position not overlapping with the semiconductor element in a plan view and has a thermal conductivity lower than other portions of the heat conduction jig.

A 2 nd aspect of the technology disclosed in the present specification relates to a method for manufacturing a power converter, and includes a semiconductor device manufactured by the above-described manufacturing method, a converter circuit for converting input power and outputting the converted power, a driver circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device, and a control circuit for outputting a control signal for controlling the driver circuit to the driver circuit.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the 1 st aspect of the technology disclosed in the present specification, the position of the heat conduction jig where the low heat conduction portion is disposed has a lower heat conductivity than other portions of the heat conduction jig, and therefore the cooling rate is slower than other portions of the heat conduction jig. Therefore, by disposing the low thermal conductive portion at a position not overlapping the semiconductor element in a plan view, solder sink holes are more likely to be generated in the bonding material at a position overlapping the position where the low thermal conductive portion is disposed in a plan view, and conversely, solder sink holes are less likely to be generated at a position not overlapping the position where the low thermal conductive portion is disposed in a plan view (including the position where the semiconductor element is disposed). In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate corresponding to the position where the semiconductor element is disposed.

According to the 2 nd aspect of the technology disclosed in the present specification, by disposing the low thermal conductive portion at a position not overlapping the semiconductor element in a plan view, solder shrinkage holes are more likely to be generated in the bonding material at a position overlapping the position where the low thermal conductive portion is disposed in a plan view, and conversely, solder shrinkage holes are less likely to be generated at a position not overlapping the position where the low thermal conductive portion is disposed in a plan view (including the position where the semiconductor element is disposed). In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate corresponding to the position where the semiconductor element is disposed.

Drawings

Fig. 1 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to an embodiment before a case and electrode terminals are connected.

Fig. 2 is a top view of the structure illustrated in fig. 1.

Fig. 3 is a plan view schematically showing an example of the structure of a heat conduction jig for protecting a cooling fin mounted on a base plate.

Fig. 4 is a cross-sectional view schematically showing an example of a structure in which the semiconductor device illustrated in fig. 1 and 2 is mounted on the heat transfer jig illustrated in fig. 3.

Fig. 5 is a diagram showing an example of the temperature distribution of the bonding material in the state of the semiconductor device immediately after the completion of the bonding process in the reflow furnace.

Fig. 6 is a diagram showing an example of the temperature distribution of the bonding material in the middle of the cooling process of the semiconductor device after the state shown in fig. 5.

Fig. 7 is a cross-sectional view showing an example in the case where solder craters are generated in the bonding material in the structure illustrated in fig. 4.

Fig. 8 is a plan view of the structure illustrated in fig. 7, and is a diagram showing an example of the temperature distribution of the bonding material during cooling of the structure.

Fig. 9 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the embodiment.

Fig. 10 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 11 is a plan view showing an example of the structure of the heat conducting jig illustrated in fig. 10.

Fig. 12 is a diagram showing an example of a cooling state of the bonding material of the semiconductor device according to the embodiment.

Fig. 13 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the embodiment.

Fig. 14 is a plan view showing an example of the structure of the heat conducting jig illustrated in fig. 13.

Fig. 15 is a diagram showing an example of a cooling state of the bonding material of the semiconductor device according to the embodiment.

Fig. 16 is a cross-sectional view schematically showing an example of the structure of a semiconductor device known to the inventors.

Fig. 17 is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion device of the embodiment.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, detailed features and the like are shown for technical explanation, but these features are merely examples and are not all necessary features for enabling the embodiments to be implemented.

The drawings are schematically illustrated, and the structures are omitted or simplified as appropriate in the drawings for the convenience of description. The size and positional relationship of the structures and the like shown in the different drawings are not necessarily described accurately, and may be changed as appropriate.

In addition, in drawings such as a top view, which is not a cross-sectional view, a shadow may be added to facilitate understanding of the contents of the embodiment.

In the following description, the same components are denoted by the same reference numerals and are shown, and their names and functions are also the same. Therefore, detailed descriptions thereof will be sometimes omitted in order to avoid redundancy.

In the following description, when a certain component is referred to as being "provided", "included", or "having", it is not an exclusive expression that excludes the presence of other components unless otherwise specified.

In the description below, ordinal numbers such as "1 st" and "2 nd" are sometimes used, but these terms are used for ease of understanding the contents of the embodiments, and are not limited to the order in which these ordinal numbers may occur.

In the following description, expressions indicating relative or absolute positional relationships, such as "in one direction", "along one direction", "parallel", "orthogonal", "central", "concentric" or "coaxial", include cases where the positional relationships are strictly expressed, and cases where an angle or distance is shifted within a range of tolerance or equivalent function, unless otherwise specified.

In the description given below, expressions indicating equal states, such as "identical", "equal", "uniform", or "homogeneous", include cases indicating strictly equal states and cases where differences occur within a range of tolerance or equivalent functions, unless otherwise specified.

In the description below, even when there are some terms indicating specific positions or directions, such as "up", "down", "left", "right", "side", "bottom", "front", and "back", these terms are used for ease of understanding the contents of the embodiments, and are used for convenience, regardless of the position or direction in actual implementation.

In the following description, the term "upper surface of …" or "lower surface of …" includes a state in which other components are formed on the upper surface or the lower surface of the target component, in addition to the upper surface or the lower surface of the target component. That is, for example, in the case of the description "b provided on the upper surface of a" does not prevent the other component "c" from being interposed between a "and a" b ".

< embodiment 1 >

Next, a semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. For convenience of explanation, first, a description will be given of a technique related to the structure of a semiconductor device known to the inventors.

Fig. 16 is a cross-sectional view schematically showing an example of the structure of a semiconductor device known to the inventors. As illustrated in fig. 16, the semiconductor device includes an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on an upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on a lower surface of the insulating substrate 1 and usually 1 piece, and a semiconductor element 2 bonded to an upper surface of the upper surface metal pattern 1a with a bonding material 3a such as solder.

The lower surface metal pattern 1b is bonded to the upper surface of the susceptor plate 4 having cooling fins 4a such as water cooling fins by a bonding material 3b such as solder. A case 11 for housing the semiconductor element 2 is bonded to the upper surface of the base plate 4 having the cooling fins 4a via an adhesive 12.

The internal electrodes 13 are connected to the upper surface of the semiconductor element 2 via a bonding material 3c such as solder. The internal electrodes 13a are also connected to the upper surface of the upper-surface metal pattern 1a via a bonding material 3d such as solder.

The internal electrode 13 is connected to or integrated with an external electrode 14 provided on the upper surface of the case 11. The internal electrode 13a is connected to or integrated with an external electrode 14A provided on the upper surface of the case 11. The case 11 is filled with an epoxy resin-based sealing material 16.

< Structure of semiconductor device >

Fig. 1 is a cross-sectional view schematically showing an example of a structure of a semiconductor device according to the present embodiment before a case 11, an internal electrode 13, and an internal electrode 13a are connected. Fig. 2 is a plan view of the structure illustrated in fig. 1.

As illustrated in fig. 1 and 2, the semiconductor device includes an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on an upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on a lower surface of the insulating substrate 1, and a semiconductor element 2 bonded to an upper surface of the upper surface metal pattern 1a with a bonding material 3a such as solder. The lower surface metal pattern 1b is bonded to the upper surface of the base plate 4 with the cooling fins 4a by a bonding material 3b such as solder.

Here, the semiconductor element 2 includes a metal-oxide-semiconductor field-effect transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a Schottky Barrier Diode (SBD), or the like.

Fig. 3 is a plan view schematically showing an example of the structure of the heat conductive jig 5 for protecting the cooling fins 4a attached to the base plate 4. Fig. 4 is a cross-sectional view schematically showing an example of the structure in which the semiconductor device illustrated in fig. 1 and 2 is mounted on the heat transfer jig 5 illustrated in fig. 3.

As illustrated in fig. 3, the heat transfer jig 5 is hollow in the central portion in a plan view, and a recessed portion 6 having a concave shape in a cross-sectional view of fig. 4 is formed at an end portion on the central portion side in the longitudinal direction. The sinking portion 6 is disposed on a side of the pair of opposing sides of the frame-shaped heat conduction jig 5, which is distant from the semiconductor element 2 in a plan view. Further, as a material of the heat conductive jig 5, for example, Al, SUS, Cu, brass, or the like is used. Further, the sunken section 6 may be formed at an outer end portion in the longitudinal direction of the heat conductive jig 5.

If the heat conductive jig 5 is mounted to the semiconductor device illustrated in fig. 1, the heat conductive jig 5 is mounted to the lower surface of the base plate 4 with the cooling fins 4a in contact therewith as illustrated in fig. 4. The heat conduction jig 5 is disposed on the lower surface of the base plate 4 at a position not overlapping the cooling fins 4a in plan view so as to be in contact with the lower surface. In the example shown in fig. 4, the sinking portion 6 is located at a position facing the lower surface of the base plate 4 with the cooling fins 4a, and is attached to an end portion of the semiconductor device on the side where the semiconductor element 2 is not arranged (at least, at a position not overlapping with the semiconductor element 2 in a plan view).

The semiconductor device according to the present embodiment includes, for example, the case 11, the internal electrodes 13a, and the epoxy resin-based sealing material 16 illustrated in fig. 16, in addition to the structure illustrated in fig. 4.

Fig. 5 and 6 are diagrams showing examples of a cooling state of the bonding material of the semiconductor device according to the present embodiment.

Fig. 5 is a diagram showing an example of the temperature distribution of the bonding material in the state of the semiconductor device immediately after the completion of the bonding process in the reflow furnace. In fig. 5, similarly, the heat conduction jig 5 is attached to the lower surface of the base plate 4 with the cooling fins 4a so as to be in contact with the lower surface, but for convenience of explanation, the arrangement of the heat conduction jig 5 is shown to be shifted in a plan view.

As illustrated in fig. 5, the bonding material 3a (and the bonding material 3b) such as solder is completely melted, and the temperature thereof becomes substantially uniform at the melting point.

Fig. 6 is a diagram showing an example of the temperature distribution of the bonding material in the middle of the cooling process of the semiconductor device after the state shown in fig. 5. In fig. 6, a portion having a relatively high temperature is shaded with a dark color, and a portion having a relatively low temperature is shaded with a light color. In fig. 6, the heat conduction jig 5 is attached to the lower surface of the base plate 4 with the cooling fins 4a so as to be in contact with the lower surface, but for convenience of explanation, the arrangement of the heat conduction jig 5 is shown to be shifted in a plan view.

As illustrated in fig. 6, the bonding material 3a (and the bonding material 3b) such as solder is gradually cooled via the base plate 4 having the cooling fins 4 a.

Here, as illustrated in fig. 4, the susceptor plate 4 with the cooling fins 4a is in contact with the heat conductive jig 5, and the heat conductive jig 5 is cooled by an external cooling plate (not illustrated here). Accordingly, the base plate 4 with the cooling fins 4a is cooled from the portion in contact with the heat conductive jig 5, and accordingly, the bonding material 3a (and the bonding material 3b) is also gradually cooled from the side close to the portion in contact with the heat conductive jig 5.

Further, if the temperature of the joining material 3a (and the joining material 3b) is lowered to the freezing point, joining is completed.

Here, in the present embodiment, the sinking portion 6 of the heat conductive jig 5 is located at a position facing the lower surface of the base plate 4 with the cooling fins 4a, and is attached to the end portion of the semiconductor device on the side where the semiconductor element 2 is not arranged.

Since the submerged portion 6 is not in contact with the lower surface of the susceptor plate 4 with the cooling fins 4a, the side of the heat conductive jig 5 where the submerged portion 6 is located is cooled less (i.e., the cooling speed is slower) than the side where the submerged portion 6 is not located. In other words, by selecting the position of the sunken section 6 with respect to the semiconductor device, the speed of temperature decrease at each position of the bonding material 3a (and the bonding material 3b) can be controlled.

It is known that if the cooling rate is lowered, solder shrinkage tends to occur. Therefore, by reducing the speed (cooling rate) of temperature decrease of the joining material near the position of the depressed portion 6, that is, by generating temperature unevenness between the joining materials in the cooling process, a portion of the joining material having a high temperature (that is, a portion having a low cooling rate) becomes the final solidification point of the solder, and guidance can be performed so that solder shrinkage cavities are generated in the portion. This can suppress the occurrence of solder shrinkage cavities directly below the insulating substrate 1 where the semiconductor element 2 is disposed.

< solder shrinkage cavity >

Next, the solder shrinkage cavity will be explained. Fig. 7 is a cross-sectional view showing an example in a case where the solder crater 15 is generated in the bonding material 3b in the structure illustrated in fig. 4. Fig. 8 is a plan view of the structure illustrated in fig. 7, and is a diagram showing an example of the temperature distribution of the bonding material during cooling of the structure. In fig. 8, a portion having a relatively high temperature is shaded with a dark color, and a portion having a relatively low temperature is shaded with a light color.

As illustrated in fig. 7 and 8, it is understood that a portion of the bonding material having a high temperature (i.e., a low cooling rate) becomes the final solidification point of the solder, and a solder crater 15 is generated in this portion. As described above, the solder shrinkage cavity 15 refers to a void that may be generated at a final solidification point of the solder in a cooling process after a bonding process in a reflow oven or the like.

< method for manufacturing semiconductor device >

Next, a method for manufacturing a semiconductor device using the heat conductive jig will be described. Fig. 9 is a flowchart showing an example of the method for manufacturing the semiconductor device according to the present embodiment.

First, the heat conduction jig 5 and the cooling fins, the insulating substrate, the semiconductor element, the bonding material, and the like constituting a part of the semiconductor device are prepared (step ST01 in fig. 9). Specifically, the lower surface of the susceptor plate 4 with the cooling fins 4a is disposed on the upper surface of the heat conductive jig 5 so as to be in contact with the upper surface of the heat conductive jig 5. The lower surface metal pattern 1b, the insulating substrate 1, and the upper surface metal pattern 1a are disposed on the upper surface of the base plate 4 with the cooling fins 4a, in this order, via a bonding material 3b such as solder. The semiconductor element 2 is disposed on a part of the upper surface metal pattern 1a via a bonding material 3a such as solder.

Next, the structure prepared in step ST01 is loaded into a reflow furnace (step ST02 in fig. 9). Here, in the reflow furnace, regions having different set temperatures are provided in the preheating region, the bonding region, and the cooling region, respectively, and a series of steps (i.e., the preheating step, the heating step, and the cooling step) are continuously performed. That is, these steps are continuously performed in a state where the semiconductor element 2 is bonded to the upper surface of the insulating substrate 1 with the bonding material 3a, the base plate 4 is bonded to the lower surface of the insulating substrate 1 with the bonding material 3b, and the heat conductive jig 5 is in contact with the lower surface of the base plate 4.

Next, the semi-finished product in the stage of being soldered in the reflow oven is taken out from the reflow oven, and the adhesive 12 is applied to the peripheral portion of the upper surface of the base plate 4 with the cooling fins 4 a. Then, the case 11 is bonded to the upper surface of the base plate 4 with the cooling fins 4a via the adhesive 12. Then, the internal electrodes 13 are bonded to the upper surface of the semiconductor element 2 via bonding materials 3c such as solder, and the internal electrodes 13a are bonded to the upper surface of the upper-surface metal pattern 1a via bonding materials 3d such as solder (step ST03 in fig. 9).

Next, the structure prepared in step ST03 is carried into the reflow furnace again (step ST04 in fig. 9). Then, in the reflow furnace, the bonding of the base plate 4 with the cooling fins 4a and the case 11, and the bonding of the semiconductor element 2 and the internal electrodes 13 are completed. Here, the heat-conducting jig 5 is removed from the base plate 4 with the cooling fins 4 a.

Next, in the structure in which reflow soldering is performed in step ST04, a bonding wire (not shown here) is wired, and the case 11 is filled with an epoxy-based sealing material 16 (step ST05 in fig. 9). Then, the encapsulating material 16 is cured by applying heat. Through the above steps, the semiconductor device is completed.

As described above, by manufacturing the semiconductor device using the heat transfer jig 5, the cooling rate of the bonding material of the semiconductor device can be controlled for each portion according to the arrangement of the heat transfer jig 5. Therefore, the occurrence of solder shrinkage cavities directly below the insulating substrate 1 at the position where the semiconductor element 2 is disposed can be suppressed. Further, by disposing the heat conduction jig 5 so as to surround the cooling fins 4a in a plan view, the shape of the cooling fins 4a can be suppressed from being deformed while holding the cooling fins 4 a. Further, since a series of steps such as the preheating step, the heating step, and the cooling step can be performed while the insulating substrate 1, the semiconductor element 2, and the base plate 4, which are positioned with respect to each other, are carried on the upper surface of the heat transfer jig 5, a positioning accuracy of the semiconductor device and a manufacturing efficiency of the semiconductor device can be improved.

< embodiment 2 >

A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is omitted as appropriate.

< Structure of semiconductor device >

Fig. 10 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment. Fig. 11 is a plan view showing an example of the structure of the heat conducting jig 5A illustrated in fig. 10.

As illustrated in fig. 10, the semiconductor device includes an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on an upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on a lower surface of the insulating substrate 1, and a semiconductor element 2 bonded to an upper surface of the upper surface metal pattern 1a with a bonding material 3a such as solder. The lower surface metal pattern 1b is bonded to the upper surface of the base plate 4 with the cooling fins 4a by a bonding material 3b such as solder. The heat conductive jig 5A is attached to the lower surface of the base plate 4 with the cooling fins 4a in contact therewith.

As illustrated in fig. 10 and 11, the heat conduction jig 5A is disposed on the lower surface of the base plate 4 at a position not overlapping the cooling fins 4a in plan view so as to be in contact with the lower surface. The heat transfer jig 5A is hollow in the central portion in a plan view, and a notch 7 is formed in the end portion on the central portion side in the longitudinal direction, the notch being cut in the direction from the central portion toward the peripheral portion as compared with other portions. The notch 7 is disposed on a side of the pair of opposing sides of the frame-shaped heat conduction jig 5A that is distant from the semiconductor element 2 in a plan view. The cutout 7 is formed in the surface of the heat conduction jig 5A that contacts the lower surface of the base plate 4. The notch 7 may be cut in a direction from the peripheral portion to the central portion of the heat transfer jig 5A.

Fig. 12 is a diagram showing an example of a cooling state of the bonding material of the semiconductor device according to the present embodiment. In fig. 12, a portion having a relatively high temperature is shaded with a dark color, and a portion having a relatively low temperature is shaded with a light color. In fig. 12, similarly, the heat conduction jig 5A is attached to the lower surface of the base plate 4 with the cooling fins 4a so as to be in contact with the lower surface, but for convenience of explanation, the arrangement of the heat conduction jig 5A is shown to be shifted in a plan view.

The cutout portion 7 formed in the heat conduction jig 5A has a smaller heat capacity than the sunken portion 6 illustrated in fig. 3. Therefore, according to the heat conduction jig 5A, a larger temperature unevenness between the joining materials can be generated in the cooling process. This is effective particularly in the case of solder having a narrow range of solid-liquid phase temperature and being less likely to cause temperature unevenness.

By making the temperature unevenness among the bonding materials in the cooling process larger, the portion of the bonding material where the temperature is high (i.e., where the cooling rate is slow) becomes the final solidification point of the solder, and it is possible to effectively guide so that the solder shrinkage cavity is generated in the portion. This can effectively suppress the occurrence of solder voids directly below the insulating substrate 1 where the semiconductor element 2 is disposed.

< embodiment 3 >

< Structure of semiconductor device >

Fig. 13 is a cross-sectional view schematically showing an example of the structure of the semiconductor device according to the present embodiment. Fig. 14 is a plan view showing an example of the structure of the heat conducting jig 5B illustrated in fig. 13.

As illustrated in fig. 13, the semiconductor device includes an insulating substrate 1, a plurality of upper surface metal patterns 1a formed on an upper surface of the insulating substrate 1, a lower surface metal pattern 1b formed on a lower surface of the insulating substrate 1, and a semiconductor element 2 bonded to an upper surface of the upper surface metal pattern 1a with a bonding material 3a such as solder. The lower surface metal pattern 1b is bonded to the upper surface of the base plate 4 with the cooling fins 4a by a bonding material 3b such as solder. The heat conductive jig 5B is attached to the lower surface of the base plate 4 with the cooling fins 4a in contact therewith.

As illustrated in fig. 13 and 14, the heat conduction jig 5B is disposed on the lower surface of the base plate 4 at a position not overlapping the cooling fins 4a in plan view so as to be in contact with the lower surface. The heat conduction jig 5B is hollow in the central portion in a plan view, and one of the short sides of the frame-shaped heat conduction jig 5B has a low thermal conductivity material 8 having a lower thermal conductivity than the other portions. The low thermal conductive material 8 is disposed on one of a pair of opposing sides of the frame-shaped heat conductive jig 5B, which is located away from the semiconductor element 2 in a plan view. The low thermal conductive material 8 is provided on the side contacting the lower surface of the susceptor plate 4 having the cooling fins 4a, and is made of, for example, a nonmetal or ceramic. Further, the heat conductive jig 5B may have the low heat conductive material 8 locally on the upper surface of the short side (not the entire surface).

Fig. 15 is a diagram showing an example of a cooling state of the bonding material of the semiconductor device according to the present embodiment. In fig. 15, a portion having a relatively high temperature is shaded with a dark color, and a portion having a relatively low temperature is shaded with a light color. In fig. 15, similarly, the heat conduction jig 5B is attached to the lower surface of the base plate 4 with the cooling fins 4a so as to be in contact with the lower surface, but for convenience of explanation, the arrangement of the heat conduction jig 5B is shown to be shifted in a plan view.

According to the low thermal conductive material 8 of the thermal conductive jig 5B, temperature unevenness between the joining materials can be generated in the cooling process. By generating temperature unevenness between the joining materials in the cooling process, a portion of the joining materials having a high temperature (i.e., a slow cooling rate) becomes the final solidification point of the solder, and guidance can be performed so that solder shrinkage cavities are generated in the portion. This can effectively suppress the occurrence of solder voids directly below the insulating substrate 1 where the semiconductor element 2 is disposed.

< embodiment 4 >

The power conversion device and the method for manufacturing the power conversion device according to the present embodiment will be described. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals and shown, and detailed description thereof is appropriately omitted.

< Structure of Power conversion device >

In this embodiment, the semiconductor device according to the above-described embodiment is applied to a power conversion device. The power conversion device to be applied is not limited to a specific application, but a case of applying the power conversion device to a three-phase inverter will be described below.

Fig. 17 is a diagram conceptually showing an example of the configuration of a power conversion system including the power conversion device of the present embodiment.

As illustrated in fig. 17, the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a dc power supply, and supplies dc power to the power conversion device 2200. The power supply 2100 may be configured by various power supplies, and may be configured by a dc system, a solar cell, a storage battery, or the like, for example. The power supply 2100 may be configured by a rectifier circuit or an AC-DC converter connected to an AC system. The power supply 2100 may be configured by a DC-DC converter that converts DC power output from the DC system into predetermined power.

The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts dc power supplied from the power supply 2100 into ac power, and then supplies the ac power to the load 2300.

As illustrated in fig. 17, power conversion device 2200 includes: a converter circuit 2201 that converts dc power into ac power and outputs the ac power; a drive circuit 2202 that outputs a drive signal for driving each switching element of the conversion circuit 2201; and a control circuit 2203 that outputs a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

Load 2300 is a three-phase motor driven by ac power supplied from power conversion device 2200. The load 2300 is not limited to a specific application, and is a motor mounted on various electric devices, for example, a motor for a hybrid car, an electric car, a railway vehicle, an elevator, or an air conditioner.

Hereinafter, the power conversion device 2200 will be described in detail. The conversion circuit 2201 includes a switching element and a flywheel diode (not shown). Then, the switching element is turned on and off to convert the dc power supplied from the power supply 2100 into ac power, and then supply the ac power to the load 2300.

Although there are various specific circuit configurations of the converter circuit 2201, the converter circuit 2201 according to the present embodiment is a 2-level three-phase full bridge circuit and includes 6 switching elements and 6 freewheeling diodes connected in anti-parallel to the switching elements.

The semiconductor device according to any of the above-described embodiments is applied to at least one of each switching element and each free wheel diode in the conversion circuit 2201. Two of the 6 switching elements are connected in series to form upper and lower arms, and each of the upper and lower arms forms each phase (i.e., U-phase, V-phase, and W-phase) of the full bridge circuit. Output terminals of the upper and lower arms (i.e., 3 output terminals of the converter circuit 2201) are connected to the load 2300.

The driving circuit 2202 generates a driving signal for driving the switching element of the conversion circuit 2201 and then supplies the driving signal to the control electrode of the switching element of the conversion circuit 2201. Specifically, a drive signal for turning the switching element on and a drive signal for turning the switching element off are output to the control electrode of each switching element based on a control signal output from a control circuit 2203 described later.

The drive signal is a voltage signal (i.e., an on signal) equal to or higher than the threshold voltage of the switching element when the switching element is maintained in the on state, and is a voltage signal (i.e., an off signal) equal to or lower than the threshold voltage of the switching element when the switching element is maintained in the off state.

The control circuit 2203 controls the switching elements of the converter circuit 2201 to supply desired power to the load 2300. Specifically, based on the electric power that should be supplied to the load 2300, the time (i.e., the on-time) at which each switching element of the conversion circuit 2201 should be brought into the on-state is calculated. For example, the switching circuit 2201 can be controlled by PWM control for modulating the on time of the switching element in accordance with the voltage to be output.

The control circuit 2203 outputs a control command (that is, a control signal) to the drive circuit 2202 so as to output an on signal to the switching element to be turned on and an off signal to the switching element to be turned off at each time. The drive circuit 2202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element based on the control signal.

In the power converter 2200 according to the present embodiment, since the semiconductor device according to any one of the above-described embodiments is applied as the switching element of the converter circuit 2201, the on-resistance after the passage of the power-on period can be stabilized.

In the present embodiment, the semiconductor device of any of the above-described embodiments is applied to a 2-level three-phase inverter, but the application example is not limited to this, and the semiconductor device of any of the above-described embodiments can be applied to various power conversion devices.

In addition, although the 2-level power conversion device is described in the present embodiment, the semiconductor device according to any of the above-described embodiments may be applied to a 3-level or multilevel power conversion device. In addition, when power is supplied to a single-phase load, the semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

In addition, when power is supplied to a DC load or the like, the semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

The power converter to which the semiconductor device according to any of the above-described embodiments is applied is not limited to the case where the load is a motor, and may be used as a power supply device of an electric discharge machine, a laser machine, an induction heating cooker, or a contactless power supply system, for example. Further, the power conversion device to which the semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

< method for manufacturing Power conversion device >

Next, a method for manufacturing the power converter according to the present embodiment will be described.

First, the semiconductor device is manufactured by the manufacturing method described in the above-described embodiment. Then, the converter circuit 2201 having the semiconductor device is provided as a structure of a power converter. The converter circuit 2201 is a circuit for converting and outputting input power.

Then, the drive circuit 2202 is provided as a configuration of the power conversion device. The driver circuit 2202 is a circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device. Then, the control circuit 2203 is provided as a configuration of the power conversion device. The control circuit 2203 is a circuit for outputting a control signal for controlling the drive circuit 2202 to the drive circuit 2202.

The semiconductor switching element used in the above-described embodiments is not limited to a switching element made of a silicon (Si) semiconductor, and for example, the semiconductor switching element may be made of a non-Si semiconductor material having a wider band gap than a Si semiconductor.

As a wide band gap semiconductor which is a non-Si semiconductor material, for example, silicon carbide (SiC), gallium nitride based materials, diamond, or the like are available.

The switching element made of a wide band gap semiconductor can be used even in a high voltage region where a unipolar operation is difficult for an Si semiconductor, and can significantly reduce an on-off loss generated at the time of the on-off operation. Therefore, a significant reduction in power loss can be achieved.

Further, the switching element formed of a wide bandgap semiconductor has a small power loss and high heat resistance. Therefore, in the case of configuring a power module having a cooling portion, the heat radiation fins of the heat sink can be miniaturized, and therefore, further miniaturization of the semiconductor module can be achieved.

Further, the switching element made of a wide bandgap semiconductor is suitable for high-frequency on/off operation. Therefore, when applied to a converter requiring a high frequency, the reactor, the capacitor, or the like connected to the converter circuit can be downsized by increasing the on/off frequency.

Therefore, the same effects can be obtained also in the case where the semiconductor switching element in the above-described embodiment is a switching element made of a wide bandgap semiconductor such as silicon carbide (SiC).

< effects produced by the above-described embodiments >

Next, an example of the effects produced by the above-described embodiments is shown. In the following description, the effects are described based on the specific configurations exemplified in the above-described embodiments, but the same effects may be produced by other specific configurations exemplified in the present specification.

In addition, this permutation may also be implemented across multiple embodiments. That is, the same effects can be produced by combining the respective configurations illustrated in the different embodiments.

According to the above-described embodiment, in the method for manufacturing a semiconductor device, at least 1 semiconductor element 2 is bonded to the upper surface of the insulating substrate 1 via the 1 st bonding material. Here, the 1 st bonding material corresponds to, for example, the bonding material 3a and the like. Then, the heat dissipation plate is bonded to the lower surface of the insulating substrate 1 via the 2 nd bonding material. Here, the 2 nd bonding material corresponds to, for example, the bonding material 3b and the like. The heat sink corresponds to, for example, the base plate 4. The heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) is disposed so as to contact at least a part of the lower surface of the susceptor plate 4. Then, the bonding material 3a and the bonding material 3B are heated, and then the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) is cooled in a state where the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) is in contact with the lower surface of the base plate 4. Here, the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) has a low thermal conductivity portion which is disposed at a position not overlapping the semiconductor element 2 in a plan view and has a lower thermal conductivity than other portions of the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B). The low thermal conductive portion corresponds to, for example, any 1 of the recessed portion 6, the cut portion 7, and the low thermal conductive material 8 (hereinafter, for convenience, any 1 of these may be described as corresponding to one another).

According to such a configuration, since the heat conductivity of the position of the heat conduction jig 5 where the sunken section 6 is disposed is lower than that of the other portion of the heat conduction jig 5, the cooling rate is lower than that of the other portion of the heat conduction jig 5. That is, the heat conduction jig 5 does not uniformly cool the insulating substrate 1 and the base plate 4 of the semiconductor device. Therefore, by disposing the depressed portion 6 at a position not overlapping the semiconductor element 2 in a plan view, solder sink is more likely to occur in the bonding material 3a or the bonding material 3b at a position overlapping the position where the depressed portion 6 is disposed in a plan view, and conversely, solder sink is less likely to occur in the bonding material 3a or the bonding material 3b at a position not overlapping the position where the depressed portion 6 is disposed (including the position where the semiconductor element 2 is disposed) in a plan view. In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed. Thus, a decrease in heat dissipation in the vicinity of the semiconductor element 2 can be suppressed, and thus a decrease in characteristics of the semiconductor element 2 can be suppressed.

In addition, the order of performing each process can be changed without particular limitation.

In addition, the same effects can be produced also in the case where another structure exemplified in the present specification is appropriately added to the above-described structure, that is, in the case where another structure in the present specification which is not mentioned as the above-described structure is appropriately added.

Further, according to the above-described embodiment, the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) has a frame shape surrounding the semiconductor element 2 in a plan view. The low thermal conductive portion is disposed on a side of the pair of opposing sides of the frame shape, which is located away from the semiconductor element 2 in a plan view. According to such a configuration, since the position where the low thermal conductive portion is disposed is a position distant from the position where the semiconductor element 2 is disposed, the final solidification point of the solder is close to the position distant from the semiconductor element 2 in a plan view, and the solder shrinkage cavity can be generated at the position by guiding. In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed.

In addition, according to the above-described embodiment, the fins are formed on the lower surface of the base plate 4. Here, the fins correspond to, for example, the cooling fins 4a and the like. The heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) is disposed on the lower surface of the base plate 4 at a position not overlapping the cooling fins 4a in plan view so as to be in contact with the lower surface. According to such a structure, the heat conductive jig 5 can effectively protect the cooling fins 4a for heat dissipation formed at the base plate 4 and contact the lower surface of the base plate 4.

In addition, according to the above-described embodiment, the low thermal conductive portion is a concave portion (i.e., the sinking portion 6) formed on the surface of the thermal conductive jig 5 that contacts the lower surface of the base plate 4. According to such a structure, the heat conductive jig 5 is not in contact with the lower surface of the base plate 4 at the portion where the recess, i.e., the submerged portion 6, is formed. Therefore, the thermal conductivity of this portion is lower than that of the other portions. As a result, the final solidification point of the solder is close to the portion, and the solder can be guided so as to generate the solder crater in the portion. In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed.

Further, according to the above-described embodiment, the low thermal conductive portion is the notch portion 7 formed on the surface of the thermal conductive jig 5A which contacts the lower surface of the base plate 4. According to such a structure, the heat conductive jig 5A is not in contact with the lower surface of the base plate 4 at the portion where the cutout portion 7 is formed. Therefore, the thermal conductivity of this portion is lower than that of the other portions. As a result, the final solidification point of the solder is close to the portion, and the solder can be guided so as to generate the solder crater in the portion. In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed.

Further, according to the above-described embodiment, the low thermal conductive portion, i.e., the low thermal conductive material 8 is formed on the surface of the heat conductive jig 5B that contacts the lower surface of the base plate 4, and is made of a material having a lower thermal conductivity than the material forming the other portion of the heat conductive jig 5B. According to such a structure, the portion having the low thermal conductive material 8 has a lower thermal conductivity than the other portion of the heat conductive jig 5B. As a result, the final solidification point of the solder is close to the portion, and the solder can be guided so as to generate the solder crater in the portion. In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed.

Further, according to the above-described embodiment, heating the bonding material 3a and the bonding material 3B and then cooling the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) are continuously performed in a state where the semiconductor element 2 is bonded to the upper surface of the insulating substrate 1 via the bonding material 3a, the base plate 4 is bonded to the lower surface of the insulating substrate 1 via the bonding material 3B, and the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) is in contact with the lower surface of the base plate 4. According to such a configuration, the insulating substrate 1, the semiconductor element 2, and the heat dissipation plate 4 can be carried on the upper surface of the heat conduction jig 5 (or the heat conduction jig 5A and the heat conduction jig 5B) in a state in which the structures are positioned with respect to each other, and then the heating step and the cooling step can be continuously performed.

Further, according to the above-described embodiment, the method of manufacturing the power converter includes the semiconductor device manufactured by the above-described manufacturing method, and the converter circuit 2201 for converting the input power and outputting the converted power is provided. Further, a driver circuit 2202 for outputting a drive signal for driving the semiconductor device to the semiconductor device is provided. Further, a control circuit 2203 is provided to output a control signal for controlling the drive circuit 2202 to the drive circuit 2202. According to such a configuration, since the position of the heat conduction jig where the low heat conduction portion is disposed has a lower heat conductivity than the other portion of the heat conduction jig, the cooling rate is slower than the other portion of the heat conduction jig. Therefore, by disposing the low thermal conductive portion at a position not overlapping the semiconductor element 2 in a plan view, solder shrinkage holes are more likely to be generated in the bonding material 3a or the bonding material 3b at a position overlapping the position where the low thermal conductive portion is disposed in a plan view, and conversely, solder shrinkage holes are less likely to be generated in a position not overlapping the position where the low thermal conductive portion is disposed in a plan view (including the position where the semiconductor element 2 is disposed). In other words, it is possible to suppress the occurrence of solder craters directly below the insulating substrate 1 corresponding to the position where the semiconductor element 2 is disposed.

< modification of the above-described embodiment >

In the above-described embodiments, materials, dimensions, shapes, relative arrangement, implementation conditions, and the like of the respective constituent elements are described in some cases, but these are merely examples in all respects and are not restrictive.

Therefore, a myriad of modifications and equivalents not shown in the drawings can be conceived within the scope of the technology disclosed in the present specification. For example, the case where at least 1 component is modified, added, or omitted is included, and the case where at least 1 component in at least 1 embodiment is extracted and combined with components in other embodiments is included.

In the above-described embodiments, when a name of a material or the like is not specifically described, an alloy or the like containing other additives in the material is included unless a contradiction occurs.

In addition, the constituent elements described as having "1" in the above-described embodiments may have "1 or more" as long as no contradiction occurs.

Each of the components in the above-described embodiments is a conceptual unit, and includes a case where 1 component is composed of a plurality of structures, a case where 1 component corresponds to a part of a certain structure, and a case where 1 structure has a plurality of components, within the scope of the technology disclosed in the present specification.

The components of the above-described embodiments include structures having other structures or shapes as long as they perform the same function.

In addition, the descriptions in the specification of the present application are referred to for all purposes related to the present technology, and are not admitted to be prior art.

Description of the reference numerals

1 insulating substrate, 1a upper surface metal pattern, 1B lower surface metal pattern, 2 semiconductor element, 3a, 3B, 3c, 3d bonding material, 4 base plate, 4A cooling fin, 5A, 5B heat conducting jig, 6 sinking part, 7 cut-out part, 8 low heat conducting material, 11 shell, 12 adhesive, 13a internal electrode, 14A external electrode, 15 solder shrinkage hole, 16 packaging material, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 driving circuit, 2203 control circuit, 2300 load.

Claims

1. A method for manufacturing a semiconductor device is provided,

at least 1 semiconductor element is bonded to the upper surface of the insulating substrate via a 1 st bonding material,

a heat sink is bonded to the lower surface of the insulating substrate via a 2 nd bonding material,

a heat conductive jig is disposed so as to contact at least a part of a lower surface of the heat dissipation plate,

heating the 1 st bonding material and the 2 nd bonding material, and cooling the heat conduction jig in a state where the heat conduction jig is in contact with a lower surface of the heat dissipation plate,

the heat conduction jig has a low heat conduction portion which is disposed at a position not overlapping the semiconductor element in a plan view and has a lower heat conductivity than other portions of the heat conduction jig.

2. The method for manufacturing a semiconductor device according to claim 1,

the heat conductive jig has a frame shape surrounding the semiconductor element in a plan view,

the low thermal conductive portion is disposed on one of a pair of opposing sides of the frame shape, the one being located away from the semiconductor element in a plan view.

3. The method for manufacturing a semiconductor device according to claim 1 or 2,

forming a fin on the lower surface of the heat dissipation plate,

the heat conductive jig is disposed so as to be in contact with the lower surface of the heat sink at a position not overlapping the fin in a plan view.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3,

the low heat conduction portion is a concave portion formed on a surface of the heat conduction jig contacting the lower surface of the heat dissipation plate.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3,

the low heat conduction portion is a notch portion formed on a surface of the heat conduction jig contacting the lower surface of the heat dissipation plate.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 3,

the low thermal conductive portion is formed on a surface of the thermal conductive jig contacting the lower surface of the heat dissipation plate, and is made of a material having a lower thermal conductivity than a material forming other portions of the thermal conductive jig.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6,

the heating of the 1 st bonding material and the 2 nd bonding material and the cooling of the heat conducting jig are continuously performed in a state where the semiconductor element is bonded to the upper surface of the insulating substrate by the 1 st bonding material, the heat radiating plate is bonded to the lower surface of the insulating substrate by the 2 nd bonding material, and the heat conducting jig is in contact with the lower surface of the heat radiating plate.

8. A method of manufacturing a power conversion device having a semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 7 and provided with a conversion circuit that converts input power and outputs the converted power,

a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device is provided,

a control circuit is provided for outputting a control signal for controlling the drive circuit to the drive circuit.