CN113539942A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN113539942A CN113539942A CN202010297241.2A CN202010297241A CN113539942A CN 113539942 A CN113539942 A CN 113539942A CN 202010297241 A CN202010297241 A CN 202010297241A CN 113539942 A CN113539942 A CN 113539942A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, wherein a grid structure is arranged on the substrate, and source and drain regions are arranged in the substrate at two sides of the grid structure; forming an interlayer dielectric layer covering the grid structure, the source region and the drain region on the substrate; forming a first contact hole exposing the source region and the drain region in the interlayer dielectric layer; forming a metal silicide lamination at the bottom of the first contact hole, wherein the metal silicide lamination at least comprises a stacking unit, and the stacking unit comprises a silicon layer and a metal layer which are sequentially formed at the bottom of the first contact hole; and annealing the metal silicide lamination to obtain the metal silicide layer. The method for forming the semiconductor structure provided by the embodiment of the invention not only avoids the problems of stress reduction and channel resistance increase caused by ion implantation of the source region and the drain region, but also greatly reduces the heat accumulation brought by the formation process of the metal silicide, can obtain the metal silicide layer with uniform components and good quality, is favorable for reducing the contact resistance and RC delay, and improves the performance of the semiconductor structure.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
Along with the continuous increase of the integration level of semiconductor devices, the relevant critical dimension of the semiconductor devices is continuously reduced, and accordingly, a plurality of problems occur, such as the surface resistance and the contact resistance of the drain and source regions of the devices are correspondingly increased, the response speed of the devices is reduced, and signals are delayed. Therefore, a low resistivity interconnect structure becomes a key element in manufacturing a high integration semiconductor device.
In order to reduce the contact resistance of the drain-source doped region of the device, a metal contact layer is formed on the drain-source doped region, and the metal contact layer is made of metal silicide. The metal silicide has lower resistivity, and can remarkably reduce the contact resistance of the drain source region. Metal silicides and formation processes have been widely used to reduce the surface resistance and contact resistance of the source and drain regions of devices, thereby reducing the rc delay.
However, the electrical performance of the semiconductor structure formed by the prior art still needs to be improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for forming a semiconductor structure, which can form a metal silicide layer with uniform components, is favorable for reducing contact resistance and RC delay.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, forming a grid structure on the substrate, wherein a source region and a drain region are arranged in the substrate on two sides of the grid structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the grid structure, the source region and the drain region; forming a first contact hole in the interlayer dielectric layer, wherein the first contact hole exposes the source region and the drain region; forming a metal silicide lamination at the bottom of the first contact hole, wherein the metal silicide lamination at least comprises a stacking unit, and the stacking unit comprises a silicon layer and a metal layer which are sequentially formed at the bottom of the first contact hole; and annealing the metal silicide lamination to obtain the metal silicide layer.
Optionally, the metal silicide stack further includes a silicon layer formed on a surface of the stacked unit.
Optionally, the ratio of the thickness of the silicon layer to the thickness of the metal layer is 0.1-10.
Optionally, the total thickness of the metal silicide lamination is 0.5nm to 30 nm.
Optionally, when the gate structure is a metal gate structure, after the metal silicide stack is formed at the bottom of the first contact hole, the method further includes: and forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole exposes the surface of the grid structure.
Optionally, when the gate structure is a polysilicon gate structure, before forming the metal silicide stack at the bottom of the first contact hole, the method further includes: and forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole exposes the surface of the grid structure.
Optionally, after forming the second contact hole, the method further includes: and forming a metal silicide lamination layer at the bottom of the first contact hole and the bottom of the second contact hole.
Optionally, after forming the second contact hole, the method further includes: and forming a barrier layer on the side wall and the bottom of the first contact hole and on the side wall and the bottom of the second contact hole.
After forming a metal silicide lamination layer at the bottom of the first contact hole and the bottom of the second contact hole, the method further comprises the following steps: and forming a barrier layer on the side wall and the bottom of the first contact hole and on the side wall and the bottom of the second contact hole.
Optionally, the step of forming the metal silicide stack at the bottom of the first contact hole includes: forming a metal silicide stacked film on the bottom and the side wall of the first contact hole; filling the first contact hole with a sacrificial layer; etching back the sacrificial layer to expose the metal silicide stacked film on the side wall of the first contact hole; and etching to remove the metal silicide stacked film on the side wall of the first contact hole, and forming a metal silicide stacked layer at the bottom of the first contact hole.
Optionally, the material of the sacrificial layer includes a bottom anti-reflective material or a spin-on carbon-containing compound.
Optionally, when forming the metal silicide stack at the bottom of the first contact hole, the method further includes: and forming a metal silicide laminated layer on the side wall of the first contact hole.
Optionally, when forming the metal silicide stack at the bottom of the first contact hole and the bottom of the second contact hole, the method further includes: and forming a metal silicide lamination layer on the side wall of the first contact hole and the side wall of the second contact hole.
Optionally, the annealing treatment method includes a temperature equalization annealing process, a spike annealing process, a flash annealing process, or a laser annealing process.
Optionally, the process parameters of the annealing treatment include: the annealing temperature is 400-1000 ℃, the annealing time is 0.4-60 seconds, the annealing atmosphere comprises one or more of nitrogen, hydrogen, ammonia, oxygen or argon, and the annealing pressure is 0.001-780 torr.
Optionally, the material of the metal layer includes titanium or nickel or cobalt.
Optionally, the material of the barrier layer includes titanium nitride or tantalum nitride.
Optionally, after the forming the barrier layer, the method further includes: and filling a conductive layer in the first contact hole and the second contact hole.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
when the metal silicide layer is formed by annealing, on one hand, because the surface of the bottom of the first contact hole is provided with the silicon layer, the problems of stress reduction and channel resistance increase caused by silicon consumption of a source region and a drain region can be avoided, and the heat accumulation caused by the metal silicide forming process is greatly reduced; on the other hand, by depositing multiple layers of silicon and metal layers, the stacked silicon and metal layers can be completely reacted during annealing treatment, the formed metal silicide layer has uniform components and good quality, no hole is formed, and the reduction of contact resistance and RC delay is facilitated.
Drawings
Fig. 1 to 9 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to a first embodiment of the present invention;
fig. 10 to 16 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to a second embodiment of the present invention.
Detailed Description
As is known in the art, metal silicide and formation processes have been widely used to reduce the surface resistance and contact resistance of the source and drain regions of the device, thereby reducing the rc delay time.
The existing method for forming metal silicide is to form a metal layer in a contact hole by a deposition mode, because metal is not easy to deposit to the bottom of the contact hole with a high aspect ratio, the thickness of the metal silicide is not easy to increase, in order to increase the thickness of the metal silicide, a layer of amorphous layer is usually formed at the bottom of the contact hole by adopting pre-amorphization treatment before the metal layer is deposited, and the metal silicide layer is formed on the basis of the amorphous layer.
The inventor finds that in the process of forming the metal silicide by adopting the method, firstly, the stress of a source region and a drain region is released due to pre-amorphization treatment, and the breakdown voltage is reduced; secondly, silicon of a source region and a drain region is consumed when the metal silicide layer is formed, and if the amorphous layer cannot completely react with the metal layer, contact capacitance is increased; finally, when the thicker amorphous layer reacts with the thicker metal layer, voids are easily generated, so that the quality of the formed metal silicide is poor, and the components of the formed metal silicide are inconsistent under the condition of limited Thermal Budget (Thermal Budget), which is not favorable for the electrical performance of the semiconductor structure.
In order to solve the above problems, the inventors have studied and provided a method for forming a semiconductor structure, in which a metal silicide stack is formed at the bottom of a first contact hole, the metal silicide stack includes at least one stack unit, the stack unit includes a silicon layer and a metal layer sequentially formed at the bottom of the first contact hole, and the metal layer does not react with silicon of a source region and a drain region during an annealing process, thereby avoiding consumption of silicon of the source region and the drain region; meanwhile, a silicon layer and metal layer stacking structure is adopted, on one hand, pre-amorphization treatment is not needed, and source-drain stress release is avoided; on the other hand, the silicon layer and the metal layer are overlapped in a cross mode, reaction can be completed during reaction, the formed metal silicide layer is uniform in components and not prone to generating holes, contact resistance and contact capacitance are reduced, and performance of the semiconductor structure is further improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First embodiment
Fig. 1 to 9 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to a first embodiment of the present invention.
Referring to fig. 1, a substrate is provided, a gate structure 200 is formed on the substrate, and a source region 101 and a drain region 102 are formed in the substrate 100 at two sides of the gate structure 200.
In this embodiment, taking the formed semiconductor structure as a Fin FET (Fin field effect transistor) structure as an example, the substrate includes: a substrate 100; discrete fins 110 on the substrate 100; an isolation structure (not shown) on the substrate 100 exposed by the fins 110 covers a portion of sidewalls of the fins 110, and a top of the isolation structure is lower than a top of the fins 110.
In other embodiments, the semiconductor device may also be a planar device, and the base is a planar substrate.
The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 110 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 100 is a silicon substrate, and the fin 110 is made of silicon.
The isolation structure serves to electrically isolate the adjacent fins 110, and the isolation structure is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. In this embodiment, the isolation structure is made of silicon oxide.
In this embodiment, the substrate 100 only includes an NMOS region, and the corresponding FinFET device is an NMOS transistor; in other embodiments, the substrate may also include an NMOS region and a PMOS region, and the corresponding semiconductor device is a CMOS transistor, or may only include a PMOS region, and the corresponding FinFET device is a PMOS transistor.
The gate structure 200 is located on the isolation structure and crosses over the fin 110, and the gate structure 200 covers a portion of the top and sidewalls of the fin 110.
In this embodiment, the gate structure 200 is a metal gate structure, and a gate electrode material of the gate structure 200 includes copper, aluminum, or tungsten.
A sidewall 210 is further formed on the sidewall of the gate structure 200. The material of the sidewall spacers 210 includes one or more of silicon nitride, silicon oxide, or silicon oxynitride. In this embodiment, the material of the sidewall spacer 210 is silicon nitride.
In this embodiment, the doping ions of the source region 101 and the drain region 102 are N-type ions, such as P, As or Sb.
Referring to fig. 2, an interlayer dielectric layer 120 is formed on the substrate exposed by the gate structure 200, and the interlayer dielectric layer 120 covers the gate structure 200, the source region 101 and the drain region 102. In this embodiment, the interlayer dielectric layer 120 is made of silicon oxide; in other embodiments, the material of the interlayer dielectric layer may also be silicon nitride or silicon oxynitride.
In this embodiment, the interlayer dielectric layer 120 is formed by a chemical vapor deposition process; in other embodiments, the interlayer dielectric layer 120 may also be formed by a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the process steps for forming the gate structure 200 and the source and drain regions 101 and 102 include: forming a dummy gate across the fin 110; forming a side wall 210 on the side wall of the pseudo gate; forming a source region 101 and a drain region 102 in the substrate at two sides of the dummy gate; forming a first dielectric layer on the substrate exposed out of the dummy gate, wherein the first dielectric layer is exposed out of the top of the dummy gate; removing the pseudo gate; forming a grid structure at the position of the dummy grid; an upper dielectric layer is formed on the first dielectric layer and on the top of the gate structure 200, and the first dielectric layer and the upper dielectric layer form the interlayer dielectric layer 120.
Referring to fig. 3, a first contact hole 310 is formed in the interlayer dielectric layer 120, and the first contact hole 310 exposes the surfaces of the source region 101 and the drain region 102.
The first contact hole 310 provides a process foundation for the subsequent formation of a conductive plug electrically connected with the source-drain doped region; in addition, the first contact hole 310 also provides a process basis for the subsequent formation of a metal silicide layer electrically connected to the source/drain doped region.
The process of forming the first contact hole 310 includes: forming a first photoresist layer (not shown) on the interlayer dielectric layer 120, wherein the first photoresist layer defines the position and the size of a first contact hole 310 to be formed; etching the interlayer dielectric layer 120 by using the first photoresist layer as a mask to form a first contact hole 310 penetrating through the interlayer dielectric layer 120, wherein the bottom of the first contact hole 310 exposes the surface of the source region 101 and the surface of the drain region 102; and removing the first photoresist layer.
After the first contact hole 310 is formed, a metal silicide stack is formed at the bottom of the first contact hole 310, the metal silicide stack at least comprises a stack unit, and the stack unit comprises a silicon layer and a metal layer which are sequentially formed at the bottom of the first contact hole 310.
In this embodiment, the metal silicide stack includes a stacked unit, which includes only a silicon layer formed at the bottom of the first contact hole 310 and a metal layer formed on the silicon layer. In other embodiments, the metal silicide stack may include a plurality of stacked units, i.e., a plurality of silicon layers and a plurality of metal layers cross-stacked, such as a silicon-metal layer-silicon-metal layer structure.
In this embodiment, the metal silicide stacked layer further includes a silicon layer formed on the stacked unit, and the metal silicide stacked layer has a structure of a silicon layer-metal layer-silicon layer.
The silicon layer formed on the stacked unit refers to a silicon layer formed on the topmost stacked unit, and a silicon layer is not formed on each stacked unit.
In other embodiments, the metal silicide stack may include only one or more stacked cells, and no silicon layer may be formed on the top-most stacked cell.
The forming of the metal silicide stacked layer means that when the metal silicide stacked layer includes a stacked unit, a silicon layer is deposited first, a metal layer is deposited next, and then a silicon layer may be deposited next on the metal layer or no silicon layer is deposited; when the metal silicide lamination layer comprises a plurality of stacking units, the silicon layer and the metal layer are arranged at intervals in the same way until the last stacking unit is formed, and then a layer of silicon layer can be deposited on the stacking unit at the topmost layer or no silicon layer can be deposited on the stacking unit at the topmost layer. And the thickness of the silicon layer deposited each time can be equal or unequal; the thickness of the metal layers deposited at each time may or may not be equal. In this embodiment, the thickness of the silicon layer deposited at each time is equal.
Specifically, the step of forming the metal silicide stack at the bottom of the first contact hole 310 includes:
referring to fig. 3, a metal silicide stack film is formed on the bottom and sidewalls of the first contact hole 310.
In this embodiment, the metal silicide stacked film includes a silicon layer 311 formed on the bottom and the sidewall of the first contact hole 310, a metal layer 312 formed on the silicon layer 311, and a silicon layer formed on the metal layer 312.
In this embodiment, the metal layer 312 is made of titanium; in other embodiments, the metal layer may also be metallic nickel or metallic cobalt.
In this embodiment, the method for depositing the silicon layer 311 is a chemical vapor deposition process; in other embodiments, the silicon layer may also be deposited using a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the method for depositing the metal layer 312 is an atomic layer deposition method; in other embodiments, the metal layer may also be deposited using physical vapor deposition, chemical vapor deposition, or electrochemical plating methods.
In this embodiment, the metal silicide stacked film further covers the surface of the interlayer dielectric layer 120.
The ratio of the thickness of the silicon layer to the thickness of the metal layer is 0.1-10. If the ratio is less than 0.1 or greater than 10, too much silicon material or too much metal material is generated, and silicon material or metal material is precipitated during the reaction, resulting in an increase in resistance.
The total thickness of the metal silicide stacked film formed on the bottom and the sidewall of the first contact hole 310 is 0.5nm or more and less than 30 nm. The total thickness of less than 0.5nm is difficult to be completed in the manufacturing process, and if the total thickness is more than or equal to 30nm, the thickness of the metal silicide layer formed subsequently is too thick, which affects the thickness of the conductive layer formed on the metal silicide layer and causes adverse effect on the resistance.
In the embodiment, the silicon layer 311, the metal layer 312 and the silicon layer 311 are sequentially formed by forming the metal silicide stacked film on the bottom and the side wall surface of the first contact hole 310, on one hand, the thickness of the metal silicide does not need to be increased by forming an amorphous layer, and the condition that the stress of a source drain epitaxial layer is lost in the pre-amorphization treatment process is avoided; on the other hand, when the silicon layer and the metal layer react to generate the metal silicide layer, silicon in the source drain region is prevented from being consumed, the silicon layer and the metal layer which are arranged at intervals can react more fully, cavities are prevented from occurring, the formed metal silicide is more uniform in components and better in quality, RC delay and contact resistance are reduced, and the performance of the semiconductor structure is improved.
Referring to fig. 4, the first contact hole 310 is filled with a sacrificial layer 400, and the sacrificial layer 400 also covers the surface of the metal silicide stacked film on the interlayer dielectric layer 120.
In this embodiment, the sacrificial layer 400 is a bottom anti-reflection layer; in other embodiments, the sacrificial layer 400 may also be a spin-on carbon-containing material layer.
In this embodiment, the method of forming the sacrificial layer 400 is spin coating; in other embodiments, the sacrificial layer may also be formed using a chemical vapor deposition process.
After the sacrificial layer 400 is formed, the sacrificial layer 400 is etched back to expose the metal silicide stacked film on the sidewall of the first contact hole 310 and expose the metal silicide stacked film on the surface of the interlayer dielectric layer 120.
The method for etching back the sacrificial layer 400 includes one or two of dry etching and wet etching. In this embodiment, the sacrificial layer 400 is etched back by a dry etching process.
Referring to fig. 5, the metal silicide stacked film on the sidewall of the first contact hole 310 is removed by etching, and the metal silicide stacked film on the surface of the interlayer dielectric layer 120 is removed at the same time, so as to form a metal silicide stack at the bottom of the first contact hole.
The method for removing the metal silicide stacked film by etching comprises one or two of dry etching and wet etching. In this embodiment, the metal silicide stacked film is removed by etching using a dry etching process.
After removing the metal silicide stacked film on the sidewall, the sacrificial layer 400 is removed.
In other embodiments, when the metal silicide stack is formed at the bottom of the first contact hole 310, the method further includes forming the metal silicide stack on the sidewall of the first contact hole 310, that is, after the metal silicide stack films are formed at the bottom and the sidewall of the first contact hole 310, the metal silicide stack film on the sidewall of the first contact hole 310 is not removed, and the metal silicide stack films at the bottom and the sidewall of the first contact hole 310 are used as the metal silicide stack, so that steps of forming a sacrificial layer and the like can be reduced, and the process flow can be simplified.
Referring to fig. 6, after a metal silicide stack is formed at the bottom of the first contact hole 310, a second contact hole 320 is formed in the interlayer dielectric layer 120, and the second contact hole 320 exposes the surface of the gate structure 200.
In this embodiment, since the gate structure 200 is a metal gate structure, it is not necessary to form a metal silicide layer to reduce the contact resistance, and therefore, it is not necessary to deposit a metal silicide stack in the second contact hole 320.
Referring to fig. 7, after the second contact hole 320 is formed, a barrier layer 500 is formed on the surface of the sidewall of the first contact hole 310, the surface of the metal silicide stack in the first contact hole 310, the sidewall and the bottom surface of the second contact hole 320.
In this embodiment, the barrier layer 500 also covers the top surface of the interlayer dielectric layer 120.
In this embodiment, the material of the barrier layer 500 is titanium nitride; in other embodiments, the material of the barrier layer 500 may also be tantalum nitride.
In this embodiment, the method of forming the barrier layer 500 includes a chemical vapor deposition method; in other embodiments, the barrier layer may also be formed using physical vapor deposition or atomic layer deposition.
In this embodiment, the barrier layer 500 is used to block the conductive metal in the first contact hole 310 and the second contact hole 320 from diffusing into the interlayer dielectric layer 120, and the barrier layer 500 on the interlayer dielectric layer 120 may be used as a polishing stop layer for subsequent polishing of the conductive metal material.
Referring to fig. 8, after the barrier layer 500 is formed, the metal silicide stack is annealed to react the silicon layer and the titanium layer in the metal silicide stack, thereby forming a metal silicide layer 600.
The annealing treatment comprises a temperature equalization annealing process, a spike annealing process, a flash annealing process or laser annealing. In this embodiment, a spike annealing process is used for annealing.
In this embodiment, the process parameters of the annealing treatment include: the annealing temperature is 400-1000 ℃, the annealing time is 0.4-60 seconds, the annealing atmosphere comprises one or more of nitrogen, hydrogen, ammonia, oxygen or argon, and the annealing pressure is 0.001-780 torr.
Referring to fig. 9, after the metal silicide layer 600 is formed, the first contact hole 310 and the second contact hole 320 are filled with a conductive layer 330 to form a conductive plug.
In this embodiment, the step of forming the conductive plug specifically includes: filling the first contact hole 310 and the second contact hole 320 with a conductive material layer (not shown), wherein the conductive material layer also covers the barrier layer 500 on the top surface of the interlayer dielectric layer 120; and carrying out chemical mechanical polishing on the conductive material layer until the surface of the interlayer dielectric layer 120 is exposed, so as to form the conductive plug.
In this embodiment, the conductive material layer is made of metal tungsten; in other embodiments, the material of the conductive material layer may also be aluminum, copper, platinum, cobalt, or the like.
In this embodiment, the method for filling the conductive material layer is an atomic layer deposition method; in other embodiments, the conductive material layer may be filled by chemical vapor deposition, physical vapor deposition, or electrochemical plating.
In this embodiment, the contact resistance is reduced and the RC delay is reduced by forming the metal silicide layer at the bottom of the first contact hole 310, and the silicon layer and the metal layer are deposited by stacking the metal silicide layer without performing pre-amorphization treatment, so that the source-drain stress loss caused in the pre-amorphization treatment process is avoided.
Second embodiment
Fig. 10 to 16 are schematic structural views corresponding to steps of a method for forming a semiconductor structure according to a second embodiment of the present invention.
In this embodiment, the gate structure 200 is a polysilicon gate structure, and in order to reduce the contact resistance and the contact capacitance of the conductive plug on the polysilicon gate structure, a metal silicide layer is also required to be formed in the contact hole on the polysilicon gate structure.
In this embodiment, the step of providing the substrate is the same as that in the first embodiment, and is not described herein again.
Referring to fig. 10, in this embodiment, the process steps of forming the gate structure 200 and the source region 101 and the drain region 102 include: forming a gate structure 200 and side walls 210 positioned at two sides of the gate structure 200 on the substrate; and forming a source region 101 and a drain region 102 in the substrate at two sides of the gate structure 200.
The subsequent process steps further comprise: an interlevel dielectric layer 120 is formed on the substrate where the gate structure 200 is exposed and on top of the gate structure 200.
Referring to fig. 11, after forming the interlayer dielectric layer 120, a first contact hole 310 and a second contact hole 320 are formed in the interlayer dielectric layer 120, the first contact hole 310 exposes the surfaces of the source region 101 and the drain region 102, and the second contact hole 320 exposes the surface of the gate structure 200.
After the first contact hole 310 and the second contact hole 320 are formed, a metal silicide stack is formed at the bottom of the first contact hole 310 and the second contact hole 320.
Specifically, the step of forming the metal silicide stack at the bottoms of the first contact hole 310 and the second contact hole 320 includes:
referring to fig. 12, a metal silicide stack film is formed on the bottom and sidewalls of the first contact hole 310 and the bottom and sidewalls of the second contact hole 320, the metal silicide stack film also covering the surface of the interlayer dielectric layer 120;
filling a sacrificial layer (not shown) in the first contact hole 310 and the second contact hole 320, wherein the sacrificial layer also covers the surface of the metal silicide stacked film on the interlayer dielectric layer 120;
and etching back the sacrificial layer to expose the metal silicide stacked film on the side wall of the first contact hole 310 and the side wall of the second contact hole 320, and simultaneously exposing the metal silicide stacked film on the surface of the interlayer dielectric layer 120.
Referring to fig. 13, the metal silicide stacked film on the sidewalls of the first contact hole 310 and the second contact hole 320 is removed.
In this embodiment, the method of removing the metal silicide stacked film on the sidewalls of the first contact hole 310 and the second contact hole 320 is the same as that described in the first embodiment, and is not repeated herein.
Also, in other embodiments, when forming the metal silicide stack at the bottom of the first contact hole 310 and the second contact hole 320, the metal silicide stack is also formed on the sidewalls of the first contact hole 310 and the second contact hole 320, i.e., the metal silicide stack is formed on the sidewalls of the first contact hole 310 and the second contact hole 320 without removing the metal silicide stack film on the sidewalls of the first contact hole 310 and the second contact hole 320.
Referring to fig. 14, a barrier layer 500 is formed on the sidewall surface of the first contact hole 310, the sidewall surface of the second contact hole 320, and the surface of the metal silicide stack.
In this embodiment, the material and the forming method of the barrier layer 500 are the same as those described in the first embodiment, and are not repeated herein.
Referring to fig. 15, the metal silicide stack is annealed to obtain a metal silicide layer.
In this embodiment, the process and process parameters of the annealing treatment are the same as those described in the first embodiment, and are not described herein again.
Referring to fig. 16, the first contact hole 310 and the second contact hole 320 are filled with a conductive layer 330 to form a conductive plug.
In this embodiment, the material and the forming method of the conductive layer 330 are the same as those described in the first embodiment, and are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, forming a grid structure on the substrate, wherein a source region and a drain region are arranged in the substrate at two sides of the grid structure;
forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the grid structure, the source region and the drain region;
forming a first contact hole in the interlayer dielectric layer, wherein the first contact hole exposes the source region and the drain region;
forming a metal silicide lamination at the bottom of the first contact hole, wherein the metal silicide lamination at least comprises a stacking unit, and the stacking unit comprises a silicon layer and a metal layer which are sequentially formed at the bottom of the first contact hole;
and annealing the metal silicide lamination to obtain the metal silicide layer.
2. The method of forming a semiconductor structure of claim 1, wherein the metal silicide stack further comprises a silicon layer formed on a surface of the stacked cell.
3. The method of claim 2, wherein a ratio of a thickness of the silicon layer to a thickness of the metal layer in the metal silicide stack is 0.1 to 10.
4. The method of forming a semiconductor structure of claim 3, wherein a total thickness of the metal silicide stack is between 0.5nm and 30 nm.
5. The method of forming a semiconductor structure of claim 1, wherein when the gate structure is a metal gate structure, after forming the metal silicide stack at the bottom of the first contact hole, further comprising: and forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole exposes the surface of the grid structure.
6. The method of forming a semiconductor structure of claim 1, wherein when the gate structure is a polysilicon gate structure, prior to forming the metal silicide stack at the bottom of the first contact hole, further comprising: and forming a second contact hole in the interlayer dielectric layer, wherein the second contact hole exposes the surface of the grid structure.
7. The method of forming a semiconductor structure of claim 6, wherein after forming the second contact hole, a metal silicide stack is formed at a bottom of the first contact hole and at a bottom of the second contact hole.
8. The method of forming a semiconductor structure of claim 5, further comprising, after forming the second contact hole: and forming a barrier layer on the side wall and the bottom of the first contact hole and on the side wall and the bottom of the second contact hole.
9. The method of forming a semiconductor structure of claim 7, further comprising, after forming a metal silicide stack at a bottom of said first contact hole and at a bottom of said second contact hole: and forming a barrier layer on the side wall and the bottom of the first contact hole and on the side wall and the bottom of the second contact hole.
10. The method of forming a semiconductor structure of claim 1, wherein forming the metal silicide stack at the bottom of the first contact hole comprises:
forming a metal silicide stacked film on the bottom and the side wall of the first contact hole;
filling the first contact hole with a sacrificial layer;
etching back the sacrificial layer to expose the metal silicide stacked film on the side wall of the first contact hole;
and etching to remove the metal silicide stacked film on the side wall of the first contact hole, and forming a metal silicide stacked layer at the bottom of the first contact hole.
11. The method of claim 10, wherein the material of the sacrificial layer comprises a bottom anti-reflective material or a spin-on carbon-containing compound.
12. The method of forming a semiconductor structure of claim 1, wherein forming a metal silicide stack at a bottom of said first contact hole further comprises: and forming a metal silicide laminated layer on the side wall of the first contact hole.
13. The method of forming a semiconductor structure of claim 7, wherein forming a metal silicide stack at the bottom of the first contact hole and at the bottom of the second contact hole further comprises: and forming a metal silicide lamination layer on the side wall of the first contact hole and the side wall of the second contact hole.
14. The method of claim 1, wherein the annealing process comprises an isothermal annealing process, a spike annealing process, a flash annealing process, or a laser annealing process.
15. The method of forming a semiconductor structure of claim 14, wherein the process parameters of the annealing process comprise: the annealing temperature is 400-1000 ℃, the annealing time is 0.4-60 seconds, the annealing atmosphere comprises one or more of nitrogen, hydrogen, ammonia, oxygen or argon, and the annealing pressure is 0.001-780 torr.
16. The method of forming a semiconductor structure of claim 1, wherein a material of the metal layer comprises titanium or nickel or cobalt.
17. The method of claim 8 or 9, wherein the material of the barrier layer comprises titanium nitride or tantalum nitride.
18. The method of forming a semiconductor structure of claim 8 or 9, further comprising, after forming the barrier layer: and filling a conductive layer in the first contact hole and the second contact hole.
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| US6376368B1 (en) * | 1999-08-05 | 2002-04-23 | Samsung Electronics Co., Ltd. | Method of forming contact structure in a semiconductor device |
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| US6376368B1 (en) * | 1999-08-05 | 2002-04-23 | Samsung Electronics Co., Ltd. | Method of forming contact structure in a semiconductor device |
| JP2006108452A (en) * | 2004-10-06 | 2006-04-20 | Renesas Technology Corp | Method of manufacturing semiconductor device |
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