CN113451883A - VCSEL chip and preparation method thereof - Google Patents
VCSEL chip and preparation method thereof Download PDFInfo
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- CN113451883A CN113451883A CN202110519335.4A CN202110519335A CN113451883A CN 113451883 A CN113451883 A CN 113451883A CN 202110519335 A CN202110519335 A CN 202110519335A CN 113451883 A CN113451883 A CN 113451883A
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- silicon nitride
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- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 abstract description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 12
- 238000007796 conventional method Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18344—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] characterized by the mesa, e.g. dimensions or shape of the mesa
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention discloses a VCSEL chip and a preparation method thereof, and relates to the technical field of laser chips. The VCSEL chip comprises a substrate and an epitaxial structure positioned on one side of the substrate, wherein the epitaxial structure comprises an N-DBR structure, an MQW active layer, an oxidation layer and a P-DBR structure which are sequentially deposited from bottom to top, a first silicon nitride layer is deposited on the P-DBR structure, the first silicon nitride layer and the P-DBR structure are etched downwards to form a table top, a P-contact circular ring is arranged on the table top, a second silicon nitride layer is deposited on the substrate from top to bottom to the first silicon nitride layer, and a P-ohmic is evaporated on the second silicon nitride layer at a position corresponding to the P-contact circular ring. The invention discloses a VCSEL chip and a preparation method thereof, and the intrinsic resistance of the chip can be effectively reduced by reducing the distance from P-contact to an MQW active layer, so that the optical performance of the chip is improved, and the efficiency is improved.
Description
Technical Field
The invention relates to the technical field of laser chips, in particular to a VCSEL chip and a preparation method thereof.
Background
The VCSEL is a vertical cavity surface emitting laser, is developed on the basis of gallium arsenide semiconductor materials, is different from other light sources such as an LED (light emitting diode) and an LD (laser diode), has the advantages of small volume, circular output light spots, single longitudinal mode output, small threshold current, low price, easiness in integration into a large-area array and the like, and is widely applied to the fields of optical communication, optical interconnection, optical storage and the like.
The VCSEL is used as a semiconductor laser, electrons exciting a semiconductor jump from a valence band to a conduction band, and energy is released in the form of light energy when the electrons jump from the conduction band back to the valence band, as shown in FIG. 1, a traditional VCSEL chip structure respectively comprises a substrate, an N-DBR, an MQW active layer, an oxide layer, a P-DBR, a P-contact and a P-ohmic contact from bottom to top, the external delay is generated in the traditional VCSEL, 10-20 pairs of P-DBRs taking AlGaAs as materials are grown on the MQW active layer, and the P-DBRs have influence on the resistance value of a chip due to more pairs of the P-DBRs, and current must pass through the DBRs to reach the MQW active layer to play a role, so that attenuation is realized in the process, and the efficiency of the chip is greatly reduced.
Disclosure of Invention
In view of the above problems, an object of the present invention is to disclose a VCSEL chip and a fabrication method thereof, which can effectively reduce the intrinsic resistance of the chip, improve the optical performance of the chip, and improve the efficiency by reducing the distance from the P-contact to the MQW active layer.
The VCSEL chip comprises a substrate and an epitaxial structure located on one side of the substrate, wherein the epitaxial structure comprises an N-DBR structure, an MQW active layer, an oxidation layer and a P-DBR structure which are sequentially deposited from bottom to top, a first silicon nitride layer is deposited on the P-DBR structure, the first silicon nitride layer and the P-DBR structure are etched downwards to form a table top, a P-contact circular ring is arranged on the table top, a second silicon nitride layer is deposited on the substrate from top to bottom to the first silicon nitride layer, and a P-ohmic layer is evaporated on the second silicon nitride layer at a position corresponding to the P-contact circular ring.
Further, the P-DBR structure comprises 10-20 pairs of DBR layers which are grown in an overlapping manner.
Further, 2-3 pairs of DBR layers are arranged between the MQW active layer and the P-contact circular ring.
Further, the material of the substrate is GaAs.
Further, the material of the P-contact circular ring is C or Ge.
In addition, the invention also discloses a preparation method of the high-efficiency VCSEL chip, which comprises the following steps:
providing a GaAs substrate, and sequentially growing an N-DBR structure, an MQW active layer, an oxidation layer and a P-DBR structure on the GaAs substrate;
depositing silicon nitride on the P-DBR to form a first silicon nitride layer;
etching the first silicon nitride layer and the P-DBR structure until 2-3 pairs of DBR layers remain in the P-DBR structure to form a table top;
forming a P-contact circular ring on the table top;
depositing silicon nitride from the GaAs substrate up to the first silicon nitride layer to obtain a second silicon nitride layer;
etching the second silicon nitride layer to a P-contact circular ring to obtain a P-ohmic groove;
and evaporating metal in the P-ohmic groove to form the P-ohmic. The material of the P-ohmic may be, but is not limited to, Ti, Pt, or Au.
Further, the P-contact circular ring is obtained by deposition or secondary epitaxy of a high-doped layer.
Further, when the P-contact ring is obtained as a secondary epitaxial highly doped layer, the highly doped layer outside the P-contact ring needs to be etched away before depositing the second silicon nitride layer.
The invention has the beneficial effects that:
the invention discloses a VCSEL chip, wherein a traditional single step is changed into a double step, the distance from a P-contact circular ring to an MQW active layer is reduced, the internal resistance of the chip can be effectively reduced only by 2-3 pairs of DBR layers, and the optical performance of the chip is improved.
Drawings
Fig. 1 is a schematic structural diagram of a conventional VCSEL chip;
fig. 2-6 are schematic structural diagrams corresponding to steps of a method for fabricating a VCSEL chip according to the present invention;
the device comprises a substrate 1, an N-DBR structure 2, an MQW active layer 3, an oxide layer 4, a P-DBR structure 5, a first silicon nitride layer 6, a table top 7, a P-contact circular ring 8, a second silicon nitride layer 9 and a P-ohmic 10.
Detailed Description
The present invention will be described in detail with reference to specific embodiments, and it is apparent that the described embodiments are only a part of the embodiments of the present application, rather than all embodiments, and all other embodiments obtained by those skilled in the art without inventive work based on the embodiments in the present application are within the scope of the present application. In addition, the process parameters which are not specially limited in the invention all adopt the conventional process parameters of the VCSEL chip.
As shown in fig. 6, the VCSEL chip of the present invention includes a substrate 1 and an epitaxial structure located on one side of the substrate 1, wherein the substrate is a GaAs substrate 1, the epitaxial structure includes a N-DBR structure 2, a MQW active layer 3, an oxide layer 4, and a P-DBR structure 5 deposited in sequence from bottom to top, the P-DBR includes 10-20 pairs of DBR layers grown in an overlapping manner, a first silicon nitride layer 6 with a thickness of 800-, the second silicon nitride layer 9 with the thickness of 2500-.
By using the chip, the structure of the chip is changed, the traditional single step structure is changed into a double-step structure, the logarithm of a DBR layer between a P-contact ring and an MQW active layer is reduced, the distance from the P-contact ring to the MQW active layer is shortened, the internal resistance of the chip can be effectively reduced, and the optical performance of the chip is improved. The following describes the technical solutions provided by the embodiments of the present invention in more detail with reference to the manufacturing method of the high efficiency VCSEL chip and the accompanying drawings fig. 2-6.
Example one
The preparation method of the high-efficiency VCSEL chip comprises the following steps:
s1: providing a GaAs substrate 1, and sequentially growing an N-DBR structure 2, an MQW active layer 3, an oxidation layer 4 and a P-DBR structure 5 on the GaAs substrate 1 according to a conventional method;
s2: depositing silicon nitride on the P-DBR by a conventional method using a PECVD apparatus to form a first silicon nitride layer 6, as shown in fig. 2;
s3: as shown in fig. 3, the first silicon nitride layer 6 and the P-DBR structure 5 are etched until 2-3 DBR layers remain in the P-DBR structure 5, so as to form a mesa 7;
s4: as shown in fig. 4, depositing C or Ge material on the mesa 7 results in a P-contact ring 8;
s5: as shown in fig. 5, a second silicon nitride layer 9 is obtained by depositing silicon nitride from the GaAs substrate 1 up to the first silicon nitride layer 6 according to a conventional method;
s6: etching the second silicon nitride layer 9 to the P-contact circular ring 8 to obtain a P-ohmic groove;
s7: as shown in FIG. 6, P-ohmic10 is formed by evaporating metal in the P-ohmic grooves, the evaporated metal can be but is not limited to Ti, Pt or Au.
Example two
In addition, the P-contact ring 8 can also be obtained by secondary epitaxy of a highly doped layer, and the method specifically comprises the following steps:
s1: providing a GaAs substrate 1, and sequentially growing an N-DBR structure 2, an MQW active layer 3, an oxidation layer 4 and a P-DBR structure 5 on the GaAs substrate 1;
s2: depositing silicon nitride on the P-DBR to form a first silicon nitride layer 6;
s3: etching the first silicon nitride layer 6 and the P-DBR structure 5 until 2-3 pairs of DBR layers remain in the P-DBR structure 5 to form a table top 7;
s4: obtaining a P-contact circular ring 8 on the table top 7 through secondary epitaxy high doping layer;
s5: etching off the high-doped layer outside the P-contact circular ring 8, and then depositing silicon nitride from the GaAs substrate 1 upwards onto the first silicon nitride layer 6 to obtain a second silicon nitride layer 9;
s6: etching the second silicon nitride layer 9 to the P-contact circular ring 8 to obtain a P-ohmic groove;
s7: metal is evaporated in the P-ohmic grooves to form P-ohmic 10.
Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims. The techniques, shapes, and configurations not described in detail in the present invention are all known techniques.
Claims (8)
1. The VCSEL chip comprises a substrate and an epitaxial structure located on one side of the substrate, wherein the epitaxial structure comprises an N-DBR structure, an MQW active layer, an oxidation layer and a P-DBR structure which are sequentially deposited from bottom to top, and is characterized in that a first silicon nitride layer is deposited on the P-DBR structure, the first silicon nitride layer and the P-DBR structure are etched downwards to form a table top, a P-contact circular ring is arranged on the table top, a second silicon nitride layer is deposited on the substrate upwards to the first silicon nitride layer, and the second silicon nitride layer is evaporated with P-ohmic at the position corresponding to the P-contact circular ring.
2. A VCSEL chip in accordance with claim 1, wherein said P-DBR structure comprises 10-20 pairs of DBR layers grown one above the other.
3. A VCSEL chip according to claim 2, wherein said MQW active layer and P-contact annular ring are separated by 2-3 DBR layers.
4. A VCSEL chip in accordance with claim 3, wherein said substrate is made of GaAs.
5. A VCSEL chip as claimed in any of claims 1 to 4, wherein the material of the P-contact ring is C or Ge.
6. A method for fabricating a VCSEL chip, the method comprising the steps of:
providing a GaAs substrate, and sequentially growing an N-DBR structure, an MQW active layer, an oxidation layer and a P-DBR structure on the GaAs substrate;
depositing silicon nitride on the P-DBR to form a first silicon nitride layer;
etching the first silicon nitride layer and the P-DBR structure until 2-3 pairs of DBR layers remain in the P-DBR structure to form a table top;
forming a P-contact circular ring on the table top;
depositing silicon nitride from the GaAs substrate up to the first silicon nitride layer to obtain a second silicon nitride layer;
etching the second silicon nitride layer to a P-contact circular ring to obtain a P-ohmic groove;
and evaporating metal in the P-ohmic groove to form the P-ohmic.
7. A method according to claim 6, wherein said P-contact ring is formed by depositing or double-epitaxially growing a highly doped layer.
8. The method as claimed in claim 7, wherein when the P-contact ring is obtained as a secondary epitaxial highly doped layer, the highly doped layer is etched away before depositing the second silicon nitride layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110519335.4A CN113451883A (en) | 2021-05-12 | 2021-05-12 | VCSEL chip and preparation method thereof |
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| CN202110519335.4A CN113451883A (en) | 2021-05-12 | 2021-05-12 | VCSEL chip and preparation method thereof |
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2021
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