CN113380930B - Deep ultraviolet light emitting diode and manufacturing method thereof - Google Patents

Deep ultraviolet light emitting diode and manufacturing method thereof Download PDF

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CN113380930B
CN113380930B CN202110656123.0A CN202110656123A CN113380930B CN 113380930 B CN113380930 B CN 113380930B CN 202110656123 A CN202110656123 A CN 202110656123A CN 113380930 B CN113380930 B CN 113380930B
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layer
superlattice
deep ultraviolet
emitting diode
ultraviolet light
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CN113380930A (en
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郑锦坚
毕京锋
高默然
范伟宏
曾家明
张成军
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Hangzhou Silan Azure Co Ltd
Xiamen Silan Advanced Compound Semiconductor Co Ltd
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Hangzhou Silan Azure Co Ltd
Xiamen Silan Advanced Compound Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

The invention provides a deep ultraviolet light-emitting diode and a manufacturing method thereof, and the deep ultraviolet light-emitting diode comprises a substrate, a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer from bottom to top, wherein the stress control layer is Al a Ga 1‑a N/Al b Ga 1‑b N superlattice layer and Al c Ga 1‑c One or two of the N non-superlattice layers, the Al a Ga 1‑a N/Al b Ga 1‑b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1‑a N layer and Al b Ga 1‑b N layer of said Al c Ga 1‑c The N non-superlattice layer comprises at least two layers of structures with Al components arranged in a gradient manner. According to the technical scheme, lattice mismatch and thermal mismatch between the template layer and the n-type semiconductor layer can be relieved, stress can be gradually released, and surface cracks are improved.

Description

Deep ultraviolet light emitting diode and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a deep ultraviolet light-emitting diode and a manufacturing method thereof.
Background
The deep ultraviolet nitride semiconductor light-emitting element has a wavelength range of 200 nm-300 nm, can interrupt DNA or RNA of virus and bacteria due to the emitted deep ultraviolet light, directly kills the virus and the bacteria, and is widely applied to the sterilization and disinfection fields of air purification, tap water sterilization, household air conditioner sterilization, automobile air conditioner sterilization and the like. The deep ultraviolet nitride semiconductor light emitting element generally uses AlGaN-based materials to epitaxially grow on a sapphire substrate; due to the fact that lattice mismatch and thermal mismatch exist between AlGaN and sapphire, the AlGaN-based material is subjected to the mismatch stress of the sapphire substrate when being epitaxially grown, and the AlGaN-based material generates more dislocation, defects, cracks and the like.
In the deep ultraviolet nitride semiconductor light-emitting element with high Al component, the AlN layer and the n-type AlGaN layer are sequentially formed on the substrate, so that the problems of lattice mismatch and thermal mismatch between the AlN layer and the substrate are high, the surface is easy to have roughness, no elongation and cracks, and the problems of lattice mismatch and thermal mismatch and easy generation of cracks also exist between the AlN layer and the n-type AlGaN layer. Cracks between the AlN layer and the substrate generally adopt a buffer layer technology to release stress between the substrate and the AlN layer so as to improve the crystal quality of the AlN layer and reduce dislocation density; however, no good solution is provided for the problem of cracking caused by lattice mismatch and thermal mismatch between the AlN layer and the n-type AlGaN layer (for example, when the thickness of n-type AlGaN layer is greater than 2 μm or the Al composition is low, cracking is likely to occur).
Therefore, a deep ultraviolet light emitting diode and a manufacturing method thereof are provided to solve the problem of cracks caused by lattice mismatch and thermal mismatch between an AlN layer and an n-type AlGaN layer.
Disclosure of Invention
The invention aims to provide a deep ultraviolet light-emitting diode and a manufacturing method thereof, so that lattice mismatch and thermal mismatch between a template layer and an n-type semiconductor layer can be relieved, stress can be gradually released, and surface cracks can be improved.
In order to achieve the above purpose, the present invention provides a deep ultraviolet light emitting diode, which comprises a substrate, a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer from bottom to top, wherein the stress control layer is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c One or two of N non-superlattice layers, the Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprisesPeriodically alternating stacked Al a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components arranged in a gradient manner.
Optionally, the template layer is an AlN layer.
Optionally, the n-type semiconductor layer is n-type Al x Ga 1-x N layer, x is more than or equal to 0.4<0.8。
Optionally, the stress control layer is the Al a Ga 1-a N/Al b Ga 1-b N superlattice layer, x<0.8<b<0.9<a<1。
Optionally, the Al in each period a Ga 1-a N layer is compared with the Al layer b Ga 1-b N layer closer to the template layer, or the Al in each period b Ga 1-b N layer is more than the Al layer a Ga 1-a The N layer is closer to the template layer.
Optionally, the number of cycles of the periodic alternating stack is greater than 1 and less than 50.
Alternatively, the Al a Ga 1-a N/Al b Ga 1-b The thickness of the N superlattice layer is less than 200 nm.
Optionally, the stress control layer is the Al c Ga 1-c N non-superlattice layer, x<c≤0.8。
Alternatively, the Al c Ga 1-c The gradient layer number N of the Al component in the N non-superlattice layer is (c-x)/m, wherein m is the gradient of the Al component, and N is>1。
Alternatively, 0 ≦ m ≦ 0.3.
Alternatively, the Al c Ga 1-c And Al components of each layer structure in the N non-superlattice layer decrease from bottom to top layer by layer.
Alternatively, the Al c Ga 1-c And the Al components of each layer structure in the N non-superlattice layer can be lifted and descended randomly from bottom to top.
Alternatively, the Al c Ga 1-c The thickness of the N non-superlattice layer is more than 100 nm.
Optionally, said stress controlThe layers are made of Al stacked from bottom to top a Ga 1-a N/Al b Ga 1-b N superlattice layer and the Al c Ga 1-c And N non-superlattice layers.
Optionally, the p-type semiconductor layer is p-type Al y Ga 1-y And y is more than or equal to 0.45 and less than or equal to 1.
Optionally, the deep ultraviolet light emitting diode further comprises a p-type contact layer on the p-type semiconductor layer.
Optionally, the p-type contact layer is p-type Al z Ga 1-z And z is more than or equal to 0 and less than or equal to 0.4.
Optionally, the thickness of the p-type contact layer is 20nm to 400 nm.
The invention also provides a manufacturing method of the deep ultraviolet light-emitting diode, which comprises the following steps:
providing a substrate; and (c) a second step of,
sequentially forming a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the substrate, wherein the stress control layer is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c One or two of the N non-superlattice layers, the Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components arranged in a gradient manner.
Optionally, the template layer is an AlN layer.
Optionally, the n-type semiconductor layer is n-type Al x Ga 1-x N layer, x is more than or equal to 0.4<0.8。
Optionally, the stress control layer is the Al a Ga 1-a N/Al b Ga 1-b N superlattice layer, x<0.8<b<0.9<a<1。
Optionally, the Al in each period a Ga 1-a N layer is compared with the Al layer b Ga 1-b N layer closer to the template layer, or the Al in each cycle b Ga 1-b N layer is more than the Al layer a Ga 1-a The N layer is closer to the template layer.
Optionally, the number of cycles of the periodic alternating stack is greater than 1 and less than 50.
Alternatively, the Al a Ga 1-a N/Al b Ga 1-b The thickness of the N superlattice layer is less than 200 nm.
Optionally, the stress control layer is the Al c Ga 1-c N non-superlattice layer, x<c≤0.8。
Alternatively, the Al c Ga 1-c The gradient layer number N of the Al component in the N non-superlattice layer is (c-x)/m, wherein m is the gradient of the Al component, and N is>1。
Alternatively, 0 ≦ m ≦ 0.3.
Alternatively, the Al c Ga 1-c And Al components of each layer structure in the N non-superlattice layer decrease from bottom to top layer by layer.
Alternatively, the Al c Ga 1-c And the Al components of each layer structure in the N non-superlattice layer can be lifted and descended randomly from bottom to top.
Alternatively, the Al c Ga 1-c The thickness of the N non-superlattice layer is larger than 100 nm.
Optionally, the stress control layer is Al stacked from bottom to top a Ga 1-a N/Al b Ga 1-b N superlattice layer and said Al c Ga 1-c And N non-superlattice layers.
Optionally, the p-type semiconductor layer is p-type Al y Ga 1-y And y is more than or equal to 0.45 and less than or equal to 1.
Optionally, the manufacturing method of the deep ultraviolet light emitting diode further includes: and forming a p-type contact layer on the p-type semiconductor layer.
Optionally, the p-type contact layer is p-type Al z Ga 1-z And z is more than or equal to 0 and less than or equal to 0.4.
Optionally, the thickness of the p-type contact layer is 20nm to 400 nm.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the deep ultraviolet light-emitting diode and the manufacturing method thereof, the stress control layer is formed between the template layer and the n-type semiconductor layer and is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c One or two of the N non-superlattice layers, the Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components arranged in a gradient manner, so that lattice mismatch and thermal mismatch between the template layer and the N-type semiconductor layer can be relieved, stress can be gradually released, and surface cracks can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a deep ultraviolet led according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a deep ultraviolet led according to an embodiment of the invention.
Wherein the reference numerals of figures 1 to 2 are as follows:
11-a substrate; 12-a template layer; 13-a stress control layer; 131-Al a Ga 1-a N/Al b Ga 1-b An N superlattice layer; 132-Al c Ga 1-c An N non-superlattice layer; a 14-n type semiconductor layer; 15-quantum well layer; a 16-p type semiconductor layer; 17-p type contact layer.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the deep ultraviolet light emitting diode and the method for manufacturing the same according to the present invention will be described in further detail below. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the invention provides a deep ultraviolet light emitting diode, which comprises a substrate, a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer from bottom to top, wherein the stress control layer is arranged on the substrate and is used for controlling the stress of the n-type semiconductor layerThe control layer is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c One or two of the N non-superlattice layers, the Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components in gradient arrangement.
The deep ultraviolet led provided in this embodiment is described in more detail with reference to fig. 1, and fig. 1 is a schematic longitudinal cross-sectional view of the deep ultraviolet led.
The substrate 11 is made of at least one material selected from sapphire, silicon carbide, aluminum nitride, gallium oxide, and the like.
The template layer 12, the stress control layer 13 and the n-type semiconductor layer 14 are sequentially formed on the substrate 11 by means of epitaxial growth.
The template layer 12 is an AlN layer for improving the growth quality of subsequently formed structures.
The stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and Al c Ga 1-c One or two stacked structures of N non-superlattice layers 132, and Al a Ga 1-a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N-amorphous lattice layer 132 includes a stacked structure of at least two layers having a gradient arrangement of Al components.
The n-type semiconductor layer 14 is n-type Al x Ga 1-x And the N layer is used for providing electrons.
The n-type Al x Ga 1-x The N layer is doped with silicon.
The n-type Al x Ga 1-x The range of the Al component x in the N layer is more than or equal to 0.4 and less than or equal to x<0.8。
Wherein, if the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 of Al a Ga 1- a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b And N layers.
The Al is a Ga 1-a N layer and the Al b Ga 1-b The Al components a and b in the N layer are in the range of x<0.8<b<0.9<a<1, then, the Al a Ga 1-a The content of Al component in the N layer is larger than that of Al b Ga 1-b Content of Al component in N layer, the Al b Ga 1-b The content of Al component in the N layer is larger than that of the N-type Al x Ga 1-x Content of Al component in the N layer. Therefore, the Al in each cycle is preferred a Ga 1-a N layer is compared with the Al layer b Ga 1-b The N layer is closer to the template layer 12 such that the Al passes from the template layer 12 through a Ga 1-a N/Al b Ga 1-b The content of Al component is generally gradually decreased from the N-superlattice layer 131 to the N-type semiconductor layer 14, so that the crystal lattice is also in a gradual trend, and thus the stress caused by the lattice mismatch and the thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be gradually released.
In other embodiments, Al may be present in each period b Ga 1-b N layer is compared with the Al layer a Ga 1-a The N layer is closer to the template layer 12.
The Al is a Ga 1-a N layer and the Al b Ga 1-b The number of cycles of the N layers of the periodic alternating stack may be more than 1 and less than 50, and the Al is controlled a Ga 1-a N/Al b Ga 1-b The thickness of the N-superlattice layer 131 is less than 200nm, so that the stress release effect is optimal, the problem of excessive stress regulation caused by too large cycle number and too large thickness is avoided, and further more serious cracks caused by adverse effects are avoided.
Or, if the stress control layer 13 is Al c Ga 1-c N non-superlattice layer 132 of Al c Ga 1-c The N-amorphous lattice layer 132 includes a stacked structure of at least two layers having a gradient arrangement of Al components.
The Al is c Ga 1-c The Al component c of each layer structure in the N non-superlattice layer 132 is in the range of x<c is less than or equal to 0.8, then, the Al c Ga 1-c The content of the Al component of each layer structure in the N non-superlattice layer 132 is larger than the content of the Al component in the N-type semiconductor layer 14.
Preferably the Al c Ga 1-c The Al composition of each layer structure in the N non-superlattice layer 132 decreases from bottom to top (i.e., the layer with the largest Al composition content is close to the template layer 12) so as to pass from the template layer 12 through the Al c Ga 1-c The content of Al component decreases from layer to layer from each layer of the N-amorphous lattice layer 132 to the N-type semiconductor layer 14, so that the lattice also has a gradual change trend, and the stress caused by lattice mismatch and thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be gradually released.
In other embodiments, the Al is c Ga 1-c The Al component of each layer structure in the N-amorphous lattice layer 132 may also be arbitrarily ascending and descending from bottom to top, such as ascending layer by layer and then descending layer by layer, or descending layer by layer and then ascending layer by layer, or ascending layer by layer and descending layer by layer alternately.
The Al is c Ga 1-c The number of gradient layers N of the Al component in the N non-superlattice layer 132 is (c-x)/m, where m is a gradient of the Al component, and m may be 0 or more and 0.3 or less; n is a radical of an alkyl radical>1。
Since x is more than or equal to 0.4<c is less than or equal to 0.8, and taking c as 0.75, x as 0.55 and m as 0.05 as examples, the gradient layer number n as 4 can be calculated according to the formula n as (c-x)/m, namely the Al c Ga 1-c The N non-superlattice layer 132 comprises 4 stacked structures with Al components arranged in a gradient manner, the gradient of the Al components between adjacent layers is 0.05, and the 4 stacked structures are sequentially made of Al from bottom to top 0.75 Ga 0.25 N layer, Al 0.7 Ga 0.3 N layer, Al 0.65 Ga 0.35 N layer and Al 0.6 Ga 0.4 N layer such that Al passes from the template layer 12 through c Ga 1-c Layers in the N-amorphous lattice layer 132 to the N-type semiconductor layer 14 (i.e., N-type Al 0.55 Ga 0.45 N layer), the content of the Al component decreases layer by layer.
The Al is c Ga 1-c The thickness of the N-type amorphous lattice layer 132 is greater than 100nm, so that the stress release effect is optimal, and the problem that the effective stress control effect cannot be realized due to too small thickness is avoided.
Or, if the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The stacked structure of N non-superlattice layers 132 is not less than 0.4 x<c≤ 0.8<b<0.9<a<1, then, the Al a Ga 1-a The content of Al component in the N layer is larger than that of Al b Ga 1-b Content of Al component in N layer, the Al b Ga 1-b The content of Al component in the N layer is larger than that of Al c Ga 1-c The content of Al component of each layer structure in the N non-superlattice layer 132, and the Al c Ga 1-c The content of Al component of each layer structure in the N non-superlattice layer 132 is greater than that of the N-type Al x Ga 1-x Content of Al component in N layer, therefore, it is preferable that Al is contained in each period a Ga 1-a N layer is more than the Al layer b Ga 1-b The N layer is closer to the template layer 12 and preferably the Al c Ga 1-c In the N-amorphous layer 132, the Al composition of each layer structure decreases from bottom to top, and it is more preferable that the Al composition decreases from bottom to top a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The N-amorphous lattice layers 132 are stacked from bottom to top (as shown in fig. 1, i.e., the Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 vs. the Al c Ga 1-c The N-amorphous lattice layer 132 is closer to the template layer 12) such that the content of the Al component decreases layer by layer, thereby causing the lattice to have a gradual trend, such that the lattice mismatch and the thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 result inThe stress can be further gradually released.
In other embodiments, the Al is a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The N-amorphous lattice layers 132 may also be stacked from top to bottom, which also allows stress relief.
The deep ultraviolet light emitting diode further comprises a quantum well layer 15, a p-type semiconductor layer 16 and a p-type contact layer 17 which are sequentially positioned on the n-type semiconductor layer 14.
The quantum well layer 15, the p-type semiconductor layer 16, and the p-type contact layer 17 may also be formed in sequence by means of epitaxial growth.
The quantum well layer 15 is used as a deep ultraviolet light emitting layer and may include well layers and barrier layers that are alternately stacked periodically, and the number of periods may be selected according to the requirement of light emitting performance. The material of the quantum well layer 15 may be InAlGaN and/or AlGaN, and the contents of the In component and the Al component are selected according to the requirement of the light emitting performance.
The p-type semiconductor layer 16 is p-type Al y Ga 1-y And the N layer is used for providing holes.
The p-type Al y Ga 1-y The range of the Al component y in the N layer is more than or equal to 0.45 and less than or equal to 1.
The p-type contact layer 17 is p-type Al z Ga 1-z N layer of the p-type Al z Ga 1-z The range of the Al component z in the N layer is more than or equal to 0 and less than or equal to 0.4. When z is 0, only GaN is contained in the p-type contact layer 17.
The thickness of the p-type contact layer 17 may be 20nm to 400 nm.
The p-type Al y Ga 1-y N layer and the p-type Al z Ga 1-z The N layer is doped with magnesium.
Due to the p-type Al y Ga 1-y The resistance is increased if the hole concentration in the N layer is low and the N layer is directly in contact with a metal electrode (not shown) on the p-type contact layer 17, and therefore, the hole concentration can be increased and the resistance can be reduced by increasing the contact between the p-type contact layer 17 and the metal electrode.
As can be seen from the structure of the deep ultraviolet light emitting diode, the structure includes the stress control layer 13 located between the template layer 12 and the n-type semiconductor layer 14, and the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and Al c Ga 1-c One or both of the N non-superlattice layers 132, the Al a Ga 1-a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N-amorphous lattice layer 132 includes at least two layers of structures in which Al components are arranged in a gradient manner, so that lattice mismatch and thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be alleviated, stress can be gradually released, and surface cracks can be improved.
An embodiment of the present invention provides a method for manufacturing a deep ultraviolet light emitting diode, and referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a deep ultraviolet light emitting diode according to an embodiment of the present invention, where the method for manufacturing a deep ultraviolet light emitting diode includes:
step S1, providing a substrate;
step S2, sequentially forming a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the substrate, wherein the stress control layer is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c One or two of the N non-superlattice layers, the Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1- b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components in gradient arrangement.
The method for manufacturing the deep ultraviolet light emitting diode according to the present embodiment is described in more detail with reference to fig. 1.
According to step S1, a substrate 11 is provided.
The substrate 11 is made of at least one material selected from sapphire, silicon carbide, aluminum nitride, gallium oxide, and the like.
In step S2, a template layer 12, a stress control layer 13, an n-type semiconductor layer 14, a quantum well layer 15, and a p-type semiconductor layer 16 are sequentially formed on the substrate 11, wherein the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and Al c Ga 1-c One or two stacked structures of N non-superlattice layers 132, and Al a Ga 1-a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N-amorphous lattice layer 132 includes a stacked structure of at least two layers having a gradient arrangement of Al components.
The template layer 12 is an AlN layer for improving the growth quality of subsequently formed structures.
The n-type semiconductor layer 14 is n-type Al x Ga 1-x And the N layer is used for providing electrons.
The n-type Al x Ga 1-x The N layer is doped with silicon.
The n-type Al x Ga 1-x The range of the Al component x in the N layer is more than or equal to 0.4 and less than or equal to x<0.8。
The substrate 11 may be placed in an MOCVD reaction chamber, and the template layer 12, the stress control layer 13, and the n-type semiconductor layer 14 may be sequentially formed by epitaxial growth. The method comprises the following specific steps: firstly, introducing trimethylaluminum and ammonia gas into a reaction chamber, and growing the template layer 12 by taking hydrogen as a carrier gas; then, introducing trimethylgallium while maintaining the introduction of trimethylaluminum and ammonia gas to grow the stress control layer 13; then, taking silane as a doping agent, keeping introducing trimethyl gallium, trimethyl aluminum and ammonia gas to grow the n-type Al x Ga 1-x And N layers. Wherein each layer structure having different Al compositions in the stress control layer 13 and the n-type Al can be obtained by adjusting the flow rate of trimethylaluminum or trimethylgallium x Ga 1-x And N layers.
And, if the stress control layer 13 is the Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 of Al a Ga 1- a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b And N layers.
The Al is a Ga 1-a N layer and the Al b Ga 1-b The Al components a and b in the N layer are in the range of x<0.8<b<0.9<a<1, then, the Al a Ga 1-a The content of Al component in the N layer is larger than that of Al b Ga 1-b Content of Al component in N layer, the Al b Ga 1-b The content of Al component in the N layer is larger than that of the N-type Al x Ga 1-x Content of Al component in the N layer. Therefore, the Al in each cycle is preferable a Ga 1-a N layer is compared with the Al layer b Ga 1-b The N layer is closer to the template layer 12 such that the Al passes from the template layer 12 through a Ga 1-a N/Al b Ga 1-b The content of the Al component is gradually decreased from the N-superlattice layer 131 to the N-type semiconductor layer 14, so that the crystal lattice also has a gradual change trend, and thus the stress caused by the lattice mismatch and the thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be gradually released.
In other embodiments, Al may be present in each period b Ga 1-b N layer is more than the Al layer a Ga 1-a The N layer is closer to the template layer 12.
The Al is a Ga 1-a N layer and said Al b Ga 1-b The number of cycles of the N layers of the periodic alternating stack may be more than 1 and less than 50, and the Al is controlled a Ga 1-a N/Al b Ga 1-b The thickness of the N-superlattice layer 131 is less than 200nm, so that the stress release effect is optimal, the problem of excessive stress regulation caused by too large cycle number and too large thickness is avoided, and further the occurrence of more serious cracks caused by adverse effects is avoided.
OrIf the stress control layer 13 is Al c Ga 1-c N non-superlattice layer 132 of Al c Ga 1-c The N-amorphous layer 132 includes a stacked structure of at least two layers in which Al components are arranged in a gradient.
The Al is c Ga 1-c The Al component c of each layer structure in the N non-superlattice layer 132 is in the range of x<c is less than or equal to 0.8, then, the Al c Ga 1-c The content of Al component of each layer structure in the N non-superlattice layer 132 is larger than that of the N-type Al x Ga 1-x Content of Al component in the N layer.
Preferably the Al c Ga 1-c The Al composition of each layer structure in the N non-superlattice layer 132 decreases from bottom to top (i.e., the layer with the largest Al composition content is close to the template layer 12) so as to pass from the template layer 12 through the Al c Ga 1-c The content of Al component decreases from layer to layer from the structures of the N-type non-superlattice layer 132 to the N-type semiconductor layer 14, so that the crystal lattice also has a gradual trend, and thus the stress caused by the lattice mismatch and the thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be gradually released.
In other embodiments, the Al is c Ga 1-c The Al component of each layer structure in the N non-superlattice layer 132 may also be changed in an arbitrary ascending and descending manner from bottom to top, such as ascending layer by layer and then descending layer by layer, or descending layer by layer and then ascending layer by layer, or ascending layer by layer and descending layer by layer alternately.
The Al is c Ga 1-c The number of gradient layers N of the Al component in the N non-superlattice layer 132 is (c-x)/m, where m is a gradient of the Al component, and m may be 0 or more and 0.3 or less; n is>1。
X is more than or equal to 0.4<c is less than or equal to 0.8, and taking c as 0.75, x as 0.55 and m as 0.05 as examples, the gradient layer number n as 4 can be calculated according to the formula n as (c-x)/m, namely the Al c Ga 1-c The N non-superlattice layer 132 comprises 4 stacked structures with Al components arranged in a gradient manner, the gradient of the Al components between adjacent layers is 0.05, and the 4 stacked structures are sequentially made of Al from bottom to top 0.75 Ga 0.25 N layer, Al 0.7 Ga 0.3 N layer, Al 0.65 Ga 0.35 N layer and Al 0.6 Ga 0.4 N layer such that Al passes from the template layer 12 through c Ga 1-c Layers in the N-amorphous lattice layer 132 to the N-type semiconductor layer 14 (i.e., N-type Al 0.55 Ga 0.45 N layer), the content of the Al component decreases layer by layer.
The Al is c Ga 1-c The thickness of the N-type amorphous lattice layer 132 is greater than 100nm, so that the stress release effect is optimal, and the problem that the effective stress control effect cannot be realized due to too small thickness is avoided.
Or, if the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The stacked structure of N non-superlattice layers 132 is not less than 0.4 x<c≤ 0.8<b<0.9<a<1, then, the Al a Ga 1-a The content of Al component in the N layer is larger than that of Al b Ga 1-b Content of Al component in N layer, the Al b Ga 1-b The content of Al component in the N layer is larger than that of Al c Ga 1-c The content of Al component of each layer structure in the N non-superlattice layer 132, and the Al c Ga 1-c The content of Al component of each layer structure in the N non-superlattice layer 132 is greater than that of the N-type Al x Ga 1-x Content of Al component in N layer, therefore, it is preferable that Al is contained in each period a Ga 1-a N layer is more than the Al layer b Ga 1-b The N layer is closer to the template layer 12 and preferably the Al c Ga 1-c In the N non-superlattice layer 132, the Al component of each layer structure is preferably decreased from bottom to top layer by layer, and more preferably, the Al component is a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The N-amorphous lattice layers 132 are stacked from bottom to top (as shown in fig. 1, i.e., the Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 compares to the Al c Ga 1-c The N-amorphous lattice layer 132 is closer to the template layer 12) such that the content of the Al component decreases layer by layer, thereby causing the crystal lattice to have a gradual trend, thereby causing the template to be a thin filmThe stress caused by the lattice mismatch and the thermal mismatch between the layer 12 and the n-type semiconductor layer 14 can be further gradually released.
In other embodiments, the Al is a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and the Al c Ga 1-c The N-amorphous lattice layers 132 may also be stacked from top to bottom, which also allows stress relief.
The manufacturing method of the deep ultraviolet light emitting diode further comprises the following steps: a p-type contact layer 17 is formed on the p-type semiconductor layer 16.
The quantum well layer 15, the p-type semiconductor layer 16, and the p-type contact layer 17 may be formed in this order by epitaxial growth in an MOCVD reaction chamber. And when the p-type semiconductor layer 16 and the p-type contact layer 17 are grown, magnesium metallocene can be used as a dopant, so that the p-type semiconductor layer 16 and the p-type contact layer 17 are doped with magnesium.
The quantum well layer 15 is used as a deep ultraviolet light emitting layer and may include well layers and barrier layers that are alternately stacked periodically, and the number of periods may be selected according to the requirement of light emitting performance. The quantum well layer 15 may be made of InAlGaN and/or AlGaN, and the contents of the In component and the Al component are selected according to the requirement of the light emitting performance.
The p-type semiconductor layer 16 is p-type Al y Ga 1-y And the N layer is used for providing holes.
The p-type Al y Ga 1-y The range of the Al component y in the N layer is more than or equal to 0.45 and less than or equal to 1.
The p-type contact layer 17 is p-type Al z Ga 1-z N layer of p-type Al z Ga 1-z The range of the Al component z in the N layer is more than or equal to 0 and less than or equal to 0.4. When z is 0, only GaN is contained in the p-type contact layer 17.
The thickness of the p-type contact layer 17 may be 20nm to 400 nm.
Further, a metal electrode (not shown) may be formed on the p-type contact layer 17 by sputtering metal.
Due to the p-type Al y Ga 1-y The hole concentration in the N layer is low, and if the N layer is directly contacted with the metal electrode on the p-type contact layer 17, the resistance value is increased, so that the hole concentration can be increased and the resistance value can be reduced by increasing the contact between the p-type contact layer 17 and the metal electrode.
In the above method for manufacturing a deep ultraviolet light emitting diode, the stress control layer 13 is formed between the template layer 12 and the n-type semiconductor layer 14, and the stress control layer 13 is Al a Ga 1-a N/Al b Ga 1-b N superlattice layer 131 and Al c Ga 1-c One or both of the N non-superlattice layers 132, the Al a Ga 1-a N/Al b Ga 1-b The N-superlattice layer 131 includes Al alternately stacked periodically a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N-amorphous layer 132 includes at least two layers of Al components arranged in a gradient manner, so that lattice mismatch and thermal mismatch between the template layer 12 and the N-type semiconductor layer 14 can be alleviated, stress can be gradually released, and surface cracks can be improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (26)

1. The deep ultraviolet light-emitting diode is characterized by comprising a substrate, a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer from bottom to top, wherein the stress control layer is formed by stacking Al from bottom to top a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c N non-superlattice layer of said Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises Al components arranged in a gradient mannerA few two-layer structure, c is less than or equal to 0.8<b<0.9<a<1, the Al in each cycle a Ga 1-a N layer is compared with the Al layer b Ga 1-b The N layer is closer to the template layer, the Al c Ga 1-c And the Al components of each layer structure in the N non-superlattice layer are reduced from bottom to top layer by layer.
2. The deep ultraviolet light emitting diode of claim 1, wherein the template layer is an AlN layer.
3. The deep ultraviolet light emitting diode of claim 1, wherein the n-type semiconductor layer is n-type Al x Ga 1- x N layer, x is more than or equal to 0.4<0.8。
4. The deep ultraviolet light emitting diode of claim 1, wherein a number of cycles of the periodic alternating stack is greater than 1 and less than 50.
5. The deep ultraviolet light emitting diode of claim 1, wherein the Al is a Ga 1-a N/Al b Ga 1-b The thickness of the N superlattice layer is less than 200 nm.
6. The deep ultraviolet light emitting diode of claim 3, wherein x < c.
7. The deep ultraviolet light emitting diode of claim 6, wherein the Al is c Ga 1-c The gradient layer number N of the Al component in the N non-superlattice layer is (c-x)/m, wherein m is the gradient of the Al component, and N is>1。
8. The deep ultraviolet light emitting diode of claim 7, wherein 0. ltoreq. m.ltoreq.0.3.
9. The deep ultraviolet light emitting diode of claim 1, wherein the Al is c Ga 1-c Thickness of N non-superlattice layerThe degree is greater than 100 nm.
10. The deep ultraviolet light emitting diode of claim 1, wherein the p-type semiconductor layer is p-type Al y Ga 1-y And y is more than or equal to 0.45 and less than or equal to 1.
11. The deep ultraviolet light emitting diode according to any one of claims 1 to 10, further comprising a p-type contact layer on the p-type semiconductor layer.
12. The deep ultraviolet light emitting diode of claim 11, wherein the p-type contact layer is p-type Al z Ga 1- z And z is more than or equal to 0 and less than or equal to 0.4.
13. The deep ultraviolet light emitting diode of claim 11, wherein the p-type contact layer has a thickness of 20nm to 400 nm.
14. A method for manufacturing a deep ultraviolet Light Emitting Diode (LED), comprising:
providing a substrate; and the number of the first and second groups,
sequentially forming a template layer, a stress control layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the substrate, wherein the stress control layer is Al stacked from bottom to top a Ga 1-a N/Al b Ga 1-b N superlattice layer and Al c Ga 1-c N non-superlattice layer of said Al a Ga 1-a N/Al b Ga 1-b The N superlattice layer comprises Al which is periodically and alternately stacked a Ga 1-a N layer and Al b Ga 1-b N layer of said Al c Ga 1-c The N non-superlattice layer comprises at least two layers of structures with Al components arranged in a gradient manner, and c is less than or equal to 0.8<b<0.9<a<1, the Al in each cycle a Ga 1-a N layer is compared with the Al layer b Ga 1-b The N layer is closer to the template layer, the Al c Ga 1-c Al group of each layer structure in N non-superlattice layerThe components decrease from bottom to top layer by layer.
15. The method of claim 14, wherein the template layer is an AlN layer.
16. The method of claim 14, wherein the n-type semiconductor layer is n-type Al x Ga 1-x N layer, x is more than or equal to 0.4<0.8。
17. The method of claim 14, wherein the number of the periodic alternating stacks is greater than 1 and less than 50.
18. The method of claim 14, wherein the Al is present in the deep ultraviolet led a Ga 1-a N/Al b Ga 1-b The thickness of the N superlattice layer is less than 200 nm.
19. The method of claim 16, wherein x < c.
20. The method of claim 19, wherein the Al is present in the deep ultraviolet led c Ga 1-c The gradient layer number N of the Al component in the N non-superlattice layer is (c-x)/m, wherein m is the gradient of the Al component, and N is>1。
21. The method of claim 20, wherein m is 0. ltoreq. m.ltoreq.0.3.
22. The method of claim 14, wherein the Al is present in the deep ultraviolet led c Ga 1-c The thickness of the N non-superlattice layer is more than 100 nm.
23. The method of claim 14The manufacturing method of the deep ultraviolet light emitting diode is characterized in that the p-type semiconductor layer is p-type Al y Ga 1-y And y is more than or equal to 0.45 and less than or equal to 1.
24. The method according to any one of claims 14 to 23, wherein the method further comprises: and forming a p-type contact layer on the p-type semiconductor layer.
25. The method of claim 24, wherein the p-type contact layer is p-type Al z Ga 1-z And z is more than or equal to 0 and less than or equal to 0.4.
26. The method of claim 24, wherein the p-type contact layer has a thickness of 20nm to 400 nm.
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