CN113270321A - Manufacturing method of high-density shielded gate trench field effect transistor device - Google Patents
Manufacturing method of high-density shielded gate trench field effect transistor device Download PDFInfo
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
A manufacturing method of a high-density shielding grid groove type field effect transistor device belongs to the field of power semiconductor devices and is used for solving the problem that the existing manufacturing method of the field effect transistor cannot further reduce the size of a unit cell, and the method comprises the following steps: forming a first conductive type epitaxial layer and a trench on a substrate; forming a trench insulating layer and a shield gate electrode in the trench; forming an inter-electrode isolation layer on the upper surface of the shielding gate electrode; forming a gate oxide layer on the side wall of the groove; filling a gate electrode material and back-etching to form a gate electrode; forming a thermal oxide layer above the gate electrode, and forming a first dielectric layer on the surface of the semiconductor; performing electric ion implantation; forming a second dielectric layer, and forming a hard mask after back etching; etching the semiconductor to form a contact hole; forming a second heavily doped conductive type doped contact region; and forming upper surface metal to form a device. The manufacturing process flow of the high-density shielding grid groove type field effect transistor device is beneficial to further reducing the cell size of the device and reducing the effect of the on-resistance of the device.
Description
Technical Field
The invention belongs to the field of power semiconductor devices, and particularly relates to a manufacturing method of a high-density shielded gate trench type field effect transistor device.
Background
The related art background of the related art shielded gate trench field effect transistor will be described below. It is noted that corresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" described in this document are relative positions corresponding to the reference illustrations. The fixed direction is not limited in the specific implementation. It is noted that the devices in the drawings are not necessarily to scale. The straight lines shown by the boundaries of the doped regions and trenches in the drawings, and the sharp corners formed by the boundaries, are generally not straight lines and precise corners in practical applications.
The shielded gate groove type field effect transistor as a novel power device has the characteristics of low on-resistance and high switching speed. A cross-sectional structure of a conventional shielded gate trench fet structure such as CN107104149B is shown in fig. 1.
Wherein the device has a series of periodically arranged trenches (102) therein. An upper electrode and a lower electrode are filled in the active region trench, and the upper electrode and the lower electrode comprise an upper gate electrode (106) and a lower shielding gate electrode (104). The gate electrode (106) and the shield gate electrode (104) are isolated by an isolation dielectric layer (107). The gate electrode (106) is isolated from the corresponding side wall of the groove through a gate oxide layer (103). The shield gate electrode (104) is isolated from the corresponding trench sidewall by a trench insulating layer (115).
In addition, the device structure also comprises a lower surface metal (112) positioned at the bottom, and N positioned above the lower surface metal (112)+A patterned underlayer (100) on N+An N-type epitaxial layer (101) over the type substrate layer (100), and a P-body doped region (108) on the semiconductor upper surface, N+A source doped region (109), andthe P + contacts the doped region (110).
In order to further reduce the on-resistance of the shielded gate trench field effect transistor, it is necessary to reduce the cell size of the device and increase the cell density of the device. However, in the conventional manufacturing process of the shielded gate trench type field effect transistor, the reduction of the cell size is limited by the photolithography process.
In the conventional shielded gate trench fet shown in fig. 1, the trench (102) and the source contact hole (120) are formed by two photolithography processes, one after the other. However, there is an alignment deviation between the two lithographies, limited by the accuracy limitations of the lithographic process. The deviation may cause the distance between the trench (102) and the source contact hole (120) to be too close. When the trenches (102) and the source contact holes (120) are too close to each other, the P + contact doping region (110) formed below the source contact holes affects the concentration of the channel region near the corresponding trench, and thus the on-resistance and switching threshold of the device. Therefore, in conventional structures, it is often necessary to leave a suitable safety distance between the trench (102) and the source contact hole (120) in view of lithographic alignment deviations. This safe distance limits further reduction in cell size.
Disclosure of Invention
In view of the above-mentioned problems of the prior art shielded gate trench fet device, there is a need to provide a method for manufacturing a high-density shielded gate trench fet device.
The invention adopts the following technical scheme:
a method of fabricating a high density shielded gate trench field effect device, the method comprising the steps of:
the method comprises the steps of firstly, providing a first heavily doped conductive substrate, and forming a first conductive epitaxial layer on the first heavily doped conductive substrate;
secondly, forming a groove on the first conductive epitaxial layer;
thirdly, forming a groove insulating layer in the groove and forming a shielding gate electrode in the groove;
fourthly, removing part of the groove insulating layer on the side wall of the groove and forming an inter-electrode isolating layer on the upper surface of the shielding gate electrode;
fifthly, forming a gate oxide layer on the side wall of the groove;
sixthly, filling gate electrode materials and back etching to form a gate electrode;
seventhly, performing thermal oxidation to form a thermal oxide layer above the gate electrode;
eighthly, etching the thermal oxidation layer on the surface of the semiconductor, and forming a first dielectric layer on the surface of the semiconductor;
ninth, performing ion implantation of the second conductive type and the first heavily doped conductive type to form a second conductive type doped region and a first heavily doped conductive type doped source region;
tenth, forming a second dielectric layer on the first dielectric layer, etching the second dielectric layer and the first dielectric layer back to the upper surface of the semiconductor and exposing the semiconductor, and forming a hard mask on the etched second dielectric layer and the first dielectric layer;
eleventh, etching the semiconductor by using the hard mask to form a contact hole;
a twelfth step of performing a second heavy doped conductive type ion implantation in the second conductive type doped body region to form a second heavy doped conductive type doped contact region;
and a tenth step of forming upper surface metal to form the device.
Optionally, in the fourth step, the method for forming the inter-electrode isolation layer includes the following steps: firstly, removing the upper half part of the groove insulating layer on the side wall of the groove by wet etching, depositing oxide in the groove, then carrying out a chemical mechanical planarization process to grind the oxide to the upper surface of the groove, and finally carrying out wet etching on the oxide to form an inter-electrode isolating layer.
Optionally, the trench insulating layer is a combination of a nitride layer and an oxide layer, and in the fourth step, the method for forming the inter-electrode isolation layer includes the following steps: firstly, removing the oxide layer in the upper half part of the trench insulating layer on the side wall of the trench by wet etching, leaving the nitride layer as a thermal oxidation protective layer, then carrying out thermal oxidation on the shielding gate electrode to form an inter-electrode isolation layer, and finally removing the thermal oxidation protective layer on the side wall of the trench.
Optionally, in the eighth step, the first dielectric layer is composed of an oxide, and the forming method is: the method comprises the steps of firstly, completely removing a thermal oxidation layer on the upper surface of a semiconductor by using wet etching, and then forming a first dielectric layer on the surface of the semiconductor by using thermal oxidation.
Optionally, in the eighth step, the first dielectric layer is composed of an oxide, and the forming method is: and removing part of the thermal oxidation layer on the upper surface of the semiconductor by using wet etching, wherein the oxide left after etching is used as a first dielectric layer.
Optionally: in the tenth step, the first dielectric layer includes an oxide, and the second dielectric layer includes: one or more of oxide, nitride, organic polymer, borophosphosilicate glass, spin-coated glass and benzocyclobutene.
Optionally: and in the tenth step, after the second medium layer is formed, carrying out chemical mechanical planarization process grinding and staying on the nitride layer in the second medium layer, and then respectively etching the exposed nitride layer and the first medium layer below the nitride layer until the semiconductor material is exposed.
Optionally, in the twelfth step, an implantation protection layer is formed on the sidewall of the contact hole in advance before the second heavily doped conductive type ion implantation is performed.
Optionally, in the twelfth step, before the ion implantation, the semiconductor is dry etched in the vertical direction in one step, so that the depth of the contact hole is further increased.
Optionally, in the twelfth step, the implantation protection layer is partially or completely removed after the second heavy doping conductive type ion implantation.
The manufacturing process of the high-density shielding grid groove type field effect transistor disclosed by the invention has the beneficial effects that the distance between the groove 102 and the source contact hole 120 in the traditional device process is prevented from being limited by photoetching, the influence of a P + contact region on a channel is reduced, the cell size of the device is further reduced, and the on-resistance of the device is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional shielded gate trench field effect device;
FIG. 2 is a schematic cross-sectional view of a third step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 3 is a schematic cross-sectional view of a fourth step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 4 is a schematic cross-sectional view of a fifth step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 5 is a schematic cross-sectional view of a sixth step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 6 is a schematic cross-sectional view of a seventh step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 7 is a schematic cross-sectional view of an eighth step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
FIG. 8 is a schematic cross-sectional view of a ninth step in the process of manufacturing a shielded gate trench FET in accordance with the present invention;
fig. 9 is a cross-sectional view of a tenth step in the process of manufacturing the shielded gate trench fet according to the present invention;
fig. 10 is a schematic cross-sectional view of a tenth step in the process of manufacturing a shielded gate trench fet according to the present invention;
fig. 11A is a schematic cross-sectional view of a twelfth step of the shielded gate trench fet according to the present invention;
11B and 11C are schematic cross-sectional views illustrating a method for implementing the twelfth step in an embodiment of the shielded gate trench FET according to the present invention;
fig. 12 is a cross-sectional view of a shielded gate trench fet according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail below with reference to the accompanying drawings and examples. It is to be noted that in the following description of the shielded gate trench field effect device and the method of manufacturing the same of the present invention, the semiconductor substrate of the shielded gate trench field effect device is considered to be composed of a silicon (Si) material. However, the substrate may be formed of any other suitable screenThe material for manufacturing the shielded gate trench field effect transistor is gallium nitride (GaN), silicon carbide (SiC), or the like. In the following description, the conductivity types of a semiconductor region are divided into a second conductivity type (P-type) and a first conductivity type (N-type), and a semiconductor region of the second conductivity type may be formed by doping an original semiconductor region with one or more impurities, which may be, but are not limited to: boron (B), aluminum (Al), gallium (Ga), and the like. A semiconductor region of a first conductivity type conductivity may also be formed by doping the original semiconductor region with one or more impurities which may be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H +), and the like. In the following description, the semiconductor region of the second heavily doped conductivity type is labeled as a P + region and the semiconductor region of the first heavily doped conductivity type is labeled as an N + region. For example, in a silicon material substrate, the impurity concentration of a heavily doped region is typically 1 × 10, unless otherwise specified19 cm-3To 1X 1021 cm-3. It will be understood by those skilled in the art that the second conductivity type (P-type) and the first conductivity type (N-type) are interchangeable, and the second heavily doped conductivity type (P-type)+Type) and first heavily doped conductivity type (N)+Type) may be interchanged. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
A method of fabricating a high density shielded gate trench field effect device, the method comprising the steps of:
in a first step, a first heavily doped conductive substrate 200 is provided and a first conductive epitaxial layer 201 is formed thereon. Wherein, the first heavily doped conductive substrate may be doped with red phosphorus or arsenic; the first conductive type epitaxial layer may be doped with phosphorus and has a thickness of 0.5 to 10 μm. The doping concentration of the first conductivity type epitaxial layer 201 may be constant or may have different doping concentrations depending on the depth. In one embodiment, the epitaxial layer 201 of the first conductivity type is doped with phosphorus at a doping concentration of 5e17 cm-3~1e16 cm-3The thickness is 1 to 10 μm. In another embodiment, the doping concentration is in the secondThe depth of the epitaxial layer 201 is increased, wherein the doping concentration is 5e17 cm at the lightest part-3~1e16 cm-3The most concentrated position is 5e17 cm-3~1e18 cm-3。
In the second step, trenches 250 are formed on the first conductive type epitaxial layer 201. Before the formation of the trench, a hard mask may need to be formed on the upper surface of the epitaxial layer in advance by photolithography. The hard mask may include: a semiconductor oxide or nitride, or a combination of both. In one embodiment, the hard mask is an insulator combination, and comprises, from bottom to top: silicon oxide (100-1000A), silicon nitride (1000-3000A), and silicon oxide (2000-3000A). In another embodiment, the hard mask is silicon oxide (1500-4000A), which may be removed after trench etching, or may remain partially or completely on the top surface of the epitaxial layer after trench etching. The trench formation method may include, but is not limited to, dry etching. In one embodiment, the trench may be formed by thermal ion etching. The etched trench may have a shape with a large top and a small bottom. In one embodiment, the width of the upper surface of the trench is 0.2-0.5 um and the depth is 1.2-3 μm. In another embodiment, the width of the upper surface of the trench is 0.5-1.5 um and the depth is 3-6 μm.
Third, a trench insulating layer 202 is formed in the trench, and a shield gate electrode 203 is formed in the trench, as shown in fig. 2.
The trench insulating layer 202 may be an oxide layer, and may also include: a combination of an oxide layer and a nitride layer. In one embodiment, the trench insulating layer 202 is an oxide layer formed by thermal oxidation or deposition; in another specific embodiment, the trench insulating layer 202 is a combination of a nitride layer and an oxide layer, wherein the nitride layer and the oxide layer are formed sequentially by deposition, respectively.
Fourth, a portion of the trench insulating layer 202 on the trench sidewalls is removed and an inter-electrode isolation layer 204 is formed on the upper surface of the shield gate electrode 203, as shown in fig. 3.
The inter-electrode isolation layer 204 is typically an oxide.
The method of forming the inter-electrode isolation layer 204 may include: the oxide is etched back after deposition. The back etching method comprises the following steps: wet or dry etching, or chemical mechanical planarization.
In one embodiment, the method of forming the inter-electrode isolation layer 204 includes the steps of: the method comprises the steps of firstly removing the upper half part of the trench insulating layer 202 on the side wall of the trench by wet etching, depositing oxide in the trench, then carrying out a chemical mechanical planarization process to grind the oxide to the upper surface of the trench, and finally carrying out wet etching on the oxide to form the inter-electrode isolation layer 204.
In addition, the inter-electrode isolation layer 204 may be formed by thermal oxidation.
In one embodiment, the method of forming the inter-electrode isolation layer 204 includes the steps of: at first, wet etching is used to remove the upper half part of the trench insulating layer 202 on the trench sidewall, and then thermal oxidation is performed to form the inter-electrode isolation layer 204 and the gate oxide layer 210.
In another embodiment, the trench insulating layer 202 is a combination of a nitride layer and an oxide layer. The process comprises the following steps: first, wet etching is used to remove the oxide layer in the upper half of the trench insulating layer 202 on the trench sidewall, and the nitride layer is left as the thermal oxidation protection layer. And then carrying out thermal oxidation on the shield gate electrode 203 to form an inter-electrode isolation layer 204, and finally removing the thermal oxidation protection layer on the side wall of the trench.
In a fifth step, a gate oxide layer 210 is formed on the trench sidewalls, as shown in fig. 4.
The thickness of the gate oxide layer 210 is 200-1000A. The method of forming the gate oxide layer 210 may include: thermal oxidation is either deposition or a combination of both.
In addition, the inter-electrode isolation layer 204 and the gate oxide layer 210 may be simultaneously formed by a thermal oxidation method. In one embodiment, the method of forming the gate oxide layer 210 is wet thermal oxidation at 900-1300 ℃.
Sixth, the gate electrode material is filled and etched back to form a gate electrode 205, as shown in fig. 5. Wherein the gate electrode material is typically polysilicon. The method of back-etching the gate electrode material may include chemical mechanical planarization and/or dry etching. The distance from the upper surface of the gate electrode 205 after the etching back to the upper surface of the semiconductor is 0.3 to 1 μm.
In the seventh step, thermal oxidation is performed to form a thermal oxide layer 206 over the gate electrode 205, as shown in fig. 6. Wherein the thickness of the thermal oxide layer 206 is 500-5000A. In one embodiment, the thermal oxide layer is formed by wet thermal oxidation at a temperature of 1000 to 1200 ℃ for 30 to 200 minutes.
Step eight, the thermal oxide layer 206 on the semiconductor surface is etched, and a first dielectric layer 301 is formed on the semiconductor surface, as shown in fig. 7.
The method for etching the thermal oxide layer 206 may include: wet or dry etching. The first dielectric layer 301 may include: an oxide or nitride, possibly in combination with an oxide layer and a nitride layer. The method of forming the first dielectric layer 301 may include: thermal oxidation is either deposition or a combination of both.
In one embodiment, the first dielectric layer 301 is comprised of an oxide. The thermal oxide layer 206 on the semiconductor upper surface is completely removed by wet etching, and then the first dielectric layer 301 is formed on the semiconductor surface by thermal oxidation.
In another embodiment, the first dielectric layer 301 is comprised of an oxide. And removing part of the thermal oxide layer 206 on the upper surface of the semiconductor by using wet etching, wherein the oxide of 50-800A left after etching is used as the first dielectric layer 301.
In the ninth step, ion implantation of the second conductive type and the first heavily doped conductive type is performed to form a second conductive type doped region 216 and a first heavily doped conductive type doped source region 215, as shown in fig. 8.
The second conductive type doped region 216 and the first heavily doped conductive type doped source region 215 may be formed by multiple times of ion implantations of the second conductive type and the first heavily doped conductive type. Wherein, each time the energy of the second conductive type ion implantation is 10 keV-200 keV, the dopant may comprise boron, gallium, , etc., and the dosage is 1e12~5e14 cm-3. After the second conductive type ion implantation, a further thermal diffusion process may be performed. In one embodiment, the thermal diffusion temperature is 900-1150 ℃ for 10-300 minutes. The energy of each ion implantation of the first heavily doped conductive type is 5keV to 200keV, the dopant may include arsenic, , phosphorus, etc., and the dosage is 1e13 to 5e16 cm-3。
Tenth, a second dielectric layer 302 is formed on the first dielectric layer 301, the second dielectric layer 302 and the first dielectric layer 301 are etched back to the upper surface of the semiconductor to expose the semiconductor, and a hard mask is formed on the etched back second dielectric layer 302 and the first dielectric layer 301, as shown in fig. 9.
The second dielectric layer 302 may be a combination layer formed by one or more of insulating substances such as oxide, nitride, organic polymer, boro-phospho-silicate glass (BPSG), spin-on glass (SOG), benzocyclobutene (BCB), and the like.
The method for etching back the second dielectric layer 302 and the first dielectric layer 301 may comprise: wet or dry etching, or chemical mechanical planarization.
In one embodiment: the first dielectric layer 301 and the second dielectric layer 302 are both oxide. First, a second dielectric layer 302 is formed by deposition. A chemical mechanical planarization process or/and a wet etching process are then performed until the semiconductor upper surface is exposed, forming a hard mask.
In another embodiment: the second dielectric layer 302 comprises a nitride layer, which may be 50-1000A thick, formed by deposition. After the second dielectric layer 302 is formed, a chemical mechanical planarization process is performed to polish and stop on the nitride layer in the second dielectric layer 302. The exposed nitride layer and the underlying first dielectric layer 301 are then etched separately to expose the semiconductor material.
In the eleventh step, the semiconductor is etched using the hard mask to form a contact hole 207 as shown in fig. 10.
The contact hole 207 may have a shape with a large width. Wherein the width of the narrowest part is 0.05-0.5 μm. The contact hole 207 has a depth of 0.2 to 1um and contacts the second conductive type doped region 216 and the first heavily doped conductive type doped source region 215.
Since the contact hole 207 is formed without a photolithography step and the distance between the contact hole 207 and the trench is not limited by the photolithography precision, the above method for forming the contact hole 207 is advantageous to reduce the cell size.
In a twelfth step, a second heavily doped conductive type doped contact region 217 is formed in the second conductive type doped body region 216, as shown in fig. 11A.
The second heavily doped conductive contact region 217 may be formed by one or more times of ion implantation of the second heavily doped conductive type. Wherein, each time the energy of the second heavily doped conductive ion implantation is 10 keV-150 keV, the doped substance may contain boron, gallium, , etc., and the dosage is 1e 13-5 e16 cm-3。
Before the second heavy doping conductive type ion implantation, an implantation protection layer 303 may be formed on the sidewall of the contact hole 207 to reduce the ion implantation dosage in the horizontal direction at the sidewall. The method comprises the following steps:
first, a third dielectric layer 304 is formed on the upper surface of the device, as shown in fig. 11B. The third dielectric layer 304 may be formed of nitride, oxide, or other material capable of blocking the implantation of ions of the second heavily doped conductive type, and has a thickness of 200A-1000A. In one embodiment, the third dielectric layer 304 is nitride and is formed by deposition to a thickness of 200A to 600A.
Then, the third dielectric layer 304 is etched in the vertical direction to expose the semiconductor at the bottom of the contact hole 207, and an implantation protection layer 303 is formed on the sidewall of the contact hole 207, as shown in fig. 11C.
The implantation protection layer 303 can reduce the implantation dose in the horizontal direction when the second heavily doped conductive type ions are implanted, and reduce the diffusion of the second heavily doped conductive type ion impurities in the horizontal direction, so that the second heavily doped conductive type doped contact region is far away from the side wall of the trench, thereby avoiding the influence on the channel. The method is beneficial to reducing the distance from the groove to the contact hole and further reducing the cell size of the device.
Further, after the formation of the implantation protective layer 303 and before the ion implantation, the semiconductor may be further dry-etched in the vertical direction, so that the depth of the contact hole 207 may be further increased.
The implantation protection layer 303 is partially or completely removed after the second heavy doping conductive type ion implantation.
In a tenth step, a top metal 209 is formed to form the device, as shown in fig. 12.
The semiconductor top metal 209 is typically Al or an Al compound, such as Al/Cu, Al/Si/Cu, etc., and has a thickness of 3 to 5 μm.
It is possible to fill the contact hole 207 with a diffusion barrier metal first before the top metal 209 is formed. The diffusion barrier metal may be composed of: metals such as Ti, W, etc., or metal compounds thereof such as TiSi, TiN, etc.
The manufacturing process flow of the shielded gate trench type field effect transistor disclosed by the invention avoids the limitation of the photoetching precision on the distance between the trench and the source contact hole in the traditional device process flow, reduces the influence of a P + contact region on the trench, and is beneficial to further reducing the cell size of the device and reducing the effect of the on-resistance of the device. It should be noted that the above embodiments are not intended to limit the scope of the present invention, and the present invention can be implemented in a wider scope than the above embodiments.
Claims (10)
1. A method of fabricating a high density shielded gate trench field effect device, the method comprising the steps of:
a first step of providing a first heavily doped conductive substrate (200) and forming a first conductive epitaxial layer (201) thereon;
a second step of forming a trench (250) on the first conductivity type epitaxial layer (201);
thirdly, forming a trench insulating layer (202) in the trench, and forming a shield gate electrode (203) in the trench;
fourthly, removing part of the groove insulating layer (202) on the side wall of the groove and forming an inter-electrode isolation layer (204) on the upper surface of the shielding gate electrode (203);
fifthly, forming a gate oxide layer (210) on the side wall of the groove;
sixthly, filling the gate electrode material and etching back to form a gate electrode (205);
a seventh step of performing thermal oxidation to form a thermal oxide layer (206) above the gate electrode (205);
eighthly, etching the thermal oxidation layer (206) on the surface of the semiconductor, and forming a first dielectric layer (301) on the surface of the semiconductor;
ninth, performing ion implantation of the second conductive type and the first heavily doped conductive type to form a second conductive type doped region (216) and a first heavily doped conductive type doped source region (215);
tenth, forming a second dielectric layer (302) on the first dielectric layer (301), etching back the second dielectric layer (302) and the first dielectric layer (301) to the upper surface of the semiconductor and exposing the semiconductor, and forming a hard mask on the etched back second dielectric layer (302) and the first dielectric layer (301);
eleventh, etching the semiconductor using the hard mask to form a contact hole (207);
a twelfth step of performing a second heavy doped conductive type ion implantation in the second conductive type doped body region (216) to form a second heavy doped conductive type doped contact region (217);
in a tenth step, a top surface metal (209) is formed to form the device.
2. The method of manufacturing a high-density shielded gate trench field effect transistor according to claim 1, wherein in the fourth step, the inter-electrode isolation layer (204) is formed by a method comprising the steps of: firstly, removing the upper half part of the trench insulating layer (202) on the side wall of the trench by wet etching, depositing oxide in the trench, then carrying out a chemical mechanical planarization process to grind the oxide to the upper surface of the trench, and finally carrying out wet etching on the oxide to form an inter-electrode isolation layer (204).
3. The method of manufacturing a high-density shielded gate trench field effect transistor according to claim 1, wherein the trench insulation layer (202) is a combination of a nitride layer and an oxide layer, and the step of forming the inter-electrode isolation layer (204) in the fourth step comprises the steps of: firstly, an oxide layer in the upper half part of a trench insulating layer (202) on the side wall of a trench is removed by wet etching, a nitride layer is left to be used as a thermal oxidation protective layer, then thermal oxidation is carried out on a shielding gate electrode (203) to form an inter-electrode isolation layer (204), and finally the thermal oxidation protective layer on the side wall of the trench is removed.
4. The method for manufacturing a high-density shielded gate trench field effect transistor according to claim 1, wherein in the eighth step, the first dielectric layer (301) is made of oxide and formed by: the thermal oxide layer (206) on the upper surface of the semiconductor is completely removed by wet etching, and then a first dielectric layer (301) is formed on the surface of the semiconductor by thermal oxidation.
5. The method for manufacturing a high-density shielded gate trench field effect transistor according to claim 1, wherein in the eighth step, the first dielectric layer (301) is made of oxide and formed by: a wet etch is used to remove a portion of the thermal oxide layer (206) from the top surface of the semiconductor, and the oxide remaining after the etch serves as the first dielectric layer (301).
6. The method of manufacturing a high density shielded gate trench field effect device as defined in claim 1, wherein: in the tenth step, the first dielectric layer (301) comprises an oxide, and the second dielectric layer (302) comprises: oxide, nitride, organic polymer, Boron Phosphorus Silicon Glass (BPSG), spin coating glass (SOG), benzocyclobutene (BCB).
7. The method of manufacturing a high density shielded gate trench field effect device as defined in claim 6, wherein: and in the tenth step, after the second dielectric layer (302) is formed, carrying out chemical mechanical planarization process grinding and staying on the nitride layer in the second dielectric layer (302), and then respectively etching the exposed nitride layer and the first dielectric layer (301) below the exposed nitride layer until the semiconductor material is exposed.
8. The method of manufacturing a high-density shielded gate trench field effect transistor according to claim 1, wherein in the twelfth step, an implantation protection layer (303) is formed on the sidewall of the contact hole (207) in advance before the second heavily doped conductive type ion implantation is performed.
9. The method of claim 8, wherein in the twelfth step, the contact hole (207) is further increased in depth by performing a vertical dry etching of the semiconductor before the ion implantation.
10. The method of claim 8, wherein in the twelfth step, the implantation protection layer (303) is partially or completely removed after the second heavily doped conductive type ion implantation.
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Application publication date: 20210817 |