CN113192550B - Method for determining optimal reading voltage of memory - Google Patents
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- CN113192550B CN113192550B CN202110459178.2A CN202110459178A CN113192550B CN 113192550 B CN113192550 B CN 113192550B CN 202110459178 A CN202110459178 A CN 202110459178A CN 113192550 B CN113192550 B CN 113192550B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method for determining the optimal read voltage of a memory, which comprises the steps of firstly setting an optimal read voltage point as an intersection point of adjacent threshold voltage states of the memory, wherein a default read voltage point is a read voltage point set when the memory leaves a factory; and calculating offset distances offset1 and offset2 of two adjacent threshold voltage states relative to the initial state, wherein the offset distance offset= (offset 1+offset 2)/2 of the optimal read voltage point relative to the default read voltage point is calculated, and determining the optimal read voltage point according to the offset distance and the default read voltage point. The invention determines the position of the optimal reading voltage through fewer reading times, thereby greatly reducing the reading error of the memory and improving the efficiency and the reliability of the memory system.
Description
Technical Field
The invention relates to the field of memory system controllers, in particular to a method for determining the optimal read voltage of a memory.
Background
During the last decade, the nonvolatile memory market has exhibited explosive growth. NAND flash memory has been the mainstream storage medium in the current nonvolatile memory field by virtue of its advantages such as good shock resistance, high integration density, low market price, and excellent reliability.
The main manifestations of NAND flash memory in the consumer market are: (1) SSDs (solid state drives) for enterprise data centers, servers, and personal computers; (2) UFS flash memory for mobile terminals such as tablet computers, cell phones, smart watches. For both SSD and UFS flash memories, they are mainly composed of two parts: firstly, storing particles, and providing the most basic storage function; and secondly, the control chip is mainly used for controlling, managing and optimizing the storage particles in the life cycle of the storage particles.
System efficiency and system reliability are two important criteria for NAND flash memory performance. The system efficiency comprises the transmission speed (interface mode and protocol) between the controller and the storage particles, the complexity of each module algorithm of the control chip and the like; the system reliability is based on the error mode and the characteristics of storage particles, the reliability problem encountered in the use process is solved and optimized in a targeted manner, and finally, the correction of bit errors is realized through Error Correction Codes (ECC), so that the reliable access of data is ensured.
The main physical structure of the NAND flash memory cell is a MOS field effect transistor, as shown in fig. 1. The charges 4 enter the storage layer 5 under the action of an external electric field, the upper part and the lower part of the storage layer 5 are respectively provided with the oxidation insulating layer 2, and the charges are blocked from diffusing to other positions after the device is powered off, so that the aim of nonvolatile storage is fulfilled. In a read operation of the flash memory, it is determined whether a read bit is '0' or '1' by applying a read voltage of a certain magnitude. The amount of charge in the memory layer 5 determines the threshold voltage (Vth, threshold Voltage) of the memory cell, a range of threshold voltages representing a threshold voltage state; if the threshold voltage is greater than the read voltage, reading out '0'; conversely, read out '1'.
Due to the special structure and material of NAND flash memory cells, the charges stored therein may be lost and spread with the increase of the retention time, resulting in lower threshold voltages. There is one such phenomenon: a part of memory cell threshold voltages are higher than the read voltage in the initial state, and the read data is '0'; but the charge loss caused by the time is lower than the read voltage in the next read operation, and the read data is '1', so that the read error occurs. FIG. 2 is a schematic diagram showing a read error, which we refer to the read voltage in the initial state as the default read voltage, and black shading in the diagram is the error bit region. If the default read voltage is not adjusted, more and more read errors can be caused, and the error correction capability of the error correction code of the control chip is exceeded, so that data damage is caused. When the data error under the default read voltage exceeds the error correction limit of the error correction code of the controller, the read voltage is subjected to offset adjustment, and the voltage point with the least error is found to be the optimal read voltage point.
Disclosure of Invention
The invention aims to solve the technical problem of providing a method for determining the optimal read voltage of a memory, which determines the position of the optimal read voltage through fewer read times, thereby greatly reducing the read error of the memory and improving the efficiency and the reliability of a memory system.
In order to solve the technical problems, the technical scheme of the invention is as follows: a method for determining an optimal read voltage of a memory, comprising the steps of:
s01), setting an optimal read voltage point as a cross point of adjacent threshold voltage states of the memory, wherein a default read voltage point is a read voltage point set when the memory leaves a factory;
s02), calculating the drift distances offset1, offset2 of two adjacent threshold voltage states relative to the initial state, and calculating the drift distance of a certain threshold voltage state relative to the initial state thereof according to the formula:
，
wherein offset is n RV is the drift distance of the threshold voltage state relative to its initial state default A default read voltage point, μ for the threshold voltage state initial Is the initial average of the threshold voltage distribution; sigma is the variance after the threshold voltage is deviated, and C is the deviation quantity; RV when the offset is calculated by the formula (1) default 、μ initial Sigma, C are known amounts;
s03), offset distance offset= (offset 1+ offset 2)/2 of the optimal read voltage point relative to the default read voltage point, and determining the optimal read voltage point according to the offset distance and the default read voltage point.
Further, C is the number of deviations corresponding to a left bias error or a right bias error, where the left bias error refers to that the corresponding threshold voltage is higher than the read voltage when writing data, but the threshold voltage is lower than the read voltage when reading data, and the right bias error refers to that the corresponding threshold voltage is lower than the read voltage when writing data, but the threshold voltage is higher than the read voltage when reading data.
Further, the difference between the written threshold voltage state number and the read threshold voltage state number is calculated again by recording the written threshold voltage state number and the read threshold voltage state number, so that C is obtained.
Further, the number of read threshold voltage states is obtained by one default read voltage reading.
Further, for a multi-value memory, the deviation amount is determined in a manner from the upper bit to the lower bit, for the threshold voltage state of the highest bit, the deviation amount is equal to the difference value between the threshold voltage state amount read out by the default read voltage and the written threshold voltage state amount, and for the threshold voltage state of the not highest bit, the deviation amount c=c1-C2, C1 is the deviation amount of the threshold voltage state of the last bit, and C2 is the difference value between the threshold voltage state amount read out by the default read voltage corresponding to the present threshold voltage state and the written threshold voltage state amount.
Further, the initial average value of the threshold voltage distribution is at a half position of the width of the threshold voltage distribution in the shipping state of the NAND flash memory particle or at an intermediate position before the adjacent default read voltage.
Further, the method for obtaining the variance after the threshold voltage is shifted is as follows: the threshold voltage distributions in different cases are extracted by gaussian fitting.
Further, the different conditions include wear level, data retention time, and read-write interference level.
Further, the method is applicable to SLC, MLC, TLC, QLC flash memory particles.
The invention has the beneficial effects that: according to the error rule of NAND flash memory storage particles in a data retention scene, the invention provides an optimal read voltage determination method by combining the change condition of threshold voltage and a Gaussian mathematical model. The method can estimate the position of the optimal read voltage by only applying the default read voltage once, and the estimated optimal read voltage point has smaller deviation from the ideal optimal read voltage point, thereby greatly reducing read errors, enhancing the reliability of the flash memory storage system and simultaneously considering the system efficiency.
Drawings
FIG. 1 is a schematic diagram of the physical structure of a NAND flash memory cell:
FIG. 2 is a schematic diagram of a NAND flash memory with read errors at a default read voltage due to threshold voltage drift;
FIG. 3 is a diagram showing the position of the ideal optimal read voltage point, and the left bias error and right bias error at the ideal optimal read voltage;
FIG. 4 is a schematic diagram of eight threshold voltage states corresponding to TLC NAND flash memory data and seven read voltage positions issued during a read operation;
FIG. 5 is a schematic diagram of the calculation of the optimal read voltage point;
FIG. 6 is a schematic diagram of estimating the threshold voltage drift distance;
FIG. 7 is a graph showing the ratio of right bias errors to total errors at different data retention times when P/E cycling=10 and P/E cycling=2000;
FIG. 8 is a graph of variance data of threshold voltage distribution of actual NAND flash memory particles at different data retention times measured at P/E cycling=10;
FIG. 9 is a graph of variance data of threshold voltage distribution of actual NAND flash memory particles at different data retention times measured at P/E cycling=2000;
fig. 10 is a CDF plot of estimated optimum read voltage versus ideal optimum read voltage offset distance for P/E cycling=10;
FIG. 11 is a CDF chart of estimating the offset distance between the optimal read voltage and the ideal optimal read voltage when P/E cycling=2000;
FIG. 12 is a flow chart for estimating an optimal read voltage;
in the figure: 1. control deletion, 2, an oxidation insulating layer, 3, a polysilicon channel, 4, charges, 5 and a storage layer.
Detailed Description
The invention will be further described with reference to the drawings and the specific examples.
Example 1
The threshold voltage distribution of the NAND flash memory approximately accords with a mathematical Gaussian function model, and according to the mathematical relation, the ideal optimal reading voltage point is the intersection point of adjacent threshold voltage states, as shown in FIG. 3. Here, we refer to the part of bit errors written with data of '0' but read with data of '1' as left offset errors; bit errors written as '1' but read as '0' are referred to as right bias errors.
According to the error rule of NAND flash memory storage particles in a data retention scene, the method for determining the optimal reading voltage of the memory is provided by combining the change condition of threshold voltage and Gaussian mathematical model. The method can estimate the position of the optimal read voltage by only applying the default read voltage once, and the estimated optimal read voltage point has smaller deviation from the ideal optimal read voltage point, thereby greatly reducing read errors, enhancing the reliability of the flash memory storage system and simultaneously considering the system efficiency.
The NAND flash memory particles in the present stage all have multi-value memory technology, and can be classified into SLC (1 bit/cell), MLC (2 bit/cell), TLC (3 bit/cell) and QLC (4 bit/cell) according to the number of memory cell bits. For the NAND flash memory particles with multi-value storage, the read operation needs to send out a plurality of read voltages, and each read voltage corresponds to an optimal read voltage point, so that the plurality of read voltages need to be determined. Here we take TLC flash particles as the experimental object, and fig. 4 shows the threshold voltage distribution of TLC flash particles, and it can be seen that TLC contains eight threshold voltage states (Er, a, … …, G), and that seven optimal read voltage points v0 to v6 need to be determined. Because the threshold voltage distribution interval between the Er state and the A state is very wide, the optimal read voltage of v0 is not needed to be determined generally, the experimental case of the invention does not comprise the research on v0, but the determination of the optimal read voltage of v0 is also within the protection scope of the invention.
FIG. 5 is a schematic diagram of the basic principle of determining the optimal read voltage position according to the present invention: if the respective amounts of shift (Offset 1 and Offset 2) of the two adjacent threshold voltage states after data retention can be obtained, the Offset distance of the optimal read voltage with respect to the default read voltage is approximately equal to the arithmetic average of the amounts of shift of the two threshold voltage distributions, whereby an approximate position of the ideal optimal read voltage can be obtained.
Through intensive research and analysis of Gaussian functions, a mathematical model shown in FIG. 6 is established to solve the drift amount of the threshold voltage distribution of the NAND flash memory, and the specific formula is as follows:
。
in this formula, offset n RV is the drift distance of the threshold voltage state relative to its initial state default A default read voltage point, μ for the threshold voltage state initial Is the initial average of the threshold voltage distribution; sigma is the variance after the threshold voltage is shifted, and C is the number of shifts. To solve this formula, it is necessary to obtainThe obtained data has deviation quantity, average value of initial threshold voltage distribution and variance value of threshold voltage distribution after data retention.
The average value of the initial threshold voltage distribution can be obtained by combining the width of the threshold voltage distribution in the shipping state of the NAND flash memory particles with the default read voltage position set in shipping, namely, the half position of the initial width or the middle position of the adjacent default read voltage; the variance can be collected in advance through Gaussian fitting of threshold voltage distribution, and the variance function under different conditions is led into a certain position in the controller, so that the variance can be conveniently called when the best read voltage is estimated.
And for the deviation quantity, the difference between the written threshold voltage state quantity and the read threshold voltage state quantity is calculated again by recording the written threshold voltage state quantity and the read threshold voltage state quantity, so that C is obtained.
In this embodiment, the number of read threshold voltage states is obtained by reading a default read voltage.
For a multi-value memory, the deviation amount is determined in a mode from high order to low order, for the threshold voltage state of the highest order, the deviation amount is equal to the difference value between the threshold voltage state amount read out by the default read voltage and the written threshold voltage state amount, for the threshold voltage state of the non-highest order, the deviation amount c=c1-C2, C1 is the deviation amount of the threshold voltage state of the last order, and C2 is the difference value between the threshold voltage state amount read out by the default read voltage corresponding to the present threshold voltage state and the written threshold voltage state amount.
In this embodiment, the number of deviations corresponding to left bias errors is taken as an example, and first, the error characteristics of NAND flash memory particles during the data retention period are measured. FIG. 7 shows the ratio of right bias errors to total errors between adjacent programming states at 10 and 2000 erase cycles (P/E Cycling). As can be seen from the figure, as the data retention time increases, the ratio of right bias errors in the total errors becomes lower and lower, and the ratio by the time of data retention for 25 days is already lower than 1%. This means that almost all errors are caused by left-hand errors with long data retention. It should be noted that, since the data error read by the default read voltage is generally not higher than the decoding limit of the error correction code of the flash memory controller under the short-time data retention, the best read voltage point is not required to be found under the short-time data retention scenario.
Based on the error rule of NAND flash memory particles under long-time data retention, recording the number of each state when writing data; counting the number of each state when reading data, the left bias error can be approximately determined by the difference between the number of writing and reading. The specific rules are as follows: the reduction of the number of the 'G' states corresponding to the highest threshold voltage read by the default read voltage relative to the number of the written 'G' states is the left bias error of the 'G' states, denoted as G Error of left deviation The method comprises the steps of carrying out a first treatment on the surface of the Then the G is subtracted from the F' state writing quantity and reading quantity Error of left deviation The difference after the part is approximately considered to be left-hand error of the 'F' state, i.e. F Error of left deviation . Similarly, we can get left-bias errors for all programmed states.
We fit a gaussian function to the NAND flash threshold voltage distribution to extract the variance parameters for different cases. Fig. 8 and 9 show variance parameters at different data retention times when P/E cycling=10 and P/E cycling=2000, respectively.
After three parameters of left bias error, initial mean value of threshold voltage distribution and threshold voltage Gaussian distribution variance after data retention are obtained, the position of the optimal reading voltage point can be estimated according to a formula. We calculate the deviation distance of the estimation result from the ideal optimal read voltage point and represent it by a Cumulative Distribution Function (CDF). FIG. 10 is a CDF distribution graph of the deviation distance between the estimated optimal read voltage and the ideal optimal read voltage in the early life of the flash memory, i.e. when the P/E Cycling is 10 times; FIG. 11 shows a CDF distribution graph of the offset distance between the estimated optimal read voltage and the ideal optimal read voltage point at the end of life of the bit flash memory, i.e. at 2000P/E cycles.
The embodiment is based on a data holding scene, so the right value of the formula equal sign is left bias error; however, in specific application, the numerical value on the right of the equal sign can be replaced by other reasonable data according to actual conditions.
It can be seen that for NAND flash grains, both early and late in life: almost 100% of the probability deviation distance is controlled within 2, and more than 60% of the probability deviation distance is controlled within 1. The scheme provided by the invention is excellent in accuracy of estimating the optimal read voltage position. In summary, the method for determining the optimal read voltage of the memory provided by the invention has scientificity and feasibility.
Based on the experimental analysis conclusion, the invention provides a high-efficiency method for determining the optimal reading voltage of a memory, and belongs to a solution of a memory control chip. The method can estimate the position of the optimal read voltage by only issuing one read operation, and takes the deviation distance between the estimated optimal read voltage point and the ideal optimal read voltage as a judgment standard.
The specific steps of the embodiment for estimating the optimal read voltage are as follows:
1. recording the number of the user data corresponding to each threshold voltage state when the user data is written into the memory;
2. writing initial threshold voltage distribution mean values and Gaussian distribution variance parameters corresponding to different conditions into a storage controller in advance, wherein the data can be obtained through early measurement and analysis;
3. recording the number of read data corresponding to each threshold voltage state during read operation, and calculating the difference value between the number of read states and the number of write states;
4. the difference is used as a numerical value on the right of the equal sign in the formula, and the initial average value of the threshold voltage distribution and rough variance data corresponding to data during reading operation are respectively imported into the formula, so that the optimal reading voltage position can be determined.
FIG. 12 is a flowchart illustrating the operation of estimating the optimum read voltage position according to the present invention.
The present invention entails collecting variance data for threshold voltage distributions under different conditions, including but not limited to: the retention time of data, the abrasion degree of storage particles, the read-write interference suffered by the data and the like; when the method is called, variance data with approximate conditions is taken;
the present embodiment is based on an actual test system and a NAND flash memory test chip, and we develop a series of implementation cases, and one of them is used to describe the implementation method of the present invention in detail.
The particles used in this example were 3D charge trapping TLC NAND flash memory particles, which had a total of 64 stacked layers, with 256 physical pages (pages) per memory Block (Block). According to the default read voltage set when the test chip leaves the factory and the threshold voltage distribution in the initial state (the interference degree of the data is small), the initial average value of the threshold voltage distribution is determined: for the states of 'A' to 'F', the initial average value is 17; for the 'G' state, the initial average is 19. After the initial mean and variance data are obtained, we take physical Page1 as an example, and the best read voltage determining process is performed as follows:
step 1, recording the quantity of eight threshold voltage states from Er 'to G' corresponding to Page1 writing data:
[18520,17571,18115,18779,18295,18204,18482,18722]。
step 2, we read P/E cycling=2000, page1 after 25 days of data retention stores data, the number of eight threshold voltage states read out is: [18552,17659,18493,18848,19214, 18639,19119,16164].
Step 3, calculating the difference value of the quantity of the writing and reading of the states of ' A ' -G ': [32,120,498,567,1486,1921,2558].
And 4, substituting the difference value in the step 3 into the right of the equal sign of the formula (1), and substituting the corresponding variance data and the initial mean value of the threshold voltage distribution in the P/E cycling=2000 and the data retention time of 25 days in the figure 9 into the left of the equal sign.
Step 5, according to the calculated offset distance of the threshold voltage, combining with the graph shown in fig. 5, the offset distance of the optimal read voltage of v 1-v 6 relative to the default read voltage is obtained: [4,7,7,10,11,12].
During the use process of the NAND flash memory, the threshold voltage shifts due to various interferences of data, and the data read by the default read voltage has great errors; by adjusting the position of the read voltage, a part of read errors can be offset to a certain extent, the reliability of the memory system is improved, and the read voltage with the least read errors is the optimal read voltage. The invention only needs to issue the default read voltage once, and can estimate the best read voltage by means of other necessary parameters, and the estimation accuracy is extremely high. The invention can greatly reduce the reading error, ensure the performance of the system and consider the efficiency and the reliability of the system.
The foregoing description is only of the basic principles and preferred embodiments of the present invention, and modifications and alternatives thereto will occur to those skilled in the art to which the present invention pertains, as defined by the appended claims.
Claims (9)
1. A method for determining an optimal read voltage of a memory, comprising: the method comprises the following steps:
s01), setting an optimal read voltage point as a cross point of adjacent threshold voltage states of the memory, wherein a default read voltage point is a read voltage point set when the memory leaves a factory;
s02), calculating the drift distances offset1, offset2 of two adjacent threshold voltage states relative to the initial state, and calculating the drift distance of a certain threshold voltage state relative to the initial state thereof according to the formula:
，
wherein offset is n RV is the drift distance of the threshold voltage state relative to its initial state default A default read voltage point, μ for the threshold voltage state initial Is the initial average of the threshold voltage distribution; sigma is the variance after the threshold voltage is deviated, and C is the deviation quantity; using a formula to calculate offset n When the mu is obtained first initial 、σ、C；
S03), offset distance offset= (offset 1+ offset 2)/2 of the optimal read voltage point relative to the default read voltage point, and determining the optimal read voltage point according to the offset distance and the default read voltage point.
2. The memory optimum read voltage determination method according to claim 1, wherein: c is the error number corresponding to left bias error or right bias error, the left bias error refers to the corresponding threshold voltage higher than the read voltage when writing data, but the threshold voltage is lower than the read voltage when reading data, the right bias error refers to the corresponding threshold voltage lower than the read voltage when writing data, but the threshold voltage is higher than the read voltage when reading data.
3. The memory optimum read voltage determination method according to claim 1, wherein: c is obtained by recording the number of written threshold voltage states and the number of read threshold voltage states and calculating the difference between the two states.
4. The memory optimal read voltage determination method of claim 3, wherein: and obtaining the quantity of the read threshold voltage states through one default read voltage reading.
5. The memory optimal read voltage determination method of claim 3, wherein: for a multi-value memory, the deviation amount is determined in a mode from high order to low order, for the threshold voltage state of the highest order, the deviation amount is equal to the difference value between the threshold voltage state amount read out by the default read voltage and the written threshold voltage state amount, for the threshold voltage state of the non-highest order, the deviation amount c=c1-C2, C1 is the deviation amount of the threshold voltage state of the last order, and C2 is the difference value between the threshold voltage state amount read out by the default read voltage corresponding to the present threshold voltage state and the written threshold voltage state amount.
6. The memory optimum read voltage determination method according to claim 1, wherein: the initial average of the threshold voltage distribution is at a half position of the width of the threshold voltage distribution in the NAND flash memory grain factory state or at an intermediate position before the adjacent default read voltage.
7. The memory optimum read voltage determination method according to claim 1, wherein: the way to obtain the variance after the threshold voltage is shifted is: the threshold voltage distributions in different cases are extracted by gaussian fitting.
8. The memory optimum read voltage determination method according to claim 7, wherein: the different conditions include wear level, data retention time, read-write interference level.
9. The memory optimum read voltage determination method according to claim 1, wherein: the method is suitable for SLC, MLC, TLC, QLC flash memory particles.
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