CN112968851B - Multi-channel stereo FM broadcast modulator - Google Patents

Multi-channel stereo FM broadcast modulator Download PDF

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CN112968851B
CN112968851B CN202110434764.1A CN202110434764A CN112968851B CN 112968851 B CN112968851 B CN 112968851B CN 202110434764 A CN202110434764 A CN 202110434764A CN 112968851 B CN112968851 B CN 112968851B
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frequency
signal
phase
data
carrier
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CN112968851A (en
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焦杰
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Jilin Radio And Television Research Institute (science And Technology Information Center Of Jilin Radio And Television Bureau)
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Jilin Radio And Television Research Institute (science And Technology Information Center Of Jilin Radio And Television Bureau)
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/12—Modulator circuits; Transmitter circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/86—Arrangements characterised by the broadcast information itself
    • H04H20/88—Stereophonic broadcast systems

Abstract

A multi-channel stereo FM broadcast modulator relates to the field of broadcast television, and solves the problems that the existing digital multi-channel FM broadcast modulator circuit is complex and high in cost and does not have FM stereo coding, and comprises an FPGA and an FPGA peripheral circuit; in the FPGA, the sampling frequency is more than four times of the output frequency, but higher requirements are put forward on the calculation speed; because the maximum calculation frequency of the general FPGA is difficult to exceed 150MHz, the 432MHz frequency calculation of the multiplication of 108MHz maximum frequency of the frequency modulation and broadcasting cannot be met; four-phase carrier modulators with 90-degree phase difference are designed, each working frequency is 114MHz, only one quarter of one carrier is calculated, and then the carriers are combined into a complete carrier according to the sequential relation of the phase difference. In the case of five frequencies and four phases, the reset mode of the circuit is more complicated than the traditional simple single-clock reset mode, and the latch synchronization of the input program signal is different from the traditional single-clock condition.

Description

Multi-channel stereo FM broadcast modulator
Technical Field
The invention relates to the field of broadcast television, in particular to a multichannel stereo frequency modulation broadcast modulator.
Background
According to national standard regulation of national frequency modulation broadcasting in China, frequency modulation is adopted for frequency modulation broadcasting programs, the frequency range is from 87MHz to 108MHz, and the maximum frequency deviation is 75 KHz; the prior documents of 'frequency modulation broadcasting multi-path digital modulation system' and 'a multi-channel signal modulator' introduce equipment capable of modulating and transmitting a plurality of sets of programs simultaneously, which all adopt a secondary modulation method, firstly use a program baseband signal to modulate frequency modulation and modulate an intermediate frequency carrier, then sum the intermediate frequency signals of a plurality of programs, and finally move the summed integral frequency spectrum to a frequency modulation broadcasting frequency band; in such a mode, the signal processing process is complex, the number of elements required by the circuit is large, especially in the circuit for realizing the frequency spectrum shifting function, the indexes of the used devices such as an analog multiplier, a filter, a phase shifter and the like are high in requirement, and if the device is manufactured by using low-cost elements, even if the device can reluctantly realize the broadcasting and the emission of multiple programs, the harmonic interference index can hardly meet the national standard requirement;
in application environments such as frequency modulation broadcast signal blind spot coverage and the like, higher requirements are placed on the volume and the cost of equipment; the invention does not adopt a high-end element, only uses a low-cost general FPGA, modulates the input broadcast program sound digital signal to radio frequency after being subjected to stereo coding, and realizes multi-path modulation through digital summation output; the channel on which each program is modulated can be set arbitrarily; the output signal has good waveform and small interference to external harmonic waves;
disclosure of Invention
The invention provides a multi-channel stereo FM broadcast modulator, aiming at solving the problems that the existing digital multi-channel FM broadcast modulator is complex in circuit, high in cost and free of FM stereo coding.
A multi-channel stereo FM broadcast modulator comprises an FPGA and an FPGA peripheral circuit;
a phase-locked loop, an adder, an SPI interface and four-phase carrier modulation circuits are set in the FPGA;
each carrier modulation circuit comprises a memory, a counter, a data selector, a D trigger, a multi-path clock restorer and four carrier frequency modulators with the phase differences of 90 degrees, wherein the four carrier frequency modulators are respectively an A-phase carrier frequency modulator, a B-phase carrier frequency modulator, a C-phase carrier frequency modulator and a D-phase carrier frequency modulator;
the multi-channel clock restorer is used for restoring the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator, the D-phase carrier frequency modulator and the counter;
frequency multiplication is carried out on a 50MHz signal of an external active crystal oscillator through a phase-locked loop to form five signals, namely a high-frequency clock signal, a signal A, a signal B, a signal C and a signal D, wherein the phase differences of the signals A, the signal B, the signal C and the signal D are 90 degrees and are reversed on the rising edge of the high-frequency clock signal;
transmitting the high-frequency clock signal, the signal A, the signal B, the signal C and the signal D to each four-phase carrier modulation circuit; the signal A, the signal B, the signal C and the signal D are respectively used as a clock signal of the phase-A carrier frequency modulator, a clock signal of the phase-B carrier frequency modulator, a clock signal of the phase-C carrier frequency modulator and a clock signal of the phase-D carrier frequency modulator correspondingly;
the counter accumulates high-frequency clock signals, outputs count values to be sent to the data selector, and enables the data selector to sequentially and circularly select the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator;
the external four sets of broadcasting program sound signals are sent into the FPGA from the SPI, the four sets of programs are respectively and correspondingly sent into four-phase carrier modulation circuits, an A-phase carrier frequency modulator, a B-phase carrier frequency modulator, a C-phase carrier frequency modulator and a D-phase carrier frequency modulator in each four-phase carrier modulation circuit jointly complete stereo coding and modulation of one set of programs, each carrier frequency modulator executes one-fourth phase modulation, and then signals output by four carrier high-frequency devices with 90-degree phase differences are combined into one set of program radio-frequency carriers through a data selector and a D trigger; after the four sets of programs are respectively modulated into four sets of program radio frequency carriers, data summed by the summator are output to the FPGA peripheral circuit.
The invention has the beneficial effects that:
the modulator only adopts a low-cost universal FPGA integrated circuit with the model number of EP4CE10 and a small number of peripheral elements to design a four-way broadcast modulation circuit;
designing an encoder and a modulator for each path of program in the FPGA; usually, the sampling frequency of the DDS system needs to be more than three times of the maximum value of the output frequency, otherwise, more harmonic waves can be generated; in order to improve the harmonic suppression index, the sampling frequency is designed to be four times greater than the output frequency, but higher requirements are put forward on the calculation speed; because the maximum calculation frequency of the general FPGA is difficult to exceed 150MHz, the 432MHz frequency calculation of the multiplication of 108MHz maximum frequency of the frequency modulation and broadcasting cannot be met; in order to solve the problem that the FPGA has insufficient calculation speed and cannot realize carrier modulation operation, four-phase carrier modulators with 90-degree phase difference are designed, each working frequency is 114MHz, only one quarter of one carrier is calculated, and then the four-phase carrier modulators are combined into a complete carrier according to the sequential relation of the phase difference.
In the case of five frequencies and four phases, the reset mode of the circuit is more complicated than the traditional simple reset with a single clock, and the latch synchronization of the input program signal is also different from the traditional single clock.
Drawings
FIG. 1 is a schematic diagram of the connection relationship between FPGA peripheral circuits and FPGA pins in the multi-channel stereo FM broadcast modulator according to the present invention;
FIG. 2 is a block diagram of an internal circuit configuration of the FPGA;
FIG. 3 is a block diagram of a single modulation circuit;
FIG. 4 is a block diagram of a carrier frequency modulation circuit;
fig. 5 is a block diagram of two frequency generators in a carrier frequency modulation circuit.
Detailed Description
The multi-channel stereo fm broadcast modulator of the present embodiment is described with reference to fig. 1 to 5, and includes an FPGA and an FPGA peripheral circuit;
the FPGA peripheral circuit adopts an FPGA integrated circuit design circuit with the model number of EP4CE10, and FIG. 1 is a schematic diagram of the design circuit, which comprises the following steps; the input end SDI, the input end SCK, the output end RFOUT, the integrated circuit U1A, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the capacitor C1 and the high-frequency transformer T1;
the input end SDI is electrically connected with a pin 23 of the integrated circuit U1A;
the input terminal SC3K is electrically connected with pin 21 of the integrated circuit U1A;
the resistor R1 is electrically connected with the 11 pin of the integrated circuit U1A;
the resistor R2 is electrically connected with the 12 pins of the integrated circuit U1A;
the resistor R3 is electrically connected with a pin 13 of the integrated circuit U1A;
the resistor R4 is electrically connected with pin 1 of the integrated circuit U1A;
the resistor R5 is electrically connected with the pin 2 of the integrated circuit U1A;
the resistor R6 is electrically connected with the pin 3 of the integrated circuit U1A;
the resistor R7 is electrically connected with the 6 pins of the integrated circuit U1A;
the resistor R8 is electrically connected with the 14 pins of the integrated circuit U1A;
the resistor R9 is electrically connected with the pin 15 of the integrated circuit U1A;
the resistor R10 is electrically connected with the 16 pins of the integrated circuit U1A;
the resistor R11 is electrically connected with the 18 pins of the integrated circuit U1A;
the resistor R12 is electrically connected with the pin 20 of the integrated circuit U1A;
the resistor R13 is electrically connected with the pin 7 of the integrated circuit U1A;
the resistor R14 is electrically connected with the pin 8 of the integrated circuit U1A;
the resistor R15 is electrically connected with a pin 9 of the integrated circuit U1A;
the resistor R16 is electrically connected with the 10 pin of the integrated circuit U1A;
a resistor R1, a resistor R2, a resistor R3, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12 and a capacitor C1 are respectively and electrically connected with a pin 3 of the high-frequency transformer T1;
the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R13, the resistor R14, the resistor R15, the resistor R16 and the capacitor C1 are electrically connected with a pin 1 of the high-frequency transformer T1 respectively;
the output end RFOUT is electrically connected with a pin 2 of the high-frequency transformer T1; GND is electrically connected to the 4-pin of the high-frequency transformer T1.
Sound data of a broadcast program are input into the FPGA in serial, communication data are input in an SPI format, serial data are input into an SDI (serial digital interface), and a clock is input into an SCK (serial clock); the input content may be not only program sound data but also a command to set a modulation frequency;
the modulated broadcast frequency modulation signal is output from an output end RFOUT and is used for being sent to a high-frequency amplifier for amplification and then being transmitted, so that the broadcast coverage of the frequency modulation broadcast program is realized.
In this embodiment, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, and the resistor R16 form an 8-bit differential DAC circuit, which is different from a conventional DAC in that a signal corresponding to a digital value is not output but a data difference signal; the output signal is sent to a capacitor C1 and a high-frequency transformer T1; the RLC resonant circuit is composed of a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16 and a capacitor C1 through a high-frequency transformer T1, the resonant frequency of the whole resonant circuit is designed to be 98MHz, and the quality factor value is in the range of 2 to 3.
The FPGA internal circuit according to this embodiment is designed as shown in fig. 2, and includes four-phase carrier modulation circuits (carrier modulation circuit 1, carrier modulation circuit 2, carrier modulation circuit 3, and carrier modulation circuit 4), a phase-locked loop, an adder, an SPI interface, and an output pin.
An external active crystal oscillator with the frequency of 50MHz is used as an external clock of the FPGA, and a phase-locked loop multiplies the frequency of a 50MHz signal of the external active crystal oscillator into 5 signals, namely a signal A, a signal B, a signal C, a signal D and a high-frequency clock signal; wherein the frequency of the high-frequency clock signal is 456 MHz; the frequency of the signal a, the signal B, the signal C, and the signal D is one fourth of the high-frequency clock signal, that is, all of the signals are 114MHz, but the phases of the signals are different, the signal a leads the signal B by 90 degrees, the signal B leads the signal C by 90 degrees, and the signal C leads the signal D by 90 degrees, all of which are inverted on the rising edge of the high-frequency clock signal; the high-frequency clock signals, the signal A, the signal B, the signal C and the signal D are all sent to a carrier modulation circuit 1, a carrier modulation circuit 2, a carrier modulation circuit 3, a carrier modulation circuit 4 and an adder to use the high-frequency clock signals; the SPI interface uses the signal A as a self clock signal; the stereo synchronization signal of 76KHz is obtained by dividing 114MHz frequency by 1500 times.
The external four sets of broadcast program sound data are sent from the SPI interface, each set of program data are respectively sent to the carrier modulation circuit 1, the carrier modulation circuit 2, the carrier modulation circuit 3 and the carrier modulation circuit 4 according to the corresponding relation of the written addresses, each modulation circuit carries out stereo coding and modulation on the programs and then sends the programs to the adder, and the summed data are output to the FPGA peripheral circuit through the output pins.
In this embodiment, the SPI interface may also receive control commands, may set up and control each modulation circuit individually, may set up program modulation frequency, and sets up whether to perform stereo encoding on the input program.
To explain the present embodiment with reference to fig. 3, fig. 3 is a structural diagram of a single carrier modulation circuit, which includes a memory, a counter, a data selector, a D flip-flop, a multi-clock reset, and four carrier modulators, where the four carrier modulators are an a-phase carrier modulator, a B-phase carrier modulator, a C-phase carrier modulator, and a D-phase carrier modulator, respectively;
in order to enable the modulation circuit to generate sine waves, a 12-bit read-only memory with 4096 addresses is designed in the FPGA and used for storing sine value data to form a sine table which can be regarded as an array of [0,2 pi ] intervals; because the sine value of all angles can be calculated only by the numerical value of the [0, pi/2 ] interval, the sine array does not need to cover the whole 2 pi range in order to save the storage space; however, the system mainly aims at increasing the speed, and the storage space is enough, so that all data in the interval of [0,2 pi ] are stored, and the calculation speed is increased in a mode of increasing the storage cost; data in the sine table are 12-bit signed integers, the designed peak-to-peak value is equal to FB0H, the maximum value is FCFH, the minimum value is 030H, and intermediate calculation overflow can be effectively prevented; only the sine table is shared by four modulation circuits corresponding to four sets of programs in the FPGA.
Each carrier modulation circuit is provided with four carrier frequency modulators with the same structure, namely an A-phase carrier frequency modulator, a B-phase carrier frequency modulator, a C-phase carrier frequency modulator and a D-phase carrier frequency modulator; the four carrier frequency modulators respectively use four signals which are 90 degrees with each other as working clocks, the signals are generated by a phase-locked loop 5, and respectively are a signal A as a clock of the A-phase carrier frequency modulator, a signal B as a clock of the B-phase carrier frequency modulator, a signal C as a clock of the C-phase carrier frequency modulator, and a signal D as a clock of the D-phase carrier frequency modulator;
the counter accumulates high-frequency clock signals, the output count value is calculated to be 1024 as a phase value of a carrier, the phase value is used for obtaining the value of the signal from the sine table and is sent to the data selector, so that the data selector circularly and sequentially selects the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator to output, and the radio frequency carrier output of a program is generated.
The traditional digital circuit only needs to simply carry out asynchronous reset or reset at one edge of a clock, however, in the system, because a carrier modulation circuit has 5 different working clocks and has phase difference, the traditional reset mode cannot be used, and a multipath clock reset device is required to be adopted;
in fig. 3, a phase a carrier frequency modulator, a phase B carrier frequency modulator, a phase C carrier frequency modulator, a phase D carrier frequency modulator, and a counter are provided for resetting; respectively latching the signal A, the signal B, the signal C and the signal D by using a D trigger at the rising edge of the high-frequency clock signal to obtain four latching signals; judging four latching signals during the system reset required period, if the signal A, the signal B and the signal C are 1 after being latched, and the signal D and the signal C are 0 after being latched, then resetting is carried out on the rising edge of the next high-frequency clock signal; if reset is performed at other times, the phase relationship of the data calculation inside the four carrier frequency modulation circuits is destroyed, and finally the four signals are combined in error.
In this embodiment, the counter in fig. 3 is a two-bit binary counter, which is cleared during reset, and is incremented at the rising edge of the 456M high-frequency clock signal after reset, and latches the output data of the data selector at the rising edge of the 456M high-frequency clock signal to be output as a set of radio frequency carriers of the fm broadcast program.
The counter outputs two-bit data to a data selection end of the data selector; therefore, the data selector can select the data output by one of the four carrier frequency modulators to be sent to the D end of the D trigger according to the numerical value in the counter, and the specific selection corresponding relation is;
selecting an A-phase carrier frequency modulator when the numerical value in the counter is 0, selecting a B-phase carrier frequency modulator when the numerical value in the counter is 1, selecting a C-phase carrier frequency modulator when the numerical value in the counter is 2, and selecting a D-phase carrier frequency modulator when the numerical value in the counter is 3;
the high-frequency clock signal is simultaneously sent to a clock end of the counter and a clock end of the D trigger, and the rising edge of the high-frequency clock signal enables data at a Q output end of the D trigger to jump into D input data of the D trigger while the numerical value of the counter is increased by one; the data output from the Q output end of the D flip-flop is the data externally output by the four-phase carrier modulation circuit.
Referring to fig. 4, a structure diagram of a carrier frequency modulator according to the present embodiment includes a carrier phase step register, a frequency modulation phase frequency length register, a stereo encoder, a carrier frequency generator, a frequency modulation frequency generator, a multiplier I, a multiplier Q, and a subtractor;
the SPI interface outputs two values to the carrier frequency modulation circuit, one is a voltage value of a broadcast program sound signal in an 8-bit unsigned number format, and the other is a carrier phase step value; because the frequency modulation frequency offset stepping quantity in the frequency modulation frequency generator expressed by 8-bit unsigned number format is exactly equal to 256 times of the phase stepping quantity, the voltage value of the sound signal can be directly stored in a frequency modulation phase stepping register as the frequency modulation frequency offset phase stepping value; carrier phase step number NfThe carrier phase step length register stores the frequency information, and then the frequency information is sent to the carrier frequency generator, so that the frequency modulation carrier transmitting frequency F of the set of broadcasting programs can be determined;
F＝Nf*114/1024+0.075
the broadcast program input to the carrier frequency modulation circuit can be modulated to a specified broadcast frequency by only setting a carrier phase step value on the SPI interface.
In this embodiment, the program encoder located between the frequency modulation phase step register and the frequency modulation frequency generator can set the function of enabling or disabling the stereo encoding; when the function of the stereo encoder is closed, the data in the frequency modulation phase step length register is directly sent to a frequency modulation frequency generator; when the stereo encoder is started, data in the frequency modulation phase step length register is subjected to stereo encoding and then is sent to a frequency modulation frequency generator, and the specific method is that;
dividing the frequency of 114MHz by 1500 to obtain a stereo synchronous signal of 76 KHz; then, dividing the stereo synchronous signal by two to obtain a 38KHz stereo carrier signal; the stereo carrier signal is divided by two again to obtain a pilot signal of 19 KHz; the three signals can not be obtained by simply dividing two frequency division by an asynchronous frequency division circuit, but 114MHz signals are used as clocks, and a synchronous sequential logic design is used to realize that the edges of the three signals of 76KHz, 38KHz and 19KHz can uniformly jump at the rising edge of 114MHz, otherwise, obvious noise is generated when four-phase combined frequency modulation carriers are used;
the data in the frequency modulation phase step length register is divided into left channel data and right channel data; designing a pilot constant to be equal to 12 according to circuit parameters in the system; using a coding counter to accumulate and count on the rising edge of a 114MHz clock signal, when the numerical value in the coding counter is 1499, resetting the coding counter by the next clock, and changing the data value of stereo coding output sent to a frequency modulation frequency generator, wherein four changing conditions are specifically generated;
1) when the pilot signal of 19KHz and the stereo carrier signal of 38KHz are both low level, the output data is equal to the left channel data plus the pilot constant;
2) when the pilot signal of 19KHz and the stereo carrier signal of 38KHz are both high level, the output data is equal to the right channel data plus the pilot constant;
3) when the pilot signal of 19KHz is high level and the stereo carrier signal of 38KHz is low level, the output data is equal to the left channel data minus the pilot constant;
4) when the 19KHz pilot signal is low and the 38KHz stereo carrier signal is high, the output data is equal to the right channel data minus the pilot constant.
In this embodiment, there are two frequency generators in the carrier frequency modulator, which are a carrier frequency generator and a frequency modulation frequency generator, and their circuit structures are completely the same, and they are all obtained by accumulating the input phase step with a 114MHz clock, and obtaining orthogonal I/Q data from a sine table, and fig. 5 is a structural block diagram of these two frequency generators; n is a radical offIs a phase step value, 114MHz is a clock signal, and R is a reset signal;
when a reset signal arrives, a phase accumulator of a carrier frequency generator in the A-phase carrier frequency modulator is cleared; setting reset initial value equal to N for phase accumulator of carrier frequency generator in B-phase carrier frequency modulatorfSetting reset initial value equal to N in phase accumulator of carrier frequency generator in C-phase carrier frequency modulatorf2; carrier frequency modulationPhase accumulator of D phase carrier frequency generator sets reset initial value equal to Nf*3。
After the reset signal is finished, the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator are operated by respective 114MHz clocks, and each clock has a long upper edge, and the phase accumulator accumulates a phase step number N once at each rising edge of the clock signal FfAnd discarding the accumulated overflow values; in the carrier frequency generator, the numerical value in the phase accumulator is used as the address of the sine table, and I data output in an I/Q data pair can be obtained from the sine table; the value in the phase accumulator is added to 1024 to be used as the address of the sine table, and the Q data output in the I/Q data pair can be obtained from the sine table;
the numerical value of a phase accumulator which is used as the address of the sine table in the frequency modulation frequency generator is shifted by 8 bits on the right and then is used as the address to obtain I data from the sine table; the phase accumulator value is shifted by 8 bits right and then 1024 is added to get the Q data from the sine table as an address.
In the present embodiment, I is the pair of I/Q data generated from the carrier frequency generatorFFor I data, QFQ data are 12-bit binary numbers; from the I/Q data pairs generated by the FM frequency generator, ISFor I data, QSQ data are 18-bit binary numbers;
multiplier I outputs I from carrier frequency generatorFI of signal and frequency-modulated frequency generator outputSMultiplying the signals to obtain MI data; multiplier Q for multiplying the Q output from the carrier frequency generatorFQ of signal and frequency-modulated frequency generator outputSMultiplying the signals to obtain MQ data; subtracting MI and MQ by a subtracter to obtain quarter-phase output in the four-phase combined frequency modulation carrier;
if the carrier frequency is dynamically set, resetting is executed after the numerical value in the carrier phase step length register is set; otherwise, the generated four-phase combined frequency modulation carrier generates more harmonic waves.
In this embodiment, the data sent from the stereo encoder to the fm frequency generator needs to perform phase synchronization; namely, a data latch is used for latching data at the rising edge of a clock; the purpose is to lead the program code numerical values input by the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator in a working cycle period to be the same; the carrier frequency modulation A phase, the carrier frequency modulation C phase and the carrier frequency modulation D phase all use the signal A as a synchronous clock; the phase B carrier frequency modulator must use the signal D as a synchronous clock to realize phase advance accumulation; if the phase synchronization relationship is incorrect, the generated four-phase combined frequency modulation carrier generates more harmonic waves.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (8)

1. The multi-channel stereo FM broadcasting modulator is characterized in that: the FPGA-based touch screen comprises an FPGA and an FPGA peripheral circuit;
a phase-locked loop, an adder, an SPI interface and four-phase carrier modulation circuits are set in the FPGA;
each carrier modulation circuit comprises a memory, a counter, a data selector, a D trigger, a multi-path clock restorer and four carrier frequency modulators with the phase differences of 90 degrees, wherein the four carrier frequency modulators are respectively an A-phase carrier frequency modulator, a B-phase carrier frequency modulator, a C-phase carrier frequency modulator and a D-phase carrier frequency modulator;
the multi-path clock restorer is used for restoring the phase A carrier frequency modulator, the phase B carrier frequency modulator, the phase C carrier frequency modulator, the phase D carrier frequency modulator and the counter;
frequency multiplication is carried out on a 50MHz signal of an external active crystal oscillator through a phase-locked loop to form five signals, namely a high-frequency clock signal, a signal A, a signal B, a signal C and a signal D, wherein the phase differences of the signals A, the signal B, the signal C and the signal D are 90 degrees and are reversed on the rising edge of the high-frequency clock signal;
transmitting the high-frequency clock signal, the signal A, the signal B, the signal C and the signal D to each four-phase carrier modulation circuit; the signal A, the signal B, the signal C and the signal D are respectively used as a clock signal of the phase-A carrier frequency modulator, a clock signal of the phase-B carrier frequency modulator, a clock signal of the phase-C carrier frequency modulator and a clock signal of the phase-D carrier frequency modulator correspondingly;
the counter accumulates high-frequency clock signals, outputs count values to be sent to the data selector, and enables the data selector to sequentially and circularly select the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator;
the external four sets of broadcasting program sound signals are sent into the FPGA from the SPI, the four sets of programs are respectively and correspondingly sent into four-phase carrier modulation circuits, an A-phase carrier frequency modulator, a B-phase carrier frequency modulator, a C-phase carrier frequency modulator and a D-phase carrier frequency modulator in each four-phase carrier modulation circuit jointly complete stereo coding and modulation of one set of programs, each carrier frequency modulator executes one-fourth phase modulation, and then signals output by four carrier high-frequency devices with 90-degree phase differences are combined into one set of program radio-frequency carriers through a data selector and a D trigger; after the four sets of programs are respectively modulated into four sets of program radio frequency carriers, data summed by the summator are output to the FPGA peripheral circuit.
2. A multiplex stereo fm broadcast modulator as defined in claim 1, wherein: the frequency of the high-frequency clock signal is 456 MHz; the frequency of the signal A, the signal B, the signal C and the signal D is one fourth of that of the high-frequency clock signal, and the frequency of the signal A, the frequency of the signal B, the frequency of the signal C and the frequency of the signal D are all 114 MHz; the phases of the signal A, the signal B, the signal C and the signal D are different, the signal A leads the signal B by 90 degrees, the signal B leads the signal C by 90 degrees, and the signal C leads the signal D by 90 degrees, and the signals are all inverted on the rising edge of the high-frequency clock signal.
3. A multi-channel stereo fm broadcast modulator according to claim 1 or 2, wherein: each carrier frequency modulator comprises a carrier phase step register, a frequency modulation phase step register, a stereo encoder, a carrier frequency generator, a frequency modulation frequency generator, a multiplier I, a multiplier Q and a subtracter;
the carrier frequency modulator receives two values input by the SPI interface, namely a voltage value of a broadcast program sound signal and a carrier phase step length value;
storing the voltage value of the sound signal as a frequency modulation frequency offset phase stepping value in a frequency modulation phase stepping register;
the stereo encoder is positioned between the frequency modulation phase step register and the frequency modulation frequency generator, and data in the frequency modulation phase step register is sent to the frequency modulation frequency generator after stereo encoding;
the carrier phase step value NfThe carrier frequency is stored in a carrier phase step length register and then is sent to a carrier frequency generator, and the frequency modulation carrier transmitting frequency F of the sound signal of the broadcast program is determined;
F＝Nf*114/1024+0.075
setting a carrier phase step value on an SPI (serial peripheral interface), and modulating a broadcast program input to the carrier frequency modulator to a specified broadcasting frequency;
i data and Q data in an I/Q data pair generated by the frequency modulation frequency generator are respectively sent to a multiplier I and a multiplier Q;
i data and Q data in an I/Q data pair generated by a carrier frequency generator are respectively sent to a multiplier I and a multiplier Q;
the multiplier I multiplies the I data output by the carrier frequency generator with the I data output by the frequency modulation frequency generator to obtain data MI;
the multiplier Q multiplies Q data output by the carrier frequency generator and Q data output by the frequency modulation frequency generator to obtain data MQ; and subtracting the data MI and the data MQ by adopting a subtracter to obtain a frequency modulation carrier wave and output the frequency modulation carrier wave to the data selector.
4. A multi-channel stereo fm broadcast modulator as claimed in claim 3, wherein:
in the carrier frequency generator, a numerical value in a phase accumulator is used as an address of a sine table in a memory, I data in an I/Q data pair is obtained from the sine table, the numerical value in the phase accumulator is added with 1024 to be used as the address of the sine table, and Q data in the I/Q data pair is obtained from the sine table;
in the frequency modulation frequency generator, the numerical value of a phase accumulator which is taken as the address of a sine table is shifted to the right by 8 bits and then taken as the address to obtain I data from the sine table; the phase accumulator value is shifted right by 8 bits and 1024 is added as an address to get the Q data from the sine table.
5. A multi-channel stereo fm broadcast modulator as claimed in claim 3, wherein:
when the stereo encoder is closed, the data in the frequency modulation phase step length register is directly sent to a frequency modulation frequency generator; when the stereo coding function is started, data in the frequency modulation phase step length register is subjected to stereo coding and then is sent to the frequency modulation frequency generator, and the specific method comprises the following steps:
the SPI interface adopts a signal A as a clock signal of the SPI interface, and a frequency signal of 114MHz is subjected to frequency division for 1500 times to obtain a stereo synchronous signal of 76 KHz; the stereo synchronous signal is divided by two to obtain a 38KHz stereo carrier signal; the stereo carrier signal is divided by two again to obtain a pilot signal of 19 KHz; the 76KHz stereo synchronous signal, the 38KHz stereo carrier signal and the 19KHz pilot signal all adopt 114MHz signals as clocks, and adopt synchronous sequential logic design to realize that the edges of the 76KHz, 38KHz and 19KHz signals all jump uniformly at the rising edge of 114 MHz;
the data in the frequency modulation phase step length register is divided into left channel data and right channel data, a pilot constant is set to be equal to 12, a coding counter is adopted, the count is accumulated on the rising edge of a 114MHz clock signal, when the number value in the coding counter is 1499, the next clock clears the coding counter, simultaneously, the data value transmitted to the frequency modulation frequency generator by the stereo coder is changed, and particularly four changing conditions occur;
when a pilot signal of 19KHz and a stereo carrier signal of 38KHz are both in a low level, output data is equal to left channel data plus a pilot constant;
when the pilot signal of 19KHz and the stereo carrier signal of 38KHz are both high level, the output data is equal to the sum of the right channel data and the pilot constant;
thirdly, when the pilot signal of 19KHz is at high level and the stereo carrier signal of 38KHz is at low level, the output data is equal to the left channel data minus the pilot constant;
and fourthly, when the pilot signal of 19KHz is at low level and the stereo carrier signal of 38KHz is at high level, the output data is equal to the right channel data minus the pilot constant.
6. A multi-channel stereo fm broadcast modulator as claimed in claim 3, wherein:
carrying out phase synchronization on the data transmitted by the stereo encoder and then transmitting the data to a frequency modulation frequency generator, and carrying out data latch on the rising edge of a clock signal by adopting a data latch so that the program coding numerical values input by the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator and the D-phase carrier frequency modulator in a working cycle period are the same; the phase A carrier frequency modulator, the phase C carrier frequency modulator and the phase D carrier frequency modulator all use the signal A as a synchronous clock signal;
the phase B carrier frequency modulator adopts a signal D as a synchronous clock signal to realize phase advance accumulation.
7. A multiplex stereo fm broadcast modulator as defined in claim 1, wherein:
the counter is cleared during resetting and is accumulated and counted on the rising edge of 456M high-frequency clock signals after resetting; and the output count value is sent to a data selector, the data selector selects data output from the A-phase carrier frequency modulator, the B-phase carrier frequency modulator, the C-phase carrier frequency modulator or the D-phase carrier frequency modulator and is used as the input of a data latch formed by a D trigger, and the data selector outputs the data to be the radio frequency carrier output of a set of frequency modulation broadcasting programs at the rising edge of a high-frequency clock signal of 456M.
8. A multiplex stereo fm broadcast modulator as defined in claim 1, wherein: the FPGA peripheral circuit comprises resistors R1-R16, a capacitor C1, a high-frequency transformer T1, an input end SDI, an input end SCK and an output end RFOUT;
the input end SDI is electrically connected with a pin 23 of the integrated circuit;
the input end SCK is electrically connected with a pin 21 of the integrated circuit;
the resistor R1 to the resistor R3 are respectively connected with pins 11 to 13 of the integrated circuit;
the resistor R4-the resistor R6 are respectively connected with pins 1-3 of the integrated circuit;
the resistor R7 is electrically connected with the pin 6 of the integrated circuit;
the resistor R8-the resistor R10 are respectively connected with pins 14-16 of the integrated circuit;
resistor R11 is electrically connected to pin 18 of the integrated circuit;
the resistor R12 is electrically connected with the pin of the integrated circuit 20;
the resistor R13 to the resistor R16 are respectively connected with pins 7 to 10 of the integrated circuit;
the resistor R1-resistor R3, the resistor R8-resistor R12 and the capacitor C1 are respectively connected with the 3 pins of the high-frequency transformer T1;
the resistor R4-resistor R7, the resistor R13-resistor R16 and the capacitor C1 are respectively connected with a pin 1 of the high-frequency transformer T1;
the output end RFOUT is electrically connected with a pin 2 of the high-frequency transformer T1; GND is electrically connected to the 4-pin of the high-frequency transformer T1.
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