CN112688663A

CN112688663A - Improved generation noise suppression circuit

Info

Publication number: CN112688663A
Application number: CN202011644827.8A
Authority: CN
Inventors: 洪锋明
Original assignee: Chengdu Lingke Microelectronics Co ltd
Current assignee: Chengdu Xinyi Technology Co ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2021-04-20

Abstract

The invention discloses an improved noise suppression circuit, comprising: a Buffer1, the positive input end of which is connected with an input signal VREF and is used for receiving a band-gap reference voltage VREF before noise reduction; the input end of the reference voltage regulating circuit is connected with the reverse input end and the output end of the Buffer1 and is used for processing a reference voltage VREF and generating a voltage-adjustable reference voltage source VREF 1; the input end of the active resistance circuit is connected with the output end of the reference voltage regulating circuit; and the input end of the quick response circuit is connected with the output end of the reference voltage regulating circuit and is used for quickly establishing a low-noise reference source VREF 2. Compared with the traditional VREF reference voltage noise suppression circuit, the improved VREF reference voltage noise suppression circuit provided by the invention omits the traditional NR noise reduction pin, reduces the capacitance value of an external capacitor CNR, reduces the application of peripheral devices and improves the integration level; meanwhile, the response speed of VREF is increased, and the output response is not influenced while noise is reduced.

Description

Improved generation noise suppression circuit

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an improved noise suppression circuit.

Background

In the field of electronic circuit technology, researchers refer to all signals other than the target signal in the electronic circuit as noise, and when the noise voltage reaches a certain level, the circuit is disturbed. Generally, noise cannot be completely eliminated, and only the noise intensity can be reduced or the circuit immunity can be improved to prevent the noise from forming interference. In order to reduce noise of reference voltage VREF, a resistor RNR is generally connected in series between VREF and an error amplifier, and a filter capacitor CNR is externally connected to an NR pin to filter noise.

Disclosure of Invention

The present invention is directed to an improved noise suppression circuit for solving the above problems.

The noise suppression circuit comprises a Buffer1, a reference voltage regulating circuit, an active resistance circuit and a quick response circuit:

a Buffer1, the positive input end of which is connected with an input signal VREF and is used for receiving a band-gap reference voltage VREF before noise reduction;

the input end of the reference voltage regulating circuit is connected with the reverse input end and the output end of the Buffer1 and is used for processing a reference voltage VREF and generating a voltage-adjustable reference voltage source VREF 1;

the input end of the active resistance circuit is connected with the output end of the reference voltage regulating circuit, and the active resistance circuit is used for receiving and processing a reference voltage source VREF1 output by the reference voltage regulating circuit and generating a low-noise reference source VREF 2;

and the input end of the quick response circuit is connected with the output end of the reference voltage regulating circuit, and the output end of the quick response circuit is connected with the output end of the active resistor, so that the quick response circuit is used for quickly establishing a low-noise reference source VREF 2.

The noise suppression circuit further comprises a filter capacitor C1, and the filter capacitor C1 is connected with the output ends of the active resistance circuit and the quick response circuit.

The reference voltage adjusting circuit consists of a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, a second resistor R2 and a third resistor R3, wherein the drain electrode of the first NMOS transistor MN1 is respectively connected with the drain electrode of the first PMOS transistor MP1, the grid electrode of the first PMOS transistor MP1 and the grid electrode of the second PMOS transistor MP2, and the source electrode and the substrate of the first NMOS transistor MN are connected with one end of the first resistor R1; the source electrode and the substrate of the first PMOS tube MP1 are connected with the source electrode and the substrate of the second PMOS tube MP2, and the drain electrode of the first PMOS tube MP1 is connected with one end of a second resistor R2; the third resistor R3 is connected with the other end of the second resistor R2.

The active resistance circuit consists of a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5, wherein the source electrode and the substrate of the second NMOS transistor MN2, the source electrode and the substrate of the third NMOS transistor MN3 and the substrate of the fourth NMOS transistor MN4 are grounded; the drain of the fourth NMOS transistor MN4 is connected to the gate and the drain of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP 5; the source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the fast response circuit.

The fast response circuit is composed of a fifth NMOS transistor MN5, a sixth PMOS transistor MP6 and an inverter INV1, wherein the drain electrode of the fifth NMOS transistor MN5 is connected with the drain electrode of the sixth PMOS transistor MP 6; the input end of the inverter INV1 is connected to the input signal VREF2_ DET and the gate of the fifth NMOS transistor MN5, and the output end thereof is connected to the gate of the sixth PMOS transistor MP 6.

The degree of noise attenuation from VREF1 to VREF2 may be expressed as an attenuation function:

wherein

Wherein, RNR is the equivalent resistance of the active resistance generated after MP4 and MP5 pass through the current mirror.

The invention has the beneficial effects that: the traditional NR noise reduction pin is omitted, the capacitance value of an external capacitor CNR is reduced, the number of applied peripheral devices is reduced, and the integration level is improved; meanwhile, the response speed of VREF is increased, and the output response is not influenced while noise is reduced.

Drawings

FIG. 1 is a schematic diagram of a VREF reference voltage noise suppression circuit according to the present invention;

FIG. 2 is a schematic diagram of a VREF reference voltage noise suppression circuit of the present invention;

fig. 3 is a diagram of a conventional VREF reference voltage noise suppression solution.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the present embodiment, as shown in fig. 1, an improved noise suppression circuit includes a Buffer1, a reference voltage adjustment circuit, an active resistance circuit, and a fast response circuit:

In this embodiment, as shown in fig. 2, the noise suppression circuit further includes a filter capacitor C1, and the filter capacitor C1 is connected to the output terminals of the active resistor circuit and the fast response circuit.

In this embodiment, as shown in fig. 2, the reference voltage adjusting circuit is composed of a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, a second resistor R2 and a third resistor R3, wherein a drain of the first NMOS transistor MN1 is respectively connected to a drain of the first PMOS transistor MP1, a gate of the first PMOS transistor MP1 and a gate of the second PMOS transistor MP2, and a source and a substrate of the first NMOS transistor MN1 are connected to one end of the first resistor R1; the source electrode and the substrate of the first PMOS tube MP1 are connected with the source electrode and the substrate of the second PMOS tube MP2, and the drain electrode of the first PMOS tube MP1 is connected with one end of a second resistor R2; the third resistor R3 is connected with the other end of the second resistor R2.

In this embodiment, as shown in fig. 2, the active resistor circuit is composed of a current source I1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5, wherein the current source I1 is connected to the drain and the gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, and the gate of the fourth NMOS transistor MN 4; the source electrode and the substrate of the second NMOS transistor MN2, the source electrode and the substrate of the third NMOS transistor MN3 and the substrate of the fourth NMOS transistor MN4 are grounded; the drain of the fourth NMOS transistor MN4 is connected to the gate and the drain of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP 5; the source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the fast response circuit.

In this embodiment, as shown in fig. 2, the fast response circuit is composed of a fifth NMOS transistor MN5, a sixth PMOS transistor MP6 and an inverter INV1, wherein the drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth PMOS transistor MP 6; the input end of the inverter INV1 is connected to the input signal VREF2_ DET and the gate of the fifth NMOS transistor MN5, and the output end thereof is connected to the gate of the sixth PMOS transistor MP 6.

In this embodiment, as shown in fig. 3, one of the main noise sources for the conventional VREF reference voltage noise suppression circuit is noise at the reference voltage VREF, that is, noise at the output end of the error amplifier, in order to reduce the noise at the reference voltage VREF, it is a common practice to add an NR pin, connect a resistor RNR in series between VREF and the error amplifier, and achieve the purpose of filtering the noise by externally connecting a filter capacitor CNR to the NR pin; the method not only adds a pin and an external device, but also has the advantages that the larger CNR value causes larger time delay of the reference voltage VREF of the linear voltage regulator while the noise of RNR and CNR is reduced.

The working principle of the noise suppression circuit is as follows:

after the reference voltage VREF passes through the Buffer1, the current mirrors MP1 and MP2 and the divided voltages R2 and R3, a reference voltage source VREF1 with adjustable voltage and basically the same temperature coefficient as VREF is generated; micro-current sources generated after the MP4 and the MP5 pass through the current mirror image replace passive resistors, and the equivalent resistance of the active resistors is RNR; the capacitor C1 is a filter capacitor, and all VREF2 is a low noise reference source passing through the noise suppression circuit and is output to the error amplifier; the degree of noise attenuation from VREF1 to VREF2 may be expressed as an attenuation function:

wherein

It can be seen that the larger RNR and C1, the smaller fp, the smaller G (f), and the more effective noise suppression. Since the active resistor RNR formed by MP4 and MP5 is large, the capacitor C1 can be reduced to facilitate integration inside the chip.

In addition, the INV1, the MN5 and the MP6 are added, so that VREF2_ DET is high level, INV1 output is low level, and a transmission gate formed by MN5 and MP6 is turned on in the VREF establishment stage, so that VREF2 is equal to VREF1, the problem that the establishment time of VREF2 is slowed due to the existence of RNR can be solved, and the response time of the low dropout linear regulator is shortened.

The foregoing is illustrative of the preferred embodiments of this invention, and it is to be understood that the invention is not limited to the precise form disclosed herein and that various other combinations, modifications, and environments may be resorted to, falling within the scope of the concept as disclosed herein, either as described above or as apparent to those skilled in the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An improved noise suppression circuit, characterized in that, the noise suppression circuit comprises a Buffer1, a reference voltage regulation circuit, an active resistance circuit and a fast response circuit:

2. An improved noise suppression circuit as in claim 1 further comprising a filter capacitor C1, said filter capacitor C1 connecting the active resistor circuit and the fast response circuit output.

3. The improved noise suppression circuit of claim 1, wherein the reference voltage adjusting circuit is composed of a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, a second resistor R2 and a third resistor R3, wherein a drain of the first NMOS transistor MN1 is connected to a drain of the first PMOS transistor MP1, a gate of the first PMOS transistor MP1 and a gate of the second PMOS transistor MP2, respectively, and a source and a substrate of the first NMOS transistor MN1 are connected to one end of the first resistor R1; the source electrode and the substrate of the first PMOS tube MP1 are connected with the source electrode and the substrate of the second PMOS tube MP2, and the drain electrode of the first PMOS tube MP1 is connected with one end of a second resistor R2; the third resistor R3 is connected with the other end of the second resistor R2.

4. The improved noise suppression circuit of claim 1, wherein the active resistor circuit is composed of a current source I1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP5, wherein the current source I1 is connected to the drain and gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, and the gate of the fourth NMOS transistor MN 4; the source electrode and the substrate of the second NMOS transistor MN2, the source electrode and the substrate of the third NMOS transistor MN3 and the substrate of the fourth NMOS transistor MN4 are grounded; the drain of the fourth NMOS transistor MN4 is connected to the gate and the drain of the third PMOS transistor MP3, the gate of the fourth PMOS transistor MP4 and the gate of the fifth PMOS transistor MP 5; the source of the fifth PMOS transistor MP5 is connected to the drain of the fourth PMOS transistor MP4, and the drain thereof is connected to the fast response circuit.

5. The improved noise suppression circuit of claim 1, wherein the fast response circuit is composed of a fifth NMOS transistor MN5, a sixth PMOS transistor MP6 and an inverter INV1, wherein the drain of the fifth NMOS transistor MN5 is connected to the drain of the sixth PMOS transistor MP 6; the input end of the inverter INV1 is connected to the input signal VREF2_ DET and the gate of the fifth NMOS transistor MN5, and the output end thereof is connected to the gate of the sixth PMOS transistor MP 6.

6. An improved noise suppression circuit as in claim 1 wherein the degree of noise attenuation from VREF1 to VREF2 is expressed as an attenuation function:

wherein