CN112667535B - STBUS cascade communication method and communication system - Google Patents
STBUS cascade communication method and communication system Download PDFInfo
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Abstract
The application discloses an STBUS cascade communication method and a communication system, which can realize data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases. The method comprises the following steps: when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, obtaining a board card mark of the target function board card; judging whether an end machine exists in the target 3U machine box according to the board card mark; if the target 3U chassis has an end machine, transmitting data according to clock synchronization information generated by the target 3U chassis; and if the target 3U chassis does not have an end machine, transmitting data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to an STBUS cascade communication method and a communication system.
Background
Currently, communication schemes are an essential key part in various fields. Communication schemes are various and functional, and when a communication operation is performed once, a plurality of communication devices (for example, various boards in a 3U chassis) are often required to cooperate with each other. The boards of different types that need to be matched may not be in the same chassis, and may be distributed in three or four chassis, and at this time, an efficient and stable communication cascade scheme between 3U chassis is necessary. U is a Unit indicating the external size of a server, is an abbreviation of Unit, and the detailed size is determined by the American Electronic Industry Association (EIA), which is an industry group. Height 1 u=1.75 inches= 4.445cm; width 19 inches = 4.826cm,3U is a multiple of 1U. With more and more usage scenarios, more communication function boards will be put into 3U chassis for use.
The existing Serial communication BUS (STBUS) communication scheme in the 3U chassis is only suitable for communication between boards in a single chassis, but is difficult to achieve when multiple chassis need to communicate with each other in real time.
Disclosure of Invention
The invention aims to provide an STBUS cascade communication method and a communication system, which can realize the data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases.
The first aspect of the present invention provides an STBUS cascade communication method, applied to an STBUS cascade communication system, where the STBUS cascade communication system includes at least two 3U chassis, where each 3U chassis includes at least one functional board card through STBUS cascade between the 3U chassis, and the method includes:
when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, obtaining a board card mark of the target function board card;
judging whether an end machine exists in the target 3U machine box according to the board card mark;
if the target 3U chassis has an end machine, transmitting data according to clock synchronization information generated by the target 3U chassis;
and if the target 3U chassis does not have an end machine, transmitting data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine.
Further, the method further comprises the following steps:
acquiring an input clock of external input;
generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
according to the STBUS clock and the synchronous signal, generating clock synchronous information and sending the clock synchronous information to the STBUS.
Further, obtaining a board mark of the target function board includes:
the function board card, which can detect clock synchronization information through the STBUS bus, in the target 3U chassis is used as a target function board card, so that the target function board card sends data and board card marks to corresponding STBUS data lines;
and acquiring the board card mark of the target function board card through the STBUS data line.
Further, the sending data according to the clock synchronization information generated by the target 3U chassis includes:
obtaining an STBUS clock according to clock synchronization information generated by the target 3U chassis;
sampling data on an STBUS data line according to an STBUS clock to obtain sampling data;
the sampled data is retransmitted to the STBUS data line according to a preset time slot allocation protocol.
Further, the sending data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis includes:
receiving clock synchronization information of an STBUS cascade chassis through a target 3U chassis, wherein the STBUS cascade chassis is a 3U chassis with an end machine;
obtaining an STBUS clock according to clock synchronization information of the STBUS cascade cabinet;
sampling data on an STBUS data line according to an STBUS clock to obtain sampling data;
the sampled data is retransmitted to the STBUS data line according to a preset time slot allocation protocol.
Further, each 3U chassis comprises at least two sets of STBUS buses,
the method further comprises the steps of:
a functional board card in the target 3U chassis detects whether a preset continuous number of time slots exist on a data line of a first set of STBUS bus and has detection signals;
if a preset continuous number of time slots exist and have detection signals, determining that the first set of STBUS bus is normal;
if the preset continuous number of time slots do not exist and the detection signal exists, determining that the first set of STBUS bus is abnormal, and switching the first set of STBUS bus into any set of STBUS bus;
when the first set of STBUS buses returns to normal, any one set of STBUS buses is switched back to the first set of STBUS buses.
A second aspect of the present invention provides an STBUS cascade communication system comprising:
at least two 3U cases, wherein the 3U cases are cascaded through STBUS, and each 3U case comprises at least one functional board card and an FPGA board;
the FPGA board is used for acquiring a board card mark of the target function board card when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus;
the FPGA board is also used for judging whether the target 3U case has an end machine according to the board mark;
the FPGA board is also used for sending data according to clock synchronization information generated by the target 3U machine case if the target 3U machine case has an end machine;
and the FPGA board is also used for sending data according to the clock synchronization information of the STBUS cascade case received by the target 3U case if the target 3U case does not exist, and the STBUS cascade case is the 3U case with the end machine.
Further, the method comprises the steps of,
the FPGA board is also used for acquiring an input clock input from the outside;
the FPGA board is also used for generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
and the FPGA board is also used for generating clock synchronization information according to the STBUS clock and the synchronization signal and sending the clock synchronization information to the STBUS.
Further, the method comprises the steps of,
the FPGA board is also used for taking a functional board card in the target 3U chassis, which can detect clock synchronization information through the STBUS bus, as a target functional board card, so that the target functional board card sends data and board card marks to corresponding STBUS data lines;
the FPGA board is also used for acquiring the board mark of the target functional board through the STBUS data line.
Further, the method comprises the steps of,
the FPGA board is also used for obtaining an STBUS clock according to clock synchronization information generated by the target 3U chassis, sampling data on the STBUS data line according to the STBUS clock to obtain sampling data, and retransmitting the sampling data to the STBUS data line according to a preset time slot allocation protocol;
or alternatively, the first and second heat exchangers may be,
the FPGA board is further used for receiving clock synchronization information of the STBUS cascade machine box through the target 3U machine box, the STBUS cascade machine box is a 3U machine box with an end machine, an STBUS clock is obtained according to the clock synchronization information of the STBUS cascade machine box, data on an STBUS data line are sampled according to the STBUS clock, sampled data are obtained, and the sampled data are retransmitted to the STBUS data line according to a preset time slot allocation protocol.
Therefore, in the STBUS cascade communication method, when the target function board card of the target 3U chassis detects clock synchronization information, the board card mark of the target function board card is obtained, whether the target 3U chassis has an end machine or not is judged according to the board card mark, and if the target 3U chassis has the end machine, data is sent according to the clock synchronization information generated by the target 3U chassis; and if the target 3U chassis does not have an end machine, transmitting data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine. Compared with the prior art, the method can realize the data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of one embodiment of an STBUS cascade communication method provided by the present invention;
fig. 2 is a schematic structural diagram of an embodiment of the STBUS cascade communication system provided by the present invention.
Detailed Description
The application discloses an STBUS cascade communication method and a communication system, which can realize data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases.
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In addition, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the technical solutions, and when the technical solutions are contradictory or cannot be implemented, the combination of the technical solutions should be considered as not existing, and not falling within the scope of protection claimed by the present invention.
Referring to fig. 1, an embodiment of the present invention provides an STBUS cascade communication method, including:
101. when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, obtaining a board card mark of the target function board card;
in this embodiment, the STBUS cascade communication system includes at least two 3U chassis, where each 3U chassis includes at least one functional board card through STBUS cascade connection between 3U chassis, and each functional board card is connected to a FPGA (Field Programmable Gate Array) board, and the FPGA is a product further developed on the basis of programmable devices such as PAL and GAL. The programmable device is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), which not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. Taking 13 function board card slots as an example, each interface and function of the FPGA are shown in table 1 below. Typically, the STBUS bus rate is 8.192Mbps, the frame rate is 8K, 128 slots per frame, and 8 bits of data are transmitted per slot.
Table 1 FPGA interface and its function
When the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, the FPGA board can acquire the board card mark ID of the target function board card through each st_in interface, and the board card mark uniquely indicates one function board card.
102. Judging whether the target 3U machine box has an end machine according to the board card mark, if so, executing step 103; if not, go to step 104;
in this embodiment, whether the target 3U chassis has an end machine is determined according to the board card mark, and the general detection time is within 30s after the FPGA board begins to work, if the end machine is present, step 103 is executed; if there is no client, go to step 104. The terminal corresponds to the radio stations, and the terminal generally occupies the most time slots to transmit data to the plurality of radio stations, and each radio station occupies a specific time slot to transmit data to the terminal, so that communication between the terminal and each radio station is formed.
103. Transmitting data according to clock synchronization information generated by the target 3U chassis;
in this embodiment, if the target 3U chassis has an end machine, clock synchronization information generated by the target 3U chassis is used as clock and synchronization information of the STBUS, and data is sent by using the clock and synchronization information.
104. And sending data according to the clock synchronization information of the STBUS cascade machine box received by the target 3U machine box, wherein the STBUS cascade machine box is the 3U machine box with the terminal machine.
In this embodiment, if the target 3U chassis does not have an end machine, the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis is used as the clock and synchronization information of the STBUS bus to send data, and the STBUS cascade chassis is the 3U chassis having the end machine.
In the embodiment of the invention, when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, a board card mark of the target function board card is obtained, whether the target 3U chassis has an end machine or not is judged according to the board card mark, and if the target 3U chassis has the end machine, data is sent according to the clock synchronization information generated by the target 3U chassis; and if the target 3U chassis does not have an end machine, transmitting data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine. Compared with the prior art, the method can realize the data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases.
Optionally, in combination with the embodiment shown in fig. 1, some embodiments of the present invention further include:
acquiring an input clock of external input;
generating an STBUS clock and a synchronous signal according to a preset protocol and an input clock;
according to the STBUS clock and the synchronous signal, generating clock synchronous information and sending the clock synchronous information to the STBUS.
In the embodiment of the invention, the interface shown in the table 1 of the FPGA board and the function table thereof are combined to obtain the externally input clock 49.152MHz, the STBUS clock 8.192MHz and the synchronizing signal are generated according to the preset protocol and the input clock, the clock synchronizing information is generated according to the STBUS clock and the synchronizing signal, and the clock synchronizing information is sent to the STBUS bus.
Optionally, in combination with the embodiment shown in fig. 1, in some embodiments of the present invention, obtaining a board card identifier of a target functional board card includes:
the function board card, which can detect clock synchronization information through the STBUS bus, in the target 3U chassis is used as a target function board card, so that the target function board card sends data and board card marks to corresponding STBUS data lines;
and acquiring the board card mark of the target function board card through the STBUS data line.
In the embodiment of the invention, a functional board card, in which clock synchronization information can be detected through an STBUS (Standard bus), in a target 3U chassis is taken as a target functional board card, namely the target functional board card can be an end machine or a radio station, when the target functional board card detects the clock synchronization information of the STBUS bus, data to be transmitted and board card marks of the target functional board card are transmitted to corresponding STBUS data lines, and an FPGA board acquires the board card marks of the target functional board card through the STBUS data lines.
Optionally, in combination with the embodiment shown in fig. 1, in some embodiments of the present invention, sending data according to clock synchronization information generated by the target 3U chassis includes:
obtaining an STBUS clock according to clock synchronization information generated by the target 3U chassis;
sampling data on an STBUS data line according to an STBUS clock to obtain sampling data;
the sampled data is retransmitted to the STBUS data line according to a preset time slot allocation protocol.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, wherein the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for synchronizing data transmission, so when an end machine exists in a target 3U machine box, the STBUS clock is obtained according to the clock synchronization information generated by the target 3U machine box, and data on an STBUS data line is sampled according to the STBUS clock to obtain sampled data; the sampled data is retransmitted to the STBUS data line according to a preset time slot allocation protocol.
Optionally, in combination with the embodiment shown in fig. 1, in some embodiments of the present invention, sending data according to clock synchronization information of the STBUS cascade chassis received by the target 3U chassis includes:
receiving clock synchronization information of an STBUS cascade chassis through a target 3U chassis, wherein the STBUS cascade chassis is a 3U chassis with an end machine;
obtaining an STBUS clock according to clock synchronization information of the STBUS cascade cabinet;
sampling data on an STBUS data line according to an STBUS clock to obtain sampling data;
the sampled data is retransmitted to the STBUS data line according to a preset time slot allocation protocol.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for synchronizing data transmission, so when an end machine does not exist in a target 3U machine box, the clock synchronization information of an STBUS cascade machine box is received through the target 3U machine box, the STBUS cascade machine box is the 3U machine box with the end machine, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade machine box, the data on the STBUS data line is sampled according to the STBUS clock, sampling data is obtained, and the sampling data is resent to the STBUS data line according to a preset time slot distribution protocol.
Alternatively, in combination with the above embodiments, in some embodiments of the present invention, each 3U chassis includes at least two sets of STBUS buses therein,
the method further comprises the steps of:
a functional board card in the target 3U chassis detects whether a preset continuous number of time slots exist on a data line of a first set of STBUS bus and has detection signals;
if a preset continuous number of time slots exist and have detection signals, determining that the first set of STBUS bus is normal;
if the preset continuous number of time slots do not exist and the detection signal exists, determining that the first set of STBUS bus is abnormal, and switching the first set of STBUS bus into any set of STBUS bus;
when the first set of STBUS buses returns to normal, any one set of STBUS buses is switched back to the first set of STBUS buses.
In the embodiment of the invention, the STBUS buses in the 3U chassis have a redundancy function, and comprise at least two sets of STBUS buses, each function board card detects the 126 th time slot on the data line of the first set of STBUS buses, detects 0xAA on the time slot for 3 times continuously, and the buses are normal, if the 0xAA is not detected for 3 times continuously, the buses are abnormal, so that the second set of STBUS is used, the first set of STBUS is detected simultaneously, and if the 0xAA is detected on the time slot for 3 times continuously, the first set of STBUS is switched back to be used.
Referring to fig. 2, an embodiment of the present invention provides an STBUS cascade communication system, including:
at least two 3U cases 201,3U are cascaded through STBUS between cases 201, and each 3U case 201 comprises at least one functional board card 202 and an FPGA board 203;
the FPGA board 203 is configured to obtain a board mark of the target functional board 202 when the target functional board 202 of the target 3U chassis 201 detects clock synchronization information through the STBUS bus;
the FPGA board 203 is further configured to determine whether the target 3U chassis 201 has an end machine according to the board card label;
the FPGA board 203 is further configured to send data according to clock synchronization information generated by the target 3U chassis 201 if the target 3U chassis 201 has an end machine;
the FPGA board 203 is further configured to send data according to clock synchronization information of the STBUS cascade chassis received by the target 3U chassis 201 if the target 3U chassis 201 does not have an end chassis, where the STBUS cascade chassis is the 3U chassis 201 having an end chassis.
In the embodiment of the invention, when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus, the FPGA board 203 acquires the board card mark of the target function board card, judges whether the target 3U chassis has an end machine according to the board card mark, and if the target 3U chassis has the end machine, sends data according to the clock synchronization information generated by the target 3U chassis; and if the target 3U chassis does not have an end machine, transmitting data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine. Compared with the prior art, the method can realize the data transmission interaction capability and instantaneity of STBUS cascade communication among a plurality of cases.
It should be noted that, in fig. 2, only 2 3U cases are shown, in practical application, taking cascading of 4 3U cases as an example, each 3U case has cascading input and cascading output, for example, cascading output of No. 1 3U case is connected to cascading input of No. 2 3U case, cascading output of No. 2 3U case is connected to cascading input of No. 3U case, cascading output of No. 3U case is connected to cascading input of No. 4 3U case, cascading output of No. 4 3U case is connected to cascading input of No. 1 3U case, so as to form a cascading closed loop.
Alternatively, in connection with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is further configured to obtain an input clock that is input externally;
the FPGA board 203 is further configured to generate an STBUS clock and a synchronization signal according to a preset protocol and an input clock;
the FPGA board 203 is further configured to generate clock synchronization information according to the STBUS clock and the synchronization signal, and send the clock synchronization information to the STBUS.
In the embodiment of the invention, the interface shown in the table 1 of the FPGA board and the function table thereof are combined to obtain the externally input clock 49.152MHz, the STBUS clock 8.192MHz and the synchronizing signal are generated according to the preset protocol and the input clock, the clock synchronizing information is generated according to the STBUS clock and the synchronizing signal, and the clock synchronizing information is sent to the STBUS bus.
Alternatively, in connection with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is further configured to use a functional board card in the target 3U chassis, where clock synchronization information can be detected through the STBUS, as a target functional board card, so that the target functional board card sends data and a board card identifier to a corresponding STBUS data line;
the FPGA board 203 is further configured to obtain a board card identifier of the target functional board card through the STBUS data line.
In the embodiment of the invention, a functional board card, in which clock synchronization information can be detected through an STBUS (Standard bus), in a target 3U chassis is taken as a target functional board card, namely the target functional board card can be an end machine or a radio station, when the target functional board card detects the clock synchronization information of the STBUS bus, data to be transmitted and board card marks of the target functional board card are transmitted to corresponding STBUS data lines, and an FPGA board acquires the board card marks of the target functional board card through the STBUS data lines.
Alternatively, in connection with the embodiment shown in fig. 2, in some embodiments of the invention,
the FPGA board 203 is further configured to obtain an STBUS clock according to clock synchronization information generated by the target 3U chassis, sample data on the STBUS data line according to the STBUS clock, obtain sampled data, and retransmit the sampled data to the STBUS data line according to a preset timeslot allocation protocol;
or alternatively, the first and second heat exchangers may be,
the FPGA board 203 is further configured to receive clock synchronization information of an STBUS cascade chassis through the target 3U chassis, where the STBUS cascade chassis is a 3U chassis with an end machine, obtain an STBUS clock according to the clock synchronization information of the STBUS cascade chassis, sample data on an STBUS data line according to the STBUS clock, obtain sampled data, and retransmit the sampled data to the STBUS data line according to a preset timeslot allocation protocol.
In the embodiment of the invention, the clock synchronization information comprises an STBUS clock and a synchronization signal, wherein the STBUS clock is used for distributing data transmission time slots, and the synchronization signal is used for synchronizing data transmission, so when an end machine exists in a target 3U machine box, the STBUS clock is obtained according to the clock synchronization information generated by the target 3U machine box, and data on an STBUS data line is sampled according to the STBUS clock to obtain sampled data; resending the sampled data to the STBUS data line according to a preset time slot allocation protocol; or the clock synchronization information comprises an STBUS clock and a synchronization signal, the STBUS clock is used for distributing data transmission time slots, the synchronization signal is used for synchronizing data transmission, therefore, when an end machine does not exist in the target 3U machine box, the clock synchronization information of the STBUS cascade machine box is received through the target 3U machine box, the STBUS cascade machine box is the 3U machine box with the end machine, the STBUS clock is obtained according to the clock synchronization information of the STBUS cascade machine box, data on the STBUS data line are sampled according to the STBUS clock, sampled data are obtained, and the sampled data are resent to the STBUS data line according to a preset time slot distribution protocol.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A method of STBUS cascade communication, applied to an STBUS cascade communication system, the STBUS cascade communication system including at least two 3U chassis, the 3U chassis being cascaded by an STBUS, each 3U chassis including at least one function board card, the method comprising:
when a target function board card of a target 3U chassis detects clock synchronization information through an STBUS bus, obtaining a board card mark of the target function board card;
judging whether an end machine exists in the target 3U machine box according to the board card mark;
if the target 3U chassis has an end machine, transmitting data according to clock synchronization information generated by the target 3U chassis;
if the target 3U chassis does not have an end machine, sending data according to clock synchronization information of the STBUS cascade chassis received by the target 3U chassis, wherein the STBUS cascade chassis is the 3U chassis with the end machine;
the STBUS cascade communication method further comprises the following steps:
acquiring an input clock of external input;
generating an STBUS clock and a synchronous signal according to a preset protocol and the input clock;
generating clock synchronization information according to the STBUS clock and the synchronization signal, and sending the clock synchronization information to an STBUS;
correspondingly, the obtaining the board card mark of the target function board card comprises the following steps:
the functional board card, which can detect the clock synchronization information through the STBUS in the target 3U chassis, is used as a target functional board card, so that the target functional board card sends data and board card marks to corresponding STBUS data lines;
and acquiring the board card mark of the target function board card through the STBUS data line.
2. The method of claim 1, wherein the sending data according to the clock synchronization information generated by the target 3U chassis comprises:
obtaining an STBUS clock according to clock synchronization information generated by the target 3U chassis;
sampling data on the STBUS data line according to the STBUS clock to obtain sampling data;
and retransmitting the sampled data to the STBUS data line according to a preset time slot allocation protocol.
3. The method according to claim 1, wherein the sending data according to the clock synchronization information of the STBUS cascade chassis received by the target 3U chassis includes:
receiving clock synchronization information of an STBUS cascade chassis through the target 3U chassis, wherein the STBUS cascade chassis is a 3U chassis with an end machine;
obtaining an STBUS clock according to the clock synchronization information of the STBUS cascade case;
sampling data on the STBUS data line according to the STBUS clock to obtain sampling data;
and retransmitting the sampled data to the STBUS data line according to a preset time slot allocation protocol.
4. A method according to any one of claims 1-3, wherein each 3U chassis includes at least two sets of STBUS buses therein,
the method further comprises the steps of:
the function board card in the target 3U chassis detects whether a preset continuous number of time slots exist on the data lines of the first set of STBUS bus and has detection signals;
if a preset continuous number of time slots have detection signals, determining that the first set of STBUS buses are normal;
if no preset continuous time slots have detection signals, determining that the first set of STBUS bus is abnormal, and switching the first set of STBUS bus into any set of STBUS bus;
and switching any one set of STBUS buses back to the first set of STBUS buses when the first set of STBUS buses are recovered to be normal.
5. An STBUS cascade communication system, comprising:
at least two 3U cases, wherein the 3U cases are cascaded through STBUS, and each 3U case comprises at least one functional board card and an FPGA board;
the FPGA board is used for acquiring a board card mark of the target function board card when the target function board card of the target 3U chassis detects clock synchronization information through the STBUS bus;
the FPGA board is further used for judging whether the target 3U chassis has an end machine according to the board card mark;
the FPGA board is further used for sending data according to clock synchronization information generated by the target 3U machine case if the target 3U machine case has an end machine;
the FPGA board is further used for sending data according to clock synchronization information of the STBUS cascade chassis received by the target 3U chassis if the target 3U chassis does not have an end machine, wherein the STBUS cascade chassis is the 3U chassis with the end machine;
wherein,,
the FPGA board is also used for acquiring an input clock input from the outside;
the FPGA board is also used for generating an STBUS clock and a synchronous signal according to a preset protocol and the input clock;
the FPGA board is also used for generating clock synchronization information according to the STBUS clock and the synchronization signal and sending the clock synchronization information to the STBUS;
the FPGA board is further used for taking a functional board card in the target 3U chassis, wherein the functional board card can detect the clock synchronization information through the STBUS bus, and the functional board card is used as a target functional board card, so that the target functional board card sends data and board card marks to corresponding STBUS data lines;
the FPGA board is also used for acquiring the board card mark of the target function board card through the STBUS data line.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
the FPGA board is further used for obtaining an STBUS clock according to clock synchronization information generated by the target 3U chassis, sampling data on the STBUS data line according to the STBUS clock to obtain sampling data, and retransmitting the sampling data to the STBUS data line according to a preset time slot allocation protocol;
or alternatively, the first and second heat exchangers may be,
the FPGA board is further configured to receive clock synchronization information of an STBUS cascade chassis through the target 3U chassis, where the STBUS cascade chassis is a 3U chassis with an end machine, obtain an STBUS clock according to the clock synchronization information of the STBUS cascade chassis, sample data on the STBUS data line according to the STBUS clock, obtain sampling data, and resend the sampling data to the STBUS data line according to a preset time slot allocation protocol.
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