CN112631989A - Data transmission method among small chips, among chips and among small chips - Google Patents
Data transmission method among small chips, among chips and among small chips Download PDFInfo
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- CN112631989A CN112631989A CN202110249118.8A CN202110249118A CN112631989A CN 112631989 A CN112631989 A CN 112631989A CN 202110249118 A CN202110249118 A CN 202110249118A CN 112631989 A CN112631989 A CN 112631989A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
- G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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Abstract
The invention discloses a method for transmitting data among small chips, among chips and among small chips, wherein the data transmission is carried out in a system comprising a plurality of small chips, wherein the first small chip can be respectively transmitted to other small chips through a plurality of data transmission interfaces; and selecting a specific interface from the plurality of data transmission interfaces according to the information of the target small chip, and transmitting the data information to the target small chip. The architecture design of the invention can achieve flexible expandability on performance, and provides the data transmission method which is accurate and reduces the delay of data transmission.
Description
Technical Field
The invention discloses a method for transmitting data among small chips, among chips and among small chips, and relates to the technical field of chip design.
Background
The chip design technology adopted in the market is mainly that only a single die (die) is provided in a single package, such as NVIDIA previous generation architecture Pascal and current latest architecture graphics (ringing), and the number of transistors (Transistor Count) is increased from 12 billion to as much as 18.6 billion, which is increased by 55%. The wafer area is increased from 471mm 2 to 754mm 2 by 60%, which is not the result of the computational advanced process scaling. This means that some designs cannot benefit from process scaling, but rather expensive processes are used for these designs. On the other hand, since the area of a single wafer is so large, the yield of the product is affected only by an atomic defect or a silk impurity in the wafer manufacturing process. In order to avoid the whole die from being scrapped, a backup design and repair circuit must be added to the die, which will significantly reduce the effective utilization rate of the die.
A conventional wafer and chip designed by using a Parallel network topology (Parallel Networks) is shown in fig. 1, and there are: chain, ring, grid, etc.
In order to effectively use the advantages brought by the advanced process technology, a framework of carrying a plurality of small chips in a single chip package is adopted, so that each small chip can be controlled at a better yield, and further the design complexity of a backup design and a repair circuit and the corresponding silicon area cost are simplified. On the other hand, for designs such as analog circuits that cannot be advantageously implemented in a micro tape manufacturing process, such as a 12 nm or 7 nm process, the designs are concentrated on the chips of the mainstream manufacturing processes, such as a 28 nm or 22 nm process, so as to improve the cost performance of the chips. And the flexibility of the chip is also improved by putting the interface function on the small chip. Furthermore, scalability in performance can also be achieved by packaging different numbers of chiplets for different target markets.
And a framework of several chiplets mounted within a single chip package, wherein one of the most important technologies is a data transmission technology between several chiplets.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the defects of the prior art, the method for transmitting data among small chips, among chips and among small chips is provided, the architecture of a plurality of small chips is loaded in a single chip package, the number of the small chips can be further expanded to reach the scalability (scalability) which is flexible in performance, and the method for transmitting data is accurate and reduces the delay of data transmission.
The invention adopts the following technical scheme for solving the technical problems:
a data transmission method between small chips, between small chips and between chips is used for data transmission in a system comprising a plurality of small chips, wherein a first small chip can be respectively transmitted to a plurality of other small chips through a plurality of data transmission interfaces; and selecting a specific interface from the plurality of data transmission interfaces according to the information of the target small chip, and transmitting the data information to the target small chip.
The method further comprises selecting a specific interface of the multiple data transmission interfaces according to the information of the chiplet where the current data is located, and transmitting the data information to the target chiplet.
As a further preferred scheme, the plurality of data transmission interfaces at least include two different types of data transmission interfaces, including one type of data transmission interface being PCIe
More preferably, the data information is transmitted in a manner that includes obtaining information of the target chiplet using the target chiplet ID; the information of the current data on the chiplet itself is obtained from the ID of the current data on the chiplet itself.
As a further preferred scheme, the data information transmission mode further includes selecting a specific interface of the multiple data transmission interfaces according to the chip ID information, and determining the specific interface according to at least the chip ID of the target chiplet and the chip ID of the chiplet where the current data is located.
As a further preferred scheme, the data information transmission mode further includes selecting a specific interface of the multiple data transmission interfaces according to the chipset ID information, and determining the specific interface according to at least the chipset ID of the target chiplet and the chipset ID of the chiplet where the current data is located.
As a further preferred scheme, the data information transmission mode further includes selecting a specific interface of the multiple data transmission interfaces according to the chip ID information and the chipset ID information, and determining according to at least the chip ID and the chipset ID where the target chiplet is located and the chip ID and the chipset ID where the chiplet where the current data is located.
As a further preferred scheme, the system comprises a plurality of chip sets for mutually transmitting data, each chip set is provided with a plurality of chips, and the plurality of chips mutually transmit data; each chip is provided with a plurality of small chips, and the small chips mutually transmit data; the transmission network in the chip package, the transmission network among the chip packages and the transmission network among the chip groups all present the topological structure of a recursive network; and determining to select a specific interface in the plurality of data transmission interfaces for data transmission at least according to the small chip ID, the chip ID and the chipset ID of the target small chip and the small chip ID, the chip ID and the chipset ID of the current data located small chip.
Compared with the prior art, the invention adopting the technical scheme has the following technical effects: the architecture design of the invention can achieve flexible expandability on performance, and provides the data transmission method which is accurate and reduces the delay of data transmission.
Drawings
FIG. 1 is a schematic diagram illustrating the architecture of the present invention.
FIG. 2 is a schematic diagram showing the positional sequence of the chip set ID, chip ID and chiplet ID in the present invention.
FIG. 3 is a schematic diagram of an algorithm for determining where data is transmitted from the present chiplet.
FIG. 4 is a schematic diagram illustrating various types of data transmission interfaces according to the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The technical scheme of the invention is further explained in detail by combining the attached drawings:
the architecture of the present invention is schematically illustrated in FIG. 1, which shows the bottom layer of 4 chiplets packaged into a single chip, with each 4 chips forming a first-level chipset.
The extension can be continued, and every 4 first-level chipsets L0 can be combined into a second-level chipset L1; every 4 second level chipsets L1 can be grouped into third level chipsets L2, which can be pushed to more level chipsets.
The 4 chiplets in the same chiplet have their chiplet ID location order set as follows:
Four chips in the same first-level chip set are set with the following chip ID position sequence:
The first level chipsets in the same second level chipset L1 have their chipset ID locations set in the order:
chipsets L0: 00, 01, 10, 11.
And so on. The order of chipset ID, chip ID, chiplet ID has a unity positional order as shown in FIG. 2.
Thus addressing a chiplet can be achieved by the following ID concatenation.
{ chipset Ln ID } … { chipset L1 ID } { chipset L0 ID } { chip ID } { chiplet ID };
for convenience of illustration, the following embodiments are described with the system only using chipset L0 at the first level, and 4 chipsets L0. And chipset L0 is shown simplified as a chipset. Thus addressing a chiplet can be achieved by 6 bits as shown in figure 2.
{ chipset ID } { chip ID } { chiplet ID };
and if the situation of the chip set Ln is supported, n > = 1, 2n + 6 bits are needed.
The different types of data transmission interfaces of the present invention will be described in detail with reference to fig. 4.
Fig. 4(a) shows the same chip, four chiplets per chip, and a connection line between chiplets is a chiplet-chiplet data transfer interface Bx.
The connecting line between the chips is another data transmission interface Ax. The Ax data transfer interface may be a standard interface such as PCIe, USB, etc. to increase the adaptability of the connection to the host side. For example, one Ax may be 16-lane PCIe Gen4, such that each Ax has a transmission capability of 16x16 = 256 Gbps. If PCIe Gen4 is collocated with CCIX, then there is a transmission capability of 16x25 = 400 Gbps.
In the above embodiment, fig. 4(a) and fig. 4(b) can see that the two connection lines have substantially the same logical architecture, that is, the topology of the recursive network is implemented.
Further, in FIG. 4(c), the chipsets are interconnected by the connection lines 2002, which is the same logic structure. In one embodiment, the connection line 2002 is the same transmission interface as the connection line 2001, and thus Ax may be used, and in another embodiment, the connection line 2002 is a different transmission interface than the connection line 2001, e.g., the connection line 2002 is Ethernet. In another embodiment, the connection line 2002 represents point-to-point wireless transmission or optical transmission.
In one embodiment of the present invention, the algorithm shown in FIG. 3 is used to determine where the data is being sent from the currently located chiplet.
The following is a description of the chipset L0, which may be further extended to the chipset Ln due to the recursive nature of the algorithm itself.
First, it is determined whether the chipset ID of the currently located chiplet is the same as the chipset ID of the target chiplet.
If the chipset IDs are the same, it is further determined whether the chip ID of the previous chiplet is the same as the chip ID of the target chiplet.
If the current data is the same as the target chiplet ID, further determining whether the chiplet ID of the chiplet in which the current data is located is the same as the chiplet ID of the target chiplet.
If the data is still the same, the data is transmitted to the specified address of the current chiplet.
If the chip group ID and the chip ID of the small chip where the current data are located are the same as those of the target small chip, but the chip IDs of the target small chip and the small chip where the current data are located are different, the small chip where the current data are located and the target small chip are already in the same chip, and at the moment, the data are transmitted to the target small chip in the ID direction of the target small chip through the Bx Link.
After the data is transferred to the next chiplet, the algorithm shown in figure 3 is executed again.
If the chip group ID of the target chiplet is the same as the chipset ID of the chiplet where the current data is located, and the chip ID of the target chiplet is different from the chip ID of the chiplet where the current data is located, but the chip ID of the target chiplet is the same as the chiplet ID of the chiplet where the current data is located, then the data is transmitted to the chiplet in the next chiplet through the Ax Link, and after the data is transmitted to the next chiplet, the algorithm shown in FIG. 3 is executed again.
If the chip group ID of the target small chip is the same as the chip group ID of the small chip where the current data is located, but the chip ID of the target small chip is different from the chip ID of the small chip where the current data is located, the data is transmitted to the next small chip in the ID direction of the target chip through the Bx Link. After the data is transferred to the next chiplet, the algorithm shown in figure 3 is executed again.
If the chip group ID of the small chip where the current data is located is different from the chip group ID of the target small chip, whether the chip group ID of the target small chip is the same as the chip group ID of the small chip where the current data is located is further confirmed, and if the chip group ID of the target small chip is the same as the chip group ID of the small chip where the current data is located, the data is firstly transmitted to the small chip in the next chip through the Ax Link. After the data is transferred to the next chiplet, the algorithm shown in figure 3 is executed again.
If not, the data is transmitted to the next small chip in the ID direction of the target chip group by the Bx Link. Wait for the data to be transferred to the next chiplet and again execute the algorithm shown in figure 3.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention. Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method for transmitting data among small chips, among chips and among small chips is characterized in that: performing data transfer in a system comprising a plurality of chiplets, wherein a first chiplet can be transferred to another plurality of chiplets through a plurality of data transfer interfaces, respectively;
and selecting a specific interface from the plurality of data transmission interfaces according to the information of the target small chip, and transmitting the data information to the target small chip.
2. The method of claim 1 for inter-chiplet, inter-chip, and inter-chiplet-to-chip data transmission, wherein: the method further comprises selecting a specific interface of the multiple data transmission interfaces according to the information of the chiplet where the current data is located, and transmitting the data information to the target chiplet.
3. The method of claim 2, wherein the method comprises the steps of: the data information is transmitted in a manner that the information of the target chiplet is obtained by the target chiplet ID; the information of the current data on the chiplet itself is obtained from the ID of the current data on the chiplet itself.
4. The method of claim 1 for inter-chiplet, inter-chip, and inter-chiplet-to-chip data transmission, wherein: the plurality of data transmission interfaces at least comprise two different types of data transmission interfaces.
5. The method of claim 4 for inter-chiplet, inter-chip, and inter-chiplet-to-chip data transmission, wherein: one of the data transmission interfaces is PCIe.
6. The method of claim 3, wherein the method comprises the steps of: the data information transmission mode further comprises selecting a specific interface of the data transmission interfaces according to the chip ID information, and determining according to at least the chip ID of the target small chip and the chip ID of the small chip where the current data is located.
7. The method of claim 3, wherein the method comprises the steps of: the data information transmission mode further comprises selecting a specific interface of the data transmission interfaces according to the chip set ID information, and determining according to at least the chip set ID of the target small chip and the chip set ID of the small chip where the current data is located.
8. The method of claim 3, wherein the method comprises the steps of: the data information transmission mode further comprises selecting a specific interface of the data transmission interfaces according to the chip ID information and the chip set ID information, and determining according to the chip ID and the chip set ID of at least the target small chip and the chip ID and the chip set ID of the small chip where the current data is located.
9. The method of claim 3, wherein the method comprises the steps of: the system comprises a plurality of chip groups for transmitting data with each other, wherein each chip group is provided with a plurality of chips for transmitting data with each other;
each chip is provided with a plurality of small chips, and the small chips mutually transmit data;
the transmission network in the chip package, the transmission network among the chip packages and the transmission network among the chip groups all present the topological structure of a recursive network;
and determining to select a specific interface in the plurality of data transmission interfaces for data transmission at least according to the small chip ID, the chip ID and the chipset ID of the target small chip and the small chip ID, the chip ID and the chipset ID of the current data located small chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110249118.8A CN112631989A (en) | 2021-03-08 | 2021-03-08 | Data transmission method among small chips, among chips and among small chips |
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| CN202110249118.8A CN112631989A (en) | 2021-03-08 | 2021-03-08 | Data transmission method among small chips, among chips and among small chips |
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| CN112631989A true CN112631989A (en) | 2021-04-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453609A (en) * | 2023-10-18 | 2024-01-26 | 原粒(北京)半导体技术有限公司 | Multi-kernel software program configuration method and device, electronic equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691326A (en) * | 2004-04-13 | 2005-11-02 | 太阳微系统公司 | Method and apparatus involving capacitively coupled communication within a stack of laminated chips |
| CN105608490A (en) * | 2015-07-29 | 2016-05-25 | 上海磁宇信息科技有限公司 | Cellular array computing system and communication method thereof |
| CN107968756A (en) * | 2012-10-22 | 2018-04-27 | 英特尔公司 | High-performance interconnection link layer |
| CN111683014A (en) * | 2020-05-26 | 2020-09-18 | 中国人民解放军国防科技大学 | Routing path tracking method and system of high-speed interconnection network |
-
2021
- 2021-03-08 CN CN202110249118.8A patent/CN112631989A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691326A (en) * | 2004-04-13 | 2005-11-02 | 太阳微系统公司 | Method and apparatus involving capacitively coupled communication within a stack of laminated chips |
| CN107968756A (en) * | 2012-10-22 | 2018-04-27 | 英特尔公司 | High-performance interconnection link layer |
| CN105608490A (en) * | 2015-07-29 | 2016-05-25 | 上海磁宇信息科技有限公司 | Cellular array computing system and communication method thereof |
| CN111683014A (en) * | 2020-05-26 | 2020-09-18 | 中国人民解放军国防科技大学 | Routing path tracking method and system of high-speed interconnection network |
Non-Patent Citations (1)
| Title |
|---|
| 胡森森: "《多核处理器缓存优化关键问题研究》", 31 December 2019 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117453609A (en) * | 2023-10-18 | 2024-01-26 | 原粒(北京)半导体技术有限公司 | Multi-kernel software program configuration method and device, electronic equipment and storage medium |
| CN117453609B (en) * | 2023-10-18 | 2024-06-07 | 原粒(北京)半导体技术有限公司 | Multi-kernel software program configuration method and device, electronic equipment and storage medium |
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