CN1126260C - Resistor string D/A converter with pulse width modulation output - Google Patents

Resistor string D/A converter with pulse width modulation output Download PDF

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CN1126260C
CN1126260C CN 01102272 CN01102272A CN1126260C CN 1126260 C CN1126260 C CN 1126260C CN 01102272 CN01102272 CN 01102272 CN 01102272 A CN01102272 A CN 01102272A CN 1126260 C CN1126260 C CN 1126260C
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resistor string
pulse width
data
analog converter
control signal
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CN 01102272
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CN1367583A (en
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谢进益
陈一修
林春安
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盛群半导体股份有限公司
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Abstract

本发明涉及一种具有脉冲宽度调制输出的电阻串数字模拟转换器,使输入的一资料的一尾端资料收敛于一中间准位,包括:一资料解码器,用以输入该资料,并解得一高位元控制信号及一低位元控制信号;一第一电阻串,由奇数个电阻串接而成,并根据该高位元控制信号的控制而选择其中一指定电阻;一第二电阻串,由偶数位电阻串接而成,跨接于该指定电阻上,并受该低位元控制信号的控制而输出一取样电位,根据该尾端资料,该取样电位收敛于中间准位;以及一取样电路,根据该取样信号并配合一锯齿波,输出一对应的脉冲宽度信号。 The present invention relates to a resistor string digital-analog converter having a pulse width modulated output, a data input so that the trailing end of a data converges to an intermediate level, comprising: a data decoder for the input data, and the solution have a high bit and a low bit control signal a control signal; a first resistor string, an odd number of resistors connected in series together, and wherein a selected resistance based on the specified upper element control signal; a second resistor string, by a series resistor made even bit, designated connected across the resistor, and by the least significant bits of the control signal voltage to output a sample, based on the trailing end of the information, the sampled voltage converges to the intermediate level; and a sample circuit, and based on the sampling signal with a sawtooth wave, a pulse width signal output corresponding to the.

Description

具有脉冲宽度调制输出的电阻串数字模拟转换器 A pulse width modulated output resistor string digital-analog converter

技术领域 FIELD

本发明涉及一种电阻串(R-string)数字模拟转换器,特别是涉及一种具有脉冲宽度调制输出的电阻串数字模拟转换器。 The present invention relates to a resistor string (R-string) digital to analog converter, and more particularly to a resistor string digital-analog converter having a pulse width modulated output.

数字模拟转换器(DAC)的应用相当广泛,尤其在语音处理方面,更是不可获缺的主要元件。 Digital to analog converter (DAC) of the wide range of applications, especially in speech processing, the main element is not eligible missing. 现有的数字模拟转换器有利用多电阻串(Multiple R-String)的方式来实现。 Conventional digital-analog converter has multiple ways to implement the use of the resistor string (Multiple R-String) a. 如图1所示,电阻串有二组RS1及RS2,输入的数位资料可分为高位元控制信号SH及低位元控制信号SL。 1, there are two sets of resistor string RS1 and RS2, the input digital data can be divided into most significant bits and least significant bits the control signal SH control signal SL. 高位元控制信号SH用来控制电阻串RS1,低位元控制信号SL用来控制电阻串RS2。 High bit control signal SH for controlling the resistor strings RS1, lower bit control signal SL for controlling the resistor string RS2. 输出电位Vout是由RS1及RS2二个电阻串来决定,当开关SW11及SW12导通(ON)时,选择到电阻串RS1里的R11,而SW22导通时,则选择到电阻串RS2里的R21,如此一来,即输出一最高的电位,即Vref。 The output potential Vout is determined by the two resistor strings RS1 and RS2, when the switches SW11 and SW12 is turned on (the ON), the selection of the resistor string RS1 in R11, while SW22 is turned on, to select in the resistor string RS2 R21, result, i.e., a maximum output voltage, i.e., Vref. 同理,若欲输出其他电位,亦可由开关组SW1及SW2的切换,来达到目的。 Similarly, the other output potential Ruoyu, or by the switch SW1 and the switch SW2 is set to achieve the purpose.

在语音处理时,尾音通常控制在一数位数值的中间值,例如以八位元为例,尾音的值为80H,而在收敛尾音时,通常数值是在80H上下漂动,例如可能一会儿跳81H,一会儿又跳到7FH,直到收敛结束时才真正停在80H。 When speech processing, a tail is typically controlled in an intermediate digit numerical value, for example, in octets, for example, a value of 80H tail, tail and in the convergence, the value is usually wander up and down in the 80H, 81H-hop moment may e.g. , while they jump 7FH, only until the end of real convergence stopped at 80H. 然而,吾人发现,7FH其高位元控制信号为7,二进位为0111,但80H的高位元控制信号为8,二进位为1000,二者在控制时会分别选到不同的电阻,也因此,在收敛时,尾音的效果会在0111及1000所选的不同的电阻上跳动,而造成声音品质上的瑕玼。 However, it found, 7FH its high bit control signal 7, binary 0111, but 80H of high bit control signal 8, binary 1000, both in the control will be selected from each to a different resistance, and therefore, when convergence, the effect will be on the tail of different resistance 0111 and 1000 selected the beating, causing flaw Ci on sound quality. 若收尾音时,能在相同的电阻(高位元电阻串)上来收敛,则可达到最佳的收敛效果。 If the ending sound, can converge onto the same resistance (high bit resistor string), you can achieve the best convergence results.

另外,PWM可用在语音处理上,然而PWM一般是采用过取样(oversampling)的方式,以8k语音取样而言,如果要表达到音质可接受的范围,至少要4倍频,这是指1位元而言,如果是六位元,工作频率就需64*4*8k=2M Hz,如此解析度提高,工作频率也必须拉高,使设计难度增加,进而造成设计上的成本提高。 Further, PWM available on the voice processing, but is generally used PWM mode through sampling (oversampling) to 8k speech samples, if a sound to be expressed to an acceptable range, to at least 4-fold, which refers to a yuan, if a six yuan, the operating frequency would need 64 * 4 * 8k = 2M Hz, so the resolution increase, the operating frequency must be pulled to make the design more difficult, and cause the cost of design is improved.

本发明的目的是由以下技术方案实现的。 Object of the present invention is achieved by the following technical solutions.

本发明提供一种具有脉冲宽度调制的电阻串数字模拟转换器,使输入的一资料的一尾端资料收敛于一中间准位,其特征在于,其包含一转换器及一取样电路,该转换器用以输入该资料,并输出一取样电位,而根据该尾端资料使该取样电位收敛于该中间位准,其中,该转换器包括:一资料解码器,用以输入该资料,并解得一高位元控制信号及一低位元控制信号;一第一电阻串,由奇数个电阻串接而成,并根据该资料解码器所产生的该高位元控制信号的控制,而选择其中一指定电阻;以及一第二电阻串,由偶数位电阻串接而成,跨接于该指定电阻上,并受该资料解码器所产生的该低位元控制信号的控制,而输出该取样电位;该取样电路,是根据该取样信号,输出一对应的脉冲宽度信号,其中该取样电路包含:一锯齿波产生器,用以产生一锯齿波;以及 The present invention provides a resistor string digital-analog converter having a pulse width modulation, so that a data input of a trailing end of the data converges to an intermediate level, characterized in that it comprises a converter and a sampling circuit that converts this information is used for inputting and outputting a sampled voltage, and according to this information so that the trailing end of the sampling voltage converges to the intermediate level, wherein the converter comprises: a data decoder for the input data, and solve for a high bit and a low bit control signal a control signal; a first resistor string, an odd number of resistors connected in series together, and based on the information of the upper element generated by the decoder control signal, selecting one of the specified resistor ; and a second resistor string, the resistor formed by series of an even bit, designated connected across the resistor, and by the lower profile of the metadata generated by the decoder control signal, and outputs the sampled potential; the sample circuit, is according to the sampling signal and outputs a corresponding pulse width signal, wherein the sampling circuit comprises: a sawtooth generator for generating a sawtooth wave; and 比较器,用以比较该锯齿波及该取样电位,而于取样电位高于该锯齿波的电位时,输出一高电位。 A comparator for comparing the sawtooth wave and the electric potential of the sample, while the sampling of the potential higher than the potential of sawtooth, the output of a high voltage.

所述的资料为一语音资料。 The data is a voice data.

所述的尾端资料为该语音资料的尾音。 The tail end of the data for the voice data.

所述的中间准位为该数字模拟转换器的一高电位及一低电位的中间电位。 Intermediate level of the intermediate potential for a high voltage digital to analog converter and a low voltage level.

所述的资料解码器为一N位元数字模拟解码器。 The data decoder is an N-bit digital to analog decoder.

所述的取样电路更包括一与门,电连接于该比较器的输出端,以于该锯齿波的下缘时,防止该取样电路的输出误差。 The sampling circuit further comprises an AND gate, electrically connected to the output of the comparator, to the lower edge of the saw-tooth wave, the error of the sample to prevent the output circuit.

所述的取样电路是输出一方波。 The output of the sampling circuit is a square wave.

所述的方波的宽度与该取样电位的高低成正比。 Width proportional to the level of the sampled potentials according to a square wave.

由以上技术方案可知,本发明与现有技术相比具有明显的优点和积极效果。 Seen from the above technical solutions, the present invention relates to the prior art, and has significant advantages as compared to the positive effects. 本发明脉冲宽度调制的电阻串数字模拟转换器,其以第一电阻串奇数,第二电阻串偶数的结构,可以具体改善语音处理时尾音收敛的问题,使其正确收敛在中间位准,同时利用锯齿波产生器,更可使工作频率不会随着解析度而改变,当然在取样电路里加设一与门,更可防止于锯齿波下缘(falling edge)时防止该取样电路的输出误差动作发生,深具有产业价值及进步性。 When the pulse width modulated present invention, a resistor string digital-analog converter, a first resistor string which is an odd number, an even number of the second resistor string structure can improve the speech processing specific problem tail convergence, the convergence in the middle so that the correct level, at the same time prevent the sampling circuit utilizing a ramp generator, the frequency will not work with more resolution can be varied, of course, provided a sampling circuit with a gate in Riga, but also prevent in edge (falling edge) the output error sawtooth action takes place, has deep industry value and progressive.

请参阅图2所示,其是本发明具有脉冲宽度调制输出的电阻串数字模拟转换器的较佳实施例。 Please refer to FIG. 2, the present invention which is a resistor string digital-analog converter having a pulse width modulated output of the preferred embodiment. 该电阻串数字模拟转换器,其包括:一资料解码器24、一第一电组串(RS1)25、一第二电阻串(RS2)26及一取样电路,可使输入的一语音资料的尾音资料收敛于一高电位及一低电位的中间电位。 The resistor string digital-analog converter, comprising: a data decoder 24, a first electrically string (RS1) 25, a second resistor string (RS2) 26, and a sampling circuit, make a voice data input tail data converge in the middle of a potential high potential and a low potential. 该资料解码器24,用以输入该语音资料,并解得一高位元控制信号及一低位元控制信号,其中该资料解码器24以一N位元数字模拟解码器为佳。 The data decoder 24 for inputting the speech data, and solutions have a high bit and a low bit control signal control signal, wherein the data decoder 24 to an N bit digital to analog decoder preferred. 该第一电阻串(RS1)25,由奇数个电阻串接而成,用以根据该高位元控制信号的控制而选择其中一指定电阻;该第二电阻串(RS2)26,由偶数个电阻串接而成,跨接于该指定电阻上,并受该低位元控制信号的控制而输出一取样电位,而根据该尾音资料,使该取样电位收敛于该中间电位;至于该取样电路,用以根据该取样信号,输出一对应的脉冲宽度信号。 The first resistor string (RS1) 25, an odd number of series resistors formed, for selecting one of the specified high resistor element according to the control of the control signal; a second resistor string (RS2) 26, an even number of resistors concatenation, is connected across the resistor designated, and by the least significant bits of the control signal voltage to output a sample, according to the tail information, so that the sampled voltage converges to the intermediate potential; as the sampling circuit, with in accordance with the sampling signal, and outputs a corresponding pulse width signal.

其中该取样电路更可包括锯齿波产生器21、比较器22、与门23等元件。 Wherein the sampling circuit may further comprise a ramp generator 21, comparator 22, the AND gate 23 and other components. 该锯齿波产生器21,用来产生一频率f2的锯齿波,而该锯齿波的上下限电压是由该第一电阻串(RS1)25所决定的V_H及V_L的值来控制。 The ramp generator 21 for generating a sawtooth frequency f2, and the upper limit value of the voltage of the sawtooth wave is V_H V_L 25 and determined by the first resistor string (RSl) to control. 至于该频率f2基本上大于频率f1的二倍,如果要得到较精准的PWM波形,则需拉高PWM的频率,也就是必须提高锯齿波的频率。 As the frequency f2 is substantially greater than twice the frequency f1, if you want to give a more precise PWM waveform, need pulled PWM frequency, i.e. the frequency of the sawtooth wave must be increased. 该比较器,用以比较该锯齿波及该取样电位,而于取样电位高于该锯齿波的电位时,输出一高电位。 The comparator for comparing the sawtooth wave and the electric potential of the sample, while the sampling of the potential higher than the potential of sawtooth, the output of a high voltage. 该与门(And Gate)23,电连接于该比较器的输出端,用以于该锯齿波的下缘(falling edge)时,防止该取样电路的输出误差。 When the output of the AND gate (And Gate) 23, electrically connected to the comparator for the lower edge of the saw-tooth wave (falling edge), to prevent the output of the sampling circuit error. 该取样电路输出一方波,其宽度与该取样电位的高低成正比。 The sampling circuit output a square wave, with a width proportional to the level of the sampled potential.

当语音资料以频率f1进入数字模拟转换器24时,由输入资料来的A个高位元来决定高位元控制信号H_SWS的值,H_SWS控制所有的第一电阻串(RS1)25中的哪二个开关要打上,如此便可决定第二电阻串(RS2)26的上下限电压,而低位元控制信号L_SWS则决定第二电阻串里的开关,如此所输出的电压便是数字模拟转换器24的取样电压Vs。 24 when the frequency f1 speech data into the digital-analog converter, the input is determined by a high bit data A control signal H_SWS high bit value, all of the control H_SWS first resistor string (RSl) 25 in which two play switch, so the lower limit voltage can be decided on a second resistor string (RS2) 26, and the lower unit control signal L_SWS second resistor string in the switch is determined, so is the output voltage of a digital-analog converter 24 sampling voltage Vs. 而第一电阻串(RS1)25的电阻个数要用奇数,用于语音处理时,才能收敛在中间的位准。 The first resistor string (RSl) to use an odd number of resistor 25, a voice processing, to converge in the middle level.

图3为锯齿波与输出PWM波形的时序图。 FIG 3 is a timing diagram of the sawtooth wave and outputs a PWM waveform. 当输入资料为0...01时,宽度最小,而当输入资料为F...FF时,宽度最大,输入资料为0...00时则没有脉冲输出。 When the input data is 0 ... 01, the minimum width, and when the input data for the F ... FF, the maximum width of the input data is 0 ... no pulse output 00.

本发明的特征在于,第一电阻串(RS1)25由奇数个电阻串联而成,第二电阻串(RS2)26由偶数个电阻串联而成,如此一来,当尾音收敛时(以八位元为例),接近80H的81H、7FH等电位,在解码时,会被解在第一电阻串(RS1)25的同一电阻上,而由第二电阻串(RS2)26的电阻来决定不同的电位,因此解析度在收尾音时即可收敛在中间位准,不会产生不稳的问题。 The present invention is characterized in that the first resistor string (RS1) 25 series resistors made an odd number, a second resistor string (RS2) 26 series resistors formed by an even, Thus, when the tail converged (in eight element as an example), the proximity 80H 81H, 7FH potential, at the time of decoding, will be in the same solution resistance of the first resistor string (RS1) 25, which is determined by the resistance of the second resistor string (RS2) 26 different potential, and therefore the resolution can be converged on the finish in the middle of the sound level, no instability problems.

另外,输入的语音资料经电阻串转换器(R-String DAC)转换为模拟信号经比较器与锯齿波相比较后,即可产生所需的脉冲宽度随资料线性变化,此随输入资料(Data in)变化的脉冲波形即为PWM的波形,而PWM的输出频率是利用锯齿波的频率来控制,所以在数字模拟转换器(DAC)提高解析度时,不会因解析度的提高而使PWM的输出频率升高。 Further, voice data input via a resistor to-serial converter (R-String DAC) converting into an analog signal by the comparator is compared with the sawtooth wave, to produce the desired pulse width varies linearly with the information, input with this data (Data pulse waveform in) is the change in the PWM waveform, and PWM output frequency is controlled by the frequency of the sawtooth wave, so that when the digital-analog converter (DAC) to improve resolution, without the improved resolution due to PWM the output frequency increases.

以上所述,仅是本发明的较佳实施例,并非对本发明作任何形式上的限制,凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。 Above, only the preferred embodiment of the present invention is not limited in the present invention of any form, all according to the technical essence any simple modification of the above embodiment of the present invention is made of embodiments, modifications and equivalents as would fall present aspect of the present invention within the range.

Claims (8)

1.一种具有脉冲宽度调制的电阻串数字模拟转换器,使输入的一资料的一尾端资料收敛于一中间准位,其特征在于,其包含一转换器及一取样电路,该转换器用以输入该资料,并输出一取样电位,而根据该尾端资料使该取样电位收敛于该中间位准,其中,该转换器包括:一资料解码器,用以输入该资料,并解得一高位元控制信号及一低位元控制信号;一第一电阻串,由奇数个电阻串接而成,并根据该资料解码器所产生的该高位元控制信号的控制,而选择其中一指定电阻;以及一第二电阻串,由偶数位电阻串接而成,跨接于该指定电阻上,并受该资料解码器所产生的该低位元控制信号的控制,而输出该取样电位;该取样电路,是根据该取样信号,输出一对应的脉冲宽度信号,其中该取样电路包含:一锯齿波产生器,用以产生一锯齿波;以及一比较器 Resistor string digital-analog converter A having a pulse width modulation, so that a data input of a trailing end of the data converges to an intermediate level, characterized in that it comprises a converter and a sampling circuit, the converter uses in the input data, and outputting a sampled voltage, and according to this information so that the trailing end of the sampling voltage converges to the intermediate level, wherein the converter comprises: a data decoder for the input data, and to give a solution high bit control signal and a low bit control signal; a first resistor string, an odd number of resistors connected in series together, and a control signal based on the high bit of the data generated by the decoder, wherein selecting a specified resistance; and a second resistor string, the resistor formed by series of an even bit, designated connected across the resistor, and by the lower profile of the metadata generated by the decoder control signal, and outputs the sampled potential; the sampling circuit , based on the sampling signal and outputs a corresponding pulse width signal, wherein the sampling circuit comprises: a sawtooth generator for generating a sawtooth wave; and a comparator 用以比较该锯齿波及该取样电位,而于取样电位高于该锯齿波的电位时,输出一高电位。 For comparing the sawtooth wave and the electric potential of the sample, while the sampling of the potential higher than the potential of sawtooth, the output of a high voltage.
2.根据权利要求1所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的资料为一语音资料。 The resistor string digital-analog converter having a pulse width modulation according to claim 1, wherein the data is a voice data.
3.根据权利要求2所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的尾端资料为该语音资料的尾音。 The resistor string digital-analog converter having a pulse width modulation according to claim 2, wherein the trailing end of the voice data information for the tail.
4.根据权利要求1所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的中间准位为该数字模拟转换器的一高电位及一低电位的中间电位。 The resistor string digital-analog converter having a pulse width modulation according to claim 1, characterized in that the intermediate level of the intermediate potential for a high voltage digital to analog converter and a low voltage level.
5.根据权利要求1所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的资料解码器为一N位元数字模拟解码器。 The resistor string digital-analog converter having a pulse width modulation according to claim 1, wherein said data decoder is an N-bit digital to analog decoder.
6.根据权利要求6所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的取样电路更包括一与门,电连接于该比较器的输出端,以于该锯齿波的下缘时,防止该取样电路的输出误差。 The resistor string digital-analog converter having a pulse width modulation according to claim 6, wherein said sampling circuit further includes an output terminal and a gate electrically connected to the comparator, to the serration in when the lower edge of the waves, to prevent an error output of the sampling circuit.
7.根据权利要求6所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的取样电路是输出一方波。 The resistor string digital-analog converter having a pulse width modulation according to claim 6, characterized in that said sampling circuit is a square-wave output.
8.根据权利要求8所述的具有脉冲宽度调制的电阻串数字模拟转换器,其特征在于,所述的方波的宽度与该取样电位的高低成正比。 The resistor string digital-analog converter having a pulse width modulation according to claim 8, characterized in that the width and the height is proportional to the sampled voltage of the square wave.
CN 01102272 2001-01-20 2001-01-20 Resistor string D/A converter with pulse width modulation output CN1126260C (en)

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