CN112583083A - Decoding implementation method, device and equipment based on Qi wireless charging protocol - Google Patents
Decoding implementation method, device and equipment based on Qi wireless charging protocol Download PDFInfo
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- H—ELECTRICITY
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J50/00—Circuit arrangements or systems for wireless supply or distribution of electric power
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Abstract
The invention discloses a decoding realization method, a device and equipment based on a Qi wireless charging protocol, wherein the method comprises the following steps: receiving the data packet through the first state machine to obtain the receiving state of the first state machine; when the first state machine is detected to be in a preparation state, a signal jumping state is detected through a second state machine; when the second state machine detects the signal jump, controlling the second state machine to enter a first sampling state; acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a preset condition; and analyzing the received data according to the sampling state to finish decoding. In the decoding process, the embodiment of the invention adopts 2 counters, one for counting high level and the other for counting bit length, thus realizing flexible sampling and reducing the bit error rate of sampling.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to a decoding implementation method, a decoding implementation device and decoding implementation equipment based on a Qi wireless charging protocol.
Background
The wireless charging device adopting Qi standard transmits power by means of 2FSK (binary frequency shift keying), and signals received by an energy receiving terminal in a wireless charging system are signals inductively coupled, so that the received signals are not single-frequency sinusoidal signals, but are doped with a large amount of high-frequency noise. In the Qi standard communication protocol, in order to ensure the stability of the transmission energy, a period difference between the carrier frequency Fop and the modulation frequency Fmod is defined, with a maximum value of 282ns and a minimum value of only 30 ns. So the demodulated high and low level lengths of the products of different companies are larger than the actual error. In the decoding method in the prior art, decoding is performed through a software algorithm, so that the development difficulty of software is improved, and a large amount of system resources are occupied when decoding is performed through the software.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
In view of the defects of the prior art, an object of the present invention is to provide a decoding implementation method, apparatus and device based on a Qi wireless charging protocol, and to solve the technical problems that in the prior art, the decoding method is performed by a software algorithm, so as to increase the difficulty in software development, and a large amount of system resources are occupied when the decoding is performed by software.
The technical scheme of the invention is as follows:
a decoding implementation method based on a Qi wireless charging protocol is applied to a data receiving unit, wherein the data receiving unit comprises two state machines which are respectively marked as a first state machine and a second state machine, and the second state machine is provided with a bit counter and a high-level timer; the method comprises the following steps:
receiving the data packet through the first state machine to obtain the receiving state of the first state machine;
when the first state machine is detected to be in a preparation state, a signal jumping state is detected through a second state machine;
when the second state machine detects the signal jump, controlling the second state machine to enter a first sampling state;
acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a preset condition;
and analyzing the received data according to the sampling state to finish decoding.
Further, the receiving state of the first state machine sequentially includes a preparation state, a preamble receiving state, a header start bit receiving state, a data header receiving state, a data packet receiving state, and a stop bit receiving state.
Further preferably, the receiving the data packet by the first state machine includes:
when the receiving state of the first state machine is in a preparation state, entering a lead code receiving state after detecting signal jumping;
when the preamble is detected to be received completely, entering a start bit receiving state and starting to receive a start bit of the data packet header;
after detecting that the start bit is received completely, entering a data packet header receiving state and starting to receive the data packet header;
after detecting that the data packet header is received completely, entering a data receiving state and starting to receive data;
when the data receiving is detected to be completed, entering a stop bit receiving state and starting to receive the stop bit of the data;
and if the stop bit is detected to be completely received, judging that the receiving of one data packet is completed.
Further preferably, the acquiring data of the high level timer and the bit counter in the sampling state, and when detecting that the high level timer and/or the bit counter satisfy a predetermined condition, jumping to a corresponding sampling state includes:
when detecting that the second state machine is in the first sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling a high level timer to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
Preferably, the acquiring data of the high level timer and the bit counter in the sampling state, and when detecting that the high level timer and/or the bit counter satisfy a predetermined condition, jumping to the corresponding sampling state includes:
when the duration of the high-level timer is greater than a second duration threshold and less than a first duration threshold, and the signal is detected to jump, whether the data reception of the first state machine is finished is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
Further, the acquiring data of the high level timer and the bit counter in the sampling state, and when detecting that the high level timer and/or the bit counter satisfy a predetermined condition, jumping to a corresponding sampling state includes:
when the fact that the bit counter exceeds the bit minimum length and the duration of the high-level timer is smaller than a second duration threshold value is detected, whether the data receiving of the first state machine is completed or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
Further, after the controlling the second state machine to jump to the second sampling state, the method includes:
when the second state machine is in a second bit sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling high level counting to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
Another embodiment of the present invention provides a decoding implementation apparatus based on Qi wireless charging protocol, applied to a data receiving unit, where the data receiving unit includes two state machines, respectively marked as a first state machine and a second state machine, and the second state machine is provided with a bit counter and a high level timer, and the apparatus includes:
the receiving state acquisition module is used for receiving the data packet through the first state machine and acquiring the receiving state of the first state machine;
the signal detection module is used for detecting a signal jumping state through the second state machine when the first state machine is detected to be in a preparation state;
the first sampling control module is used for controlling the second state machine to enter a first sampling state after the second state machine detects the signal jump;
the second sampling control module is used for acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when the high-level timer and/or the bit counter are detected to meet a preset condition;
and the analysis module is used for analyzing the received data according to the sampling state to finish decoding.
Another embodiment of the present invention provides a decoding implementation device based on a Qi wireless charging protocol, the device comprising at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the above-described decoding implementation method based on the Qi wireless charging protocol.
Yet another embodiment of the present invention provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by one or more processors, cause the one or more processors to perform the above-described decoding implementation method based on the Qi wireless charging protocol.
Has the advantages that: in the decoding process, the embodiment of the invention adopts 2 counters, one for counting high level and the other for counting bit length, thus realizing flexible sampling and reducing the bit error rate of sampling.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a flowchart of a preferred embodiment of a decoding implementation method based on a Qi wireless charging protocol according to the present invention;
FIG. 2 is a functional block diagram of a decoding device according to a preferred embodiment of the present invention based on a Qi wireless charging protocol;
fig. 3 is a schematic hardware structure diagram of a decoding implementation device based on the Qi wireless charging protocol according to a preferred embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Embodiments of the present invention will be described below with reference to the accompanying drawings.
The embodiment of the invention provides a decoding implementation method based on a Qi wireless charging protocol. Referring to fig. 1, fig. 1 is a flowchart illustrating a decoding implementation method based on a Qi wireless charging protocol according to a preferred embodiment of the present invention. The decoding implementation method based on the Qi wireless charging protocol is applied to a data receiving unit, wherein the data receiving unit comprises two state machines which are respectively marked as a first state machine and a second state machine, and the second state machine is provided with a bit counter and a high-level timer; as shown in fig. 1, it includes the steps of:
step S100, receiving a data packet through a first state machine to obtain a receiving state of the first state machine;
step S200, when detecting that the first state machine is in a preparation state, detecting a signal jumping state through a second state machine;
step S300, when the second state machine detects the signal jump, controlling the second state machine to enter a first sampling state;
s400, acquiring data of a high-level timer and a bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a preset condition;
and step S500, analyzing the received data according to the sampling state to finish decoding.
In specific implementation, the data receiving unit in the embodiment of the present invention includes two state machines, which are respectively recorded as a first state machine and a second state machine, where the first state machine is used to control the reception of a data packet, and the second state machine is used to sample a bit. The second state machine is provided with a bit counter and a high level timer.
Receiving the data packet through the first state machine to obtain the receiving state of the first state machine; when the first state machine is detected to be in a preparation state, the second state machine detects signal jumping; when the second state machine detects the signal jump, controlling the second state machine to enter a first bit sampling state; the first bit sampling state is a high level sampling state.
Acquiring the states of a high-level timer and a bit counter, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a preset condition; and when the sampling of the second state machine is detected to be finished and the data receiving of the first state machine is detected to be finished, controlling the second state machine to enter a preparation state. And completing the analysis of the data according to the sampling of the high level, and completing the decoding.
The embodiment of the invention adopts hardware for decoding, can improve the decoding speed, does not occupy system resources, and has the decoded bit error rate basically the same as the bit error rate of software decoding. The hardware only decodes the data part, the decoded data is not analyzed, and the analyzed data is processed by software, so that the flexibility is stronger, and the protocol can be conveniently upgraded. In the decoding process, 2 counters are adopted, one is used for timing high level, and the other is used for counting bit length, so that flexible sampling can be realized, and the adopted error rate is reduced.
The hardware partially decodes the data means that the received data is high level and low level, and the high level and the low level are decoded to be changed into data to be put into a FIFO for software reading.
Further, the receiving state of the first state machine sequentially includes a preparation state, a preamble receiving state, a header start bit receiving state, a data header receiving state, a data packet receiving state, and a stop bit receiving state.
In the implementation, the state of receiving a packet is divided into 6 states in total. Respectively an IDLE state (ready state), a PREAMBLE state (receive PREAMBLE), a WAIT _ START state (receive START bit), an REC _ HEAD state (receive header), an REC _ DATA state (receive packet), and an REC _ LAST _ STOP state (STOP bit for receiving the LAST byte DATA).
Further, receiving the data packet by the first state machine includes:
when the receiving state of the first state machine is in a preparation state, entering a lead code receiving state after detecting signal jumping;
when the preamble is detected to be received completely, entering a start bit receiving state and starting to receive a start bit of the data packet header;
after detecting that the start bit is received completely, entering a data packet header receiving state and starting to receive the data packet header;
after detecting that the data packet header is received completely, entering a data receiving state and starting to receive data;
when the data receiving is detected to be completed, entering a stop bit receiving state and starting to receive the stop bit of the data;
and if the stop bit is detected to be completely received, judging that the receiving of one data packet is completed.
In specific implementation, the method STARTs to be in an IDLE state, STARTs to receive a lead code after signal jump, enters a PREAMBLE state, WAITs for receiving first data after the lead code is received, STARTs a START bit of a header, and enters a WAIT _ START state; after the start bit is received, the HEAD of the packet starts to be received, the REC _ HEAD state is entered, after the HEAD of the packet finishes receiving, the DATA starts to be received, the REC _ DATA state is entered, after the LAST DATA finishes receiving, the STOP bit of the LAST DATA starts to be received, the REC _ LAST _ STOP state is entered, the STOP bit of the LAST DATA finishes receiving, one packet finishes receiving, and the IDLE state is entered.
Further, acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a predetermined condition, including:
when detecting that the second state machine is in the first sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling a high level timer to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
In specific implementation, the state is in an IDLE state, and the state enters a W _ H state after signal jump is detected.
In the W _ H state (bit1 sample), the bit counter count starts counting, and if the sample level is high, the high timer cnt _ high also starts counting. When the count of the cnt _ high counter reaches a first time threshold value, wherein the first time threshold value is a preset maximum high level, jumping to an IT _ AH state;
in the IT _ AH (bit0 high) state, if the state of the first state machine is at reception completion, the state jumps to the IDLE state, otherwise IT jumps to the second sampling state, which is called W _ L state. The specific process of the second sampling state is described in detail in the following embodiments.
If the state of the first state machine is in the receiving completion state, the state of the second state machine jumps to the IDLE state.
Further, acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a predetermined condition, including:
when the duration of the high-level timer is greater than a second duration threshold and less than a first duration threshold, and the signal is detected to jump, whether the data reception of the first state machine is finished is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
In specific implementation, the second time threshold is a preset minimum high level time length, so that when the count value of the cnt _ high counter is greater than the minimum high level time length and less than the maximum high level time length, the signal is in a jump state, and the state jumps to an IT _ HL state; the maximum high level duration and the minimum high level duration are set and determined according to protocols and practical application, because different peripheral circuits and the layout of the PCB have influence on the lengths of the high level and the low level, the difference between the demodulated high level and the low level and the Qi protocol requirement is large, and the maximum high level duration and the minimum high level duration are set to be configurable so as to enable the error rate of analysis to be lower.
In the IT _ HL (bit1 high low) state, the state jumps to the IDLE state if the state of the first state machine is at reception completion, otherwise to the first sampling state (W _ H state).
Further, acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a predetermined condition, including:
when the fact that the bit counter exceeds the bit minimum length and the duration of the high-level timer is smaller than a second duration threshold value is detected, whether the data receiving of the first state machine is completed or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
In specific implementation, when the count counter counts for more than the minimum bit length and cnt _ high is less than the minimum high level duration, the state jumps to IT _ AL.
In the IT _ AL (bit0 is low) state, if the state of the first state machine is at reception completion, the state jumps to the IDLE state, otherwise IT jumps to the first sampling state (W _ H state).
Further, after the controlling the second state machine to jump to the second sampling state, the method includes:
when the second state machine is in a second bit sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling high level counting to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
In specific implementation, in the W _ L (bit0 sample) state, the bit counter count starts counting, and if the sample level is high, the high level timer cnt _ high also starts counting. When the count of the cnt _ high counter reaches the maximum high level, jumping to an IT _ AH state;
when the count value of the cnt _ high counter is greater than the minimum high level duration and less than the maximum high level duration, the signal is jumped, and the state is jumped to an IT _ LH state; an IT _ LH state (bit1 low high) state, which jumps to the IDLE state if the state of the first state machine is at reception completion, and jumps to the second sampling state (W _ L state) otherwise.
When the count of the count counter exceeds the minimum bit length and the cnt _ high is less than the minimum high level duration, the state jumps to the IT _ AL state;
if the data receiving state is in the receiving completion state, the state jumps to the IDLE state. The sampling refers to checking whether the receiving line is high level or low level according to the protocol requirement, the decoding refers to analyzing the data packet by sampling the high level and the low level on the line, and the analyzed data is put into FIFO.
The embodiment of the method can show that the invention provides the decoding implementation method based on the Qi wireless charging protocol, the hardware is adopted for decoding, the decoding speed can be improved, the system resources are not occupied, and the error rate of the decoded data is lower than that of the software decoding.
It should be noted that, a certain order does not necessarily exist between the above steps, and those skilled in the art can understand, according to the description of the embodiments of the present invention, that in different embodiments, the above steps may have different execution orders, that is, may be executed in parallel, may also be executed interchangeably, and the like.
Another embodiment of the present invention provides a decoding implementation apparatus based on Qi wireless charging protocol, as shown in fig. 2, the apparatus 1 includes:
a receiving state obtaining module 11, configured to receive the data packet through the first state machine, and obtain a receiving state of the first state machine;
the signal detection module 12 is configured to detect a signal transition state through the second state machine when it is detected that the first state machine is in a ready state;
the first sampling control module 13 is configured to control the second state machine to enter a first sampling state after the second state machine detects a signal jump;
the second sampling control module 14 is configured to acquire data of the high-level timer and the bit counter in a sampling state, and when it is detected that the high-level timer and/or the bit counter meet a predetermined condition, jump to a corresponding sampling state;
and the analysis module 15 is configured to analyze the received data according to the sampling state, and complete decoding.
The specific implementation is shown in the method embodiment, and is not described herein again.
Another embodiment of the present invention provides a decoding implementation device based on Qi wireless charging protocol, as shown in fig. 3, the device 10 includes:
one or more processors 110 and a memory 120, where one processor 110 is illustrated in fig. 3, the processor 110 and the memory 120 may be connected by a bus or other means, and the connection by the bus is illustrated in fig. 3.
The memory 120 is a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions corresponding to the decoding implementation method based on the Qi wireless charging protocol in the embodiment of the present invention. The processor 110 executes various functional applications and data processing of the device 10, i.e. implements the Qi wireless charging protocol based decoding implementation method in the above-described method embodiments, by running non-volatile software programs, instructions and units stored in the memory 120.
The memory 120 may include a storage program area and a storage data area, wherein the storage program area may store an application program required for operating the device, at least one function; the storage data area may store data created according to the use of the device 10, and the like. Further, the memory 120 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 120 optionally includes memory located remotely from processor 110, which may be connected to device 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more units are stored in the memory 120, which when executed by the one or more processors 110, perform the Qi wireless charging protocol based decoding implementation method in any of the method embodiments described above, e.g. perform the method steps S100 to S500 in fig. 1 described above.
Embodiments of the present invention provide a non-transitory computer-readable storage medium storing computer-executable instructions for execution by one or more processors, for example, to perform method steps S100-S500 of fig. 1 described above.
By way of example, non-volatile storage media can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as Synchronous RAM (SRAM), dynamic RAM, (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The disclosed memory components or memory of the operating environment described herein are intended to comprise one or more of these and/or any other suitable types of memory.
Another embodiment of the present invention provides a computer program product comprising a computer program stored on a non-volatile computer readable storage medium, the computer program comprising program instructions which, when executed by a processor, cause the processor to perform the Qi wireless charging protocol based decoding implementation method of the above method embodiment. For example, the method steps S100 to S500 in fig. 1 described above are performed.
The above-described embodiments are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the embodiment.
Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments may be implemented by software plus a general hardware platform, and may also be implemented by hardware. Based on such understanding, the above technical solutions essentially or contributing to the related art can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of the various embodiments or some parts of the embodiments.
Conditional language such as "can," "might," or "may" is generally intended to convey that a particular embodiment can include (yet other embodiments do not include) particular features, elements, and/or operations, among others, unless specifically stated otherwise or otherwise understood within the context as used. Thus, such conditional language is also generally intended to imply that features, elements, and/or operations are in any way required for one or more embodiments or that one or more embodiments must include logic for deciding, with or without input or prompting, whether such features, elements, and/or operations are included or are to be performed in any particular embodiment.
What has been described herein in the specification and drawings includes examples that can provide decoding implementation methods and apparatus based on the Qi wireless charging protocol. It will, of course, not be possible to describe every conceivable combination of components and/or methodologies for purposes of describing the various features of the disclosure, but it can be appreciated that many further combinations and permutations of the disclosed features are possible. It is therefore evident that various modifications can be made to the disclosure without departing from the scope or spirit thereof. In addition, or in the alternative, other embodiments of the disclosure may be apparent from consideration of the specification and drawings and from practice of the disclosure as presented herein. It is intended that the examples set forth in this specification and the drawings be considered in all respects as illustrative and not restrictive. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (10)
1. A decoding implementation method based on a Qi wireless charging protocol is characterized by being applied to a data receiving unit, wherein the data receiving unit comprises two state machines which are respectively marked as a first state machine and a second state machine, and the second state machine is provided with a bit counter and a high level timer; the method comprises the following steps:
receiving the data packet through the first state machine to obtain the receiving state of the first state machine;
when the first state machine is detected to be in a preparation state, a signal jumping state is detected through a second state machine;
when the second state machine detects the signal jump, controlling the second state machine to enter a first sampling state;
acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when detecting that the high-level timer and/or the bit counter meet a preset condition;
and analyzing the received data according to the sampling state to finish decoding.
2. The Qi wireless charging protocol-based decoding implementation method of claim 1, wherein the receiving states of the first state machine sequentially comprise a ready state, a preamble receiving state, a header start bit receiving state, a packet header receiving state, a packet receiving state, and a stop bit receiving state.
3. The Qi wireless charging protocol-based decoding implementation method of claim 2, wherein the receiving the data packet by the first state machine comprises:
when the receiving state of the first state machine is in a preparation state, entering a lead code receiving state after detecting signal jumping;
when the preamble is detected to be received completely, entering a start bit receiving state and starting to receive a start bit of the data packet header;
after detecting that the start bit is received completely, entering a data packet header receiving state and starting to receive the data packet header;
after detecting that the data packet header is received completely, entering a data receiving state and starting to receive data;
when the data receiving is detected to be completed, entering a stop bit receiving state and starting to receive the stop bit of the data;
and if the stop bit is detected to be completely received, judging that the receiving of one data packet is completed.
4. The Qi wireless charging protocol-based decoding implementation method of claim 3, wherein the obtaining data of the high level timer and the bit counter in the sampling state, and jumping to the corresponding sampling state when detecting that the high level timer and/or the bit counter satisfy a predetermined condition comprises:
when detecting that the second state machine is in the first sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling a high level timer to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
5. The Qi wireless charging protocol-based decoding implementation method of claim 3, wherein the obtaining data of the high level timer and the bit counter in the sampling state, and jumping to the corresponding sampling state when detecting that the high level timer and/or the bit counter satisfy a predetermined condition comprises:
when the duration of the high-level timer is greater than a second duration threshold and less than a first duration threshold, and the signal is detected to jump, whether the data reception of the first state machine is finished is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
6. The Qi wireless charging protocol-based decoding implementation method of claim 5, wherein the obtaining data of the high level timer and the bit counter in the sampling state, and jumping to the corresponding sampling state when detecting that the high level timer and/or the bit counter satisfy a predetermined condition comprises:
when the fact that the bit counter exceeds the bit minimum length and the duration of the high-level timer is smaller than a second duration threshold value is detected, whether the data receiving of the first state machine is completed or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to the first sampling state.
7. The Qi wireless charging protocol-based decoding implementation method of claim 4, wherein the controlling the second state machine to jump to the second sampling state comprises:
when the second state machine is in a second bit sampling state, controlling the bit counter to start counting;
when the sampling level is high level, controlling high level counting to start timing;
when the fact that the duration of the high-level timer reaches a first duration threshold value is detected, whether the data of the first state machine are received or not is judged;
if the data reception of the first state machine is finished, controlling the second state machine to jump to a preparation state;
and if the data of the first state machine is not received completely, controlling the second state machine to jump to a second sampling state.
8. The utility model provides a decoding realization device based on Qi wireless charging protocol which characterized in that is applied to data receiving element, data receiving element includes two state machines, marks as first state machine and second state machine respectively, the second state machine is provided with bit counter and high level timer, the device includes:
the receiving state acquisition module is used for receiving the data packet through the first state machine and acquiring the receiving state of the first state machine;
the signal detection module is used for detecting a signal jumping state through the second state machine when the first state machine is detected to be in a preparation state;
the first sampling control module is used for controlling the second state machine to enter a first sampling state after the second state machine detects the signal jump;
the second sampling control module is used for acquiring data of the high-level timer and the bit counter in a sampling state, and jumping to a corresponding sampling state when the high-level timer and/or the bit counter are detected to meet a preset condition;
and the analysis module is used for analyzing the received data according to the sampling state to finish decoding.
9. A decoding implementation device based on a Qi wireless charging protocol, characterized in that the device comprises at least one processor; and the number of the first and second groups,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method for implementing a Qi-based wireless charging protocol decoding of any one of claims 1-7.
10. A non-transitory computer-readable storage medium having stored thereon computer-executable instructions that, when executed by one or more processors, cause the one or more processors to perform the Qi wireless charging protocol based decoding implementation method of any one of claims 1-7.
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