CN112564652A - Trans-impedance amplifier with adjustable input range - Google Patents

Abstract

The present disclosure relates to a transimpedance amplifier with an adjustable input range. A multi-stage transimpedance amplifier (TIA) with an adjustable input linear range is disclosed. The TIA includes: a first stage configured to convert a single-ended current signal from an optical sensor of a receiver signal chain to a single-ended voltage signal; and a second stage configured to convert the single-ended voltage signal provided by the first stage into a differential signal. In such a TIA, the input linear range may be adjusted using a clamp, which may be programmed with an output offset current to prevent overloading of the second stage of the TIA and to maintain a linear transfer function without compression.

Description

Trans-impedance amplifier with adjustable input range

Cross Reference to Related Applications

The present application is related to U.S. patent application No. 62/905,772 entitled "transimpedance amplifier with ADJUSTABLE INPUT RANGE (TRANSIMPEDANCE AMPLIFIER WITH adjust INPUT RANGE)" filed on 25.9.2019, the disclosure of which is hereby incorporated by reference in its entirety.

Technical Field

The present disclosure relates generally to electronic devices and, more particularly, to transimpedance amplifiers.

Background

Light detection and ranging (LIDAR) refers to a measurement method that measures distance to a target object by illuminating the object with light (e.g., with pulses of light (e.g., pulses of laser light)) and measuring the reflected light with an optical sensor, such as an Avalanche Photodiode (APD). The difference in laser return time and wavelength can then be used to determine the distance to the object and/or to make a digital three-dimensional representation of the object. LIDAR systems are used in a variety of situations. For example, LIDAR systems may be used with aircraft, automobiles, binoculars, monoculars, or the like.

A conventional receiver chain of a LIDAR system may include a sequence of optical sensors that receive/detect optical pulses and convert them to electrical current, a transimpedance amplifier (TIA) that converts the current signal from the optical sensors to a voltage signal, and an analog-to-digital converter (ADC) that converts the voltage signal from the TIA to a digital signal for further processing. Some ADCs operate better when the input signals they are supplied to are differential signals. However, optical sensors typically produce current in only one direction, and therefore, the optical sensor output is typically single ended. Accordingly, a LIDAR system may include a circuit configured to convert a single-ended voltage output from a TIA to a differential signal, which may then be provided as an input to an ADC. Such circuitry may be part of an ADC driver, which is an electronic component configured to perform signal conditioning on the ADC. Such circuitry may also be considered a second stage of the TIA (i.e., the first stage converts the current signal from the optical sensor to a single-ended voltage signal, while the second stage converts the single-ended voltage signal to a differential signal).

The ADC driver may be a key factor that enables the ADC to achieve the desired performance. First, the ADC driver (which typically operates at a higher supply voltage than the ADC) should ensure that the maximum output of the driver never exceeds the supply of the ADC to protect the ADC from permanent damage. Second, the ADC driver should adjust its output so as not to overload the ADC. The ADC may be overloaded when the output from the ADC driver exceeds the minimum and maximum voltages within the full scale range of the ADC. High-speed ADCs, such as those used as modern pipelined converters, may also be overloaded if the common-mode voltage of the input signal provided to the ADC does not remain in a narrow band (e.g., less than 100 millivolts (mV)) around the input common-mode voltage of the ADC.

In addition to the danger of overloading the ADC, certain limitations may be exceeded by the TIA in the signal path to the ADC and the input of the single-ended to differential conversion circuit. An overload condition of any of these components of the receiver chain is highly undesirable because it may take a few microseconds or even milliseconds before the receiver recovers from the overload, during which time the receiver may not be able to process the input signal, i.e., the receiver is effectively temporarily disabled. In applications such as LIDAR systems, it may be of absolute importance to temporarily disable the receiver, since this means that the LIDAR system has no knowledge of its surroundings before the receiver recovers from an overload.

Disclosure of Invention

According to one aspect of the present disclosure, a system configured to convert a single-ended current input to a differential voltage output is disclosed, the system comprising: a first amplifier circuit having an output for providing a first amplifier output generated by the first amplifier circuit based on the single-ended current input; an output offset current generation circuit configured to generate an output offset current; a second amplifier circuit having a differential input comprising a first input and a second input and configured to generate the differential voltage output based on: receiving a signal based on the first amplifier output at the first input and a signal based on the output offset current at the second input; and a clamp circuit coupled to the output of the first amplifier circuit and further coupled to a control signal configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on the output offset current.

In accordance with another aspect of the present disclosure, a system configured to convert a single-ended current input to a differential voltage output is disclosed, the system comprising: a first stage configured to receive the single-ended current input and to generate a single-ended output based on the single-ended current input; a clamping circuit configured to generate a clamped single-ended output by clamping the single-ended output when one of the following is true: when the single-ended output exceeds a maximum voltage value, wherein the maximum voltage value is based on an output offset current, or when the single-ended output falls below a minimum voltage value, wherein the minimum voltage value is based on the output offset current; and a second stage configured to: receiving a signal based on the clamped single-ended output as a first input of a differential input of the second stage, receiving a signal based on the output offset current as a second input of the differential input of the second stage, and generating the differential voltage output based on the differential input.

According to yet another aspect of the present disclosure, a system configured to convert a single-ended signal to a differential signal is disclosed, the system comprising: an amplifier; and a clamp circuit, wherein: the amplifier has a differential input and a differential output, a first input of the differential input of the amplifier is configured to receive a signal based on the single-ended signal that has been clamped by the clamping circuit based on a clamping control signal, wherein the clamping control signal is based on an output offset current, a second input of the differential input of the amplifier is configured to receive a signal based on the output offset current, and the amplifier is configured to generate the differential signal based on the signal received at the differential input of the amplifier.

Drawings

To provide a more complete understanding of the present disclosure and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

fig. 1 is a circuit diagram illustrating a LIDAR receiver.

Fig. 2 is a circuit diagram illustrating an exemplary embodiment of a reference voltage source for a LIDAR receiver.

Fig. 3 provides a graphical representation of an exemplary input waveform for amplifier a2 and a graphical representation of an exemplary output waveform for amplifier a2 with I0 set to zero.

Fig. 4 provides a graphical representation of an exemplary input waveform for amplifier a2 and I0 is set to 0.5 x I_LRA graphical representation of an exemplary output waveform of amplifier a 2.

Figure 5 is a circuit diagram illustrating a LIDAR receiver with a multi-stage TIA having an adjustable input range in accordance with some embodiments of the present disclosure.

Figure 6 is a circuit diagram illustrating an exemplary single-ended TIA that may be used within the multi-stage TIA of figure 5, in accordance with some embodiments of the present disclosure.

Fig. 7A and 7B are circuit diagrams of fig. 6 showing examples of operating points for minimum and maximum output swings, respectively.

Figure 8 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with adjustable input range implemented by a voltage controlled high side clamp circuit, in accordance with some embodiments of the present disclosure.

Figure 9 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with adjustable input range implemented by a voltage controlled low side clamp, in accordance with some embodiments of the present disclosure.

Figure 10 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with adjustable input range implemented by a current control high side clamp circuit, in accordance with some embodiments of the present disclosure.

Figure 11 is a circuit diagram illustrating an example of a first stage of a multi-stage TIA with adjustable input range implemented by a current-controlled low-side clamp circuit, according to some embodiments of the present disclosure.

Fig. 12 is a block diagram of an exemplary LIDAR system in which a multi-stage TIA having an adjustable input range may be implemented, in accordance with some embodiments of the present disclosure.

Figure 13 provides a block diagram illustrating an example data processing system that may be configured to implement or control at least part of the processing of received signals using a multi-level TIA having an adjustable input range, in accordance with some embodiments of the present disclosure.

Fig. 14 is an exemplary illustration of a LIDAR system integrated with an automobile, according to some embodiments of the disclosure.

Detailed Description

SUMMARY

There are several innovative aspects to each of the systems, methods, and devices of the present disclosure, no single one of which is solely responsible for all the desirable attributes disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

Some aspects of the present disclosure relate to a multi-level TIA with an adjustable input linear range. An exemplary TIA includes a first stage and a second stage. The first stage is configured to convert a single-ended current input signal to a single-ended output voltage signal. In some embodiments, the single-ended current input signal may be, but is not limited to, a current signal received from an optical sensor of a receiver signal chain of the LIDAR system. The second stage is configured to convert the single-ended output voltage signal generated by the first stage to a differential voltage output signal. To this end, the second stage is configured to receive a differential input via two inputs: a first input (e.g., a negative input, denoted herein as "IN-") and a second input (e.g., a positive input, denoted herein as "IN +"). The first differential input of the second stage is configured to receive a signal based on the single-ended voltage signal generated by the first stage. The second differential input of the second stage is configured to receive a signal based on the output offset current of the second stage. The second stage is further configured to provide a differential output via: a first output (e.g., a negative output, denoted herein as "OUT-") and a second output (e.g., a positive output, denoted herein as "OUT +"). In such a TIA, the input linear range of the second stage may be adjusted by using a clamp circuit at/in (or associated with) the output of the first stage to keep the second stage of the TIA and subsequent ADCs free of overload and to help ensure that the second stage has a linear transfer function with substantially no compression.

In various embodiments, the clamp may be a high side clamp or a low side clamp. As known in the art and used herein, "high-side clamping" of a signal refers to ensuring that the magnitude of the signal does not exceed a maximum value set by a circuit referred to as "high-side clamping circuit" or simply "high-side clamping". Similarly, as known in the art and used herein, "low side clamping" of a signal refers to ensuring that the magnitude of the signal does not fall below a minimum value set by a circuit referred to as a "low side clamp" or simply a "low side clamp". When triggered, the clamp circuit of any of the multi-stage TIAs described herein may ensure that the voltage of the signal at the first differential input coincides with a clamp value, i.e., does not exceed a maximum voltage value if the clamp circuit is a high-side clamp circuit or does not drop below a minimum voltage value if the clamp circuit is a low-side clamp circuit.

In some embodiments, the clamp circuit may be programmed with an output offset current, meaning that the clamp value applied by the clamp circuit may be based on (e.g., may depend on or may be calculated from) the output offset current of the second stage. Thus, when the clamping circuit of the multi-stage TIA described herein is a high-side clamp, the maximum value that the clamping circuit sets/applies to the single-ended output voltage signal from the first stage may be based on the output offset current of the second stage. On the other hand, when the clamp is a low side clamp, the minimum value that the clamp sets/applies to the single ended output voltage signal from the first stage may be based on the output offset current of the second stage. Regardless of whether the clamping circuit is a high-side clamp or a low-side clamp, the multi-stage TIA may advantageously ensure that the differential inputs of the second stage, and consequently the ADC, are not overloaded, since the second input of the differential input of the second stage receives a signal based on the output offset current, and since the first input of the differential input of the second stage receives a clamped version of the single-ended output voltage signal from the first stage (where clamping is also based on the output offset current).

In some embodiments, the second stage of the multi-stage TIA disclosed herein may be considered part of the ADC driver.

Fig. 5-14 illustrate some exemplary embodiments of a multi-level TIA having an adjustable input range. However, any implementation of a multi-level TIA with an adjustable input range is within the scope of the present disclosure, in accordance with the description provided herein.

Other aspects of the present disclosure provide systems, such as LIDAR systems (particularly LIDAR receivers), which may include one or more multi-stage TIAs with adjustable input ranges implemented using programmable clamp circuits as described herein, as well as methods of operating such systems and methods of using such systems to determine a distance to at least one object. While some embodiments of the present disclosure refer to LIDAR as an exemplary system in which a multi-stage TIA having an adjustable input range as described herein may be implemented, in other embodiments, a multi-stage TIA as described herein may be implemented in systems other than LIDAR, all of which are within the scope of the present disclosure. Further, although some embodiments of the present disclosure describe a multi-stage TIA with an adjustable input range receiving a single-ended current input from an optical sensor, all of the multi-stage TIAs described herein may be used in systems where the single-ended current input is provided by any other source or electronic component. Similarly, although some embodiments of the present disclosure describe a multi-stage TIA with adjustable input range that provides a differential voltage output to an ADC, all of the multi-stage TIAs described herein may be used in systems where a differential voltage output is provided from a multi-stage TIA to any other electronic component other than an ADC. Still further, as described herein, an arrangement that converts a single-ended signal to a differential signal using an output offset current and clamps the single-ended signal based on a value of the output offset current may be used in systems other than LIDAR systems, ADC drivers, and TIAs, all of which are within the scope of the present disclosure.

The precise design of a multi-level TIA with adjustable input range described herein may be implemented in many different ways, all of which are within the scope of the present disclosure. In one example of a design variation in accordance with various embodiments of the present disclosure, for each of the transistors of a multi-level TIA having an adjustable input range, a bipolar transistor (e.g., where the various transistors may be NPN or PNP transistors), a Field Effect Transistor (FET) (e.g., a Metal Oxide Semiconductor (MOS) technology transistor (e.g., where the various transistors may be N-type MOS (nmos) or P-type MOS (pmos) transistors)), or a combination of one or more FETs and one or more bipolar transistors may be chosen, respectively. In view of this, in the following description, the first terminal, the second terminal, and the third terminal of the transistor are sometimes described with reference to them. The term "first terminal" of a transistor is used to refer to an emitter terminal in case the transistor is a bipolar transistor, or to a source terminal in case the transistor is a FET; the term "second terminal" of a transistor is used to refer to a collector terminal in the case where the transistor is a bipolar transistor, or to a drain terminal in the case where the transistor is an FET; and the term "third terminal" of a transistor is used to refer to a base terminal in the case where the transistor is a bipolar transistor, or a gate terminal in the case where the transistor is an FET. These terms remain the same regardless of whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor in the case where the transistor is a bipolar transistor or an NMOS transistor in the case where the transistor is a FET) or a P-type transistor (e.g., a PNP transistor in the case where the transistor is a bipolar transistor or a PMOS transistor in the case where the transistor is a FET). In another example, in various embodiments, for each of the transistors of the multi-level TIA having an adjustable input range, a selection may be made of which transistors to implement as N-type transistors (e.g., the transistors are implemented as NMOS transistors of a FET, or the transistors are implemented as NPN transistors of a bipolar transistor), and which transistors to implement as P-type transistors (e.g., the transistors are implemented as PMOS transistors of a FET, or the transistors are implemented as PNP transistors of a bipolar transistor), respectively. In still other examples, in various embodiments, which type of transistor architecture is employed may be selected. For example, any of the transistors implemented as FETs of a multi-stage TIA having an adjustable input range as described herein may be planar transistors or may be non-planar transistors (some examples of the latter include finfets, nanowire transistors, or nanoribbon transistors).

As will be appreciated by one skilled in the art, aspects of the present disclosure, and in particular aspects of a multi-level TIA with adjustable input range as presented herein, may be implemented in various ways (e.g., as a method, system, computer program product, or computer-readable storage medium). Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," module "or" system. The functions described in this disclosure may be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of each of the methods described herein may be performed by different processing units. Furthermore, aspects of the disclosure may take the form of a computer program product embodied in one or more computer-readable media, which are preferably non-transitory, having computer-readable program code embodied thereon (e.g., stored). In various embodiments, such computer programs may, for example, be downloaded (updated) to existing devices and systems (e.g., to existing receivers, LIDAR systems, and/or their controllers, etc.) or stored at the time of manufacture of such devices and systems.

The following detailed description presents various descriptions of specific certain embodiments. However, the innovations described herein may be implemented in a number of different ways (e.g., as defined and encompassed by the selection examples). In the following description, reference is made to the accompanying drawings wherein like reference numbers may indicate identical or functionally similar elements. It will be understood that the elements shown in the figures are not necessarily drawn to scale. Further, it should be understood that certain embodiments may include more elements than shown in the figures and/or a subset of the elements shown in the figures. Further, some embodiments may incorporate any suitable combination of features from two or more of the figures.

The description may use the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. Unless otherwise specified, the use of the ordinal adjectives "first", "second", and "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Further, for purposes of this disclosure, the phrase "a and/or B" or the symbol "a/B" refers to (a), (B), or (a and B), while the phrase "A, B and/or C" refers to (a), (B), (C), (a and B), (a and C), (B and C), or (A, B and C). As used herein, the notation "A/B/C" means (A, B and/or C). The term "between …" when referring to a measurement range includes the ends of the measurement range.

Various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term "connect" refers to a direct electrical connection between the things that are connected, without any intervening devices/components, while the term "couple" refers to a direct electrical connection between the things that are connected, or an indirect electrical connection through one or more passive or active intervening devices/components. In another example, the term "circuitry" refers to one or more passive and/or active components arranged to cooperate with one another to provide a desired function. Sometimes, in this description, the term "circuit" may be omitted (e.g., a clamp circuit may be simply referred to as "clamp" or the like). The terms "substantially," "approximately," "about," and the like, if used, may be used to generally refer to within +/-20% of a target value, such as within +/-10% of the target value, based on the context of the particular value as described herein or as known in the art.

Foundation of multi-stage TIA

To illustrate the multi-stage TIA with adjustable input range presented herein, implemented using a programmable clamp circuit, it may be useful to first understand the settings in which a multi-stage TIA may be used and the phenomena that may occur when using such a TIA. The following basic information may be considered as a basis on which the present disclosure may be appropriately explained. Such information is provided for purposes of explanation only, and thus, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.

As described above, a multi-level TIA may be used in a LIDAR system. Fig. 1 is a schematic diagram of a LIDAR receiver 100. A LIDAR receiver typically includes an optical sensor (e.g., APD)102, a TIA104, and an ADC 106. The optical sensor 102 may be configured to receive pulses of light reflected from an object and convert the pulses of light into pulses of current. As shown in fig. 1, in some embodiments, the optical sensor 102 may have its cathode connected to an input port of the TIA104 (the input port of the TIA104 is shown in fig. 1 with a white dot labeled IIN (standing for "input current") 103). Thus, the optical sensor 102 may be negatively biased and may sink current from the TIA 104. Although not specifically shown in this figure, in other embodiments, the optical sensor 102 may have its anode connected to the input port of the TIA 104; thus, the optical sensor 102 will be positively biased and may provide current to the TIA 104.

The TIA104 may be configured to amplify the current pulses from the optical sensor 102 and provide voltage pulses. The TIA104 may be a multi-stage TIA having a first stage and a second stage. The first stage may include an amplification circuit 105 (shown in fig. 1 and also interchangeably referred to herein as "amplifier a 0") and a feedback Resistor (RT)107 electrically coupled between an input of the amplification circuit 105 and an output of the amplification circuit 105. The first stage may be configured to convert a single-ended input current signal IIN (e.g., a current from the optical sensor 102) to a single-ended output voltage signal, which is provided at an output of the amplification circuit 105. The output of the amplification circuit 105 may be electrically connected to an input of a second stage, which may be considered to be part of the ADC driver. The second stage may include an amplification circuit 109 (shown in fig. 1 and also interchangeably referred to herein as "amplifier a 2"). The second stage may be configured to perform single-ended to differential conversion to generate differential drive signals for the ADC 106. For this purpose, the amplification circuit 109 has a differential input, as shown in fig. 1, with the following two input terminals: a first input terminal, shown as "IN-" (e.g., a negative input); and a second input terminal, shown as "IN +" (e.g., a positive input). Fig. 1 further shows that the amplification circuit 109 has a differential output, as shown in fig. 1 with the following two output terminals: a first output terminal, shown as "OUT-" (e.g., a negative output); and a second output terminal, shown as "OUT +" (e.g., a positive output). The ADC106 may convert the received differential analog signal (which is based on the differential output from the amplification circuit 109) (e.g., a differential analog voltage pulse signal) into a digital signal. The digital signal may be provided to a digital signal processor (not shown in fig. 1).

Generally, the two amplifiers a0 and a2 are designed to be optimized according to different parameters. Amplifier a0 may be optimized for maximum dynamic range (e.g., maximum input linear range and minimum input current noise), while amplifier a2 may be optimized for maximum output swing as an output stage that may also be included or included in an ADC driver that may scale the signal and concentrate the differential output around the input common mode voltage of the ADC.

As shown IN fig. 1, the negative input terminal of amplifier a2 (i.e., the input terminal of a2 labeled "IN-" IN fig. 1) may be coupled to the single-ended output of amplifier a 0. The positive input terminal of amplifier a2 (i.e., the input terminal of a2 labeled "IN +" IN fig. 1) may be coupled to a reference voltage source 110 configured to output a reference voltage VREF. The reference voltage provided by the reference voltage source VREF may be adjustable, for example, to best utilize the dynamic range provided by the electronic components configured to receive the differential output from the second stage of the TIA104, for example, to best utilize the dynamic range provided by the ADC 106.

In some embodiments, the reference voltage source 110 of fig. 1 may be implemented with the reference voltage circuit 210 as shown in fig. 2 (otherwise, fig. 2 shows a LIDAR receiver 200 that is substantially the same as the LIDAR receiver 100 shown in fig. 1). Fig. 2 illustrates that, in some embodiments, the circuit 210 may include an amplification circuit 205 (shown in fig. 2 and also interchangeably referred to herein as "amplifier a 1") and a feedback Resistor (RT)207 electrically coupled between an input of the amplification circuit 205 and an output of the amplification circuit 205. The output of the amplification circuit 205 may be electrically coupled to an input of the second stage, for example, to the positive input terminal of amplifier a 2. In some embodiments, amplifier a1 may be substantially an exact or scaled copy of amplifier a0 (which may save area and power). Amplifier a0 may be referred to as the "signal TIA" or "main TIA" (since this is the circuit that performs the current-to-voltage conversion), while amplifier a1 may be referred to as the "reference TIA" or "replica TIA. The reference voltage VREF provided by the amplifier a1 at the positive input of the amplifier a2 may be adjusted in a power efficient manner using a current source that provides the current I0 to the input of the replica TIA a 1. The output voltage of the replica amplifier a1 with I0 ═ 0 can be configured to track the output voltage of the main amplifier a0 with IIN ═ 0 as process, voltage, and temperature (PVT) variations. The current I0 is commonly referred to as the "output offset current" of/for the first stage of the TIA 104. The output offset current may be used to modify the output of the multi-stage TIA104 (a process sometimes referred to as "ramping") in order to better utilize the input signal range of subsequent electronic components (e.g., the ADC 106) configured to receive the output of the TIA 104.

Prior art solutions have generally focused on mitigating overloading of amplifier a0 (e.g., in response to the output current of the optical sensor 102 exceeding the linear input range of amplifier a0) to prevent permanent damage and ensure fast recovery times. A TIA optimized for low noise and large output swing in a high-speed LIDAR receiver may have a linear range of 100 microamps. At very large currents (e.g., on the order of hundreds of milliamps) from the optical sensor 102, an external mechanism such as a protection diode may be necessary to prevent permanent damage to the amplifier a 0. At more moderate currents (e.g., on the order of a few milliamps) from the optical sensor 102, the amplifier a0 may include an internal mechanism to keep the transistor out of the saturation region, which facilitates rapid recovery after the overload condition is removed.

The inventors of the present disclosure have recognized that each amplifier stage of a multi-stage TIA requires fast recovery in order to achieve an optimal response. While existing solutions may rely on internal mechanisms within each amplifier to handle overload conditions, embodiments of the present disclosure provide for a simple adjustable circuit that relies on limiting the maximum swing in a previous amplifier stage.

Input and output waveforms at amplifier A2 for a multi-stage TIA

Fig. 3 provides a plot 310 of an exemplary input waveform for amplifier a2 and a plot 320 of an exemplary output waveform for amplifier a2 with I0 ═ 0. The solid line 312 of the plot 310 indicates the signal provided to the negative input IN-of the amplifier a2 when I0 is 0. The dashed line 314 of the diagram 310 indicates the signal provided to the positive input IN + of the amplifier a2 when I0 is 0. The solid line 322 of the diagram 320 indicates the signal provided at the negative output OUT-of the amplifier a2 when I0 is 0. The dashed line 324 of the diagram 320 indicates the signal provided at the positive output OUT + of the amplifier a2 when I0 is 0.

Line 312 of plot 310 illustrates an exemplary response of the output of amplifier a0 with respect to the input current IIN of amplifier a 0. For IIN equal to 0, the output of amplifier a0 may have a minimum value V_min,A0The minimum is marked at the bottom of the plot 310. The output of replica amplifier a1 with zero output offset current (i.e., I0 ═ 0) is also V_min,A0. When IIN is 0 and I0 is 0, amplifiers a0 and a1 may be considered to match in all respects, and their outputs are the same.As the input current IIN increases, the output of amplifier A0 may reach its maximum value V_max,A0This maximum value is also marked in the diagram 310. Thus, when I0 is 0, the minimum differential input of amplifier a2, which is the output of amplifier a0 (V) when IIN is minimum (i.e., IIN is 0), may be 0_min,A0) And the output of amplifier a1 (also V) when I0 is 0 and IIN is 0_min,A0) The difference between them. On the other hand, the maximum differential input of amplifier A2 may be V_max,A0And V_min,A0The difference between, i.e. the output of amplifier A0 (i.e. V) when IIN is maximum_max,A0) And the output of amplifier a1 (i.e., V) when I0 is 0_min,A0) The difference between them. The diagram 320 of fig. 3 shows a vertical dash-dot line 328. The portion of the plot 320 shown to the left of line 328 shows the negative and positive outputs of amplifier a2 when IIN is 0. The portion of the plot 320 shown to the right of line 328 shows the negative and positive outputs of amplifier a2 as IIN gradually increases, showing the deviation between the negative and positive outputs of amplifier a 2.

In pulsed LIDAR systems (where linearity of the output is often not important), the maximum output swing of amplifier a0 at the input of reference amplifier a0 corresponds to the linear input range (I) of its current_LRWhere "LR" represents the "linear range"), i.e.:

where RT is the feedback resistance 107 between the input and output of amplifier a 0. In such a case, as shown in the graph 320 of FIG. 3, the differential output response of the amplifier A2 may be a symmetric output around the common-mode voltage Vcm (shown with dotted line 326 in the graph 320 of FIG. 3), with a minimum value V at the negative output terminal OUT-of the amplifier A2_min,A2And a maximum value at the positive output terminal OUT + of the amplifier a2 is V_max,A2. In some embodiments, the common mode voltage Vcm of amplifier a2 may be set to match the input common mode voltage of ADC 106. In various embodiments, the TIA104 may have additional passive and/or active components (not shown in this figure),to set or adjust the output to a desired common mode output voltage to match the input common mode of the ADC 106.

To maximize the differential output swing of amplifier a2, the optimal reference voltage VREF at the positive input IN + of amplifier a2 may be_optIs set as V_min,A0And V_max,A0Average value of (d):

this will limit the maximum voltage of the differential input of amplifier a2 to:

i.e., the linear range of the amplifier is +/-dV, which is half the maximum swing of amplifier a 0.

The optimum output offset current in this case is

The optimum output offset current is equal to the linear input range I of the first stage amplifier A0_LRHalf (i.e., I0)_opt＝0.5*I_LR). FIG. 4 provides a plot 410 of an exemplary input waveform for amplifier A2 and a plot 420 of an exemplary output waveform for amplifier A2, where the output offset current I0 is equal to the linear input range I of amplifier A2_LRHalf of (i.e., I0 ═ I0)_opt＝0.5*I_LR). Solid line 412 of diagram 410 indicates when I0 ═ I0_opt＝0.5*I_LRThe signal is provided to the negative input in-of amplifier a 2. Dashed line 414 of diagram 410 indicates when I0 ═ I0_opt＝0.5*I_LRThe signal provided to the positive input IN + of amplifier a 2. Solid line 422 of diagram 420 indicates when I0 ═ I0_opt＝0.5*I_LRIs the signal provided at the negative output OUT-of amplifier a 2. Dashed line 424 of diagram 420 indicates when I0 ═ I0_opt＝0.5*I_LRIs the signal provided at the positive output OUT + of amplifier a 2.

As shown IN fig. 4, with the optimal reference voltage at the positive input IN + of amplifier a2, the differential output swing of amplifier a2 of diagram 420 IN fig. 4 may be twice the differential output swing of diagram 320 IN fig. 3. The graphs of fig. 3 and 4 show that when IIN is 0 and the output offset current I0 is 0, then amplifiers a0 and a1 are matched in all respects and their outputs are substantially the same, and by varying I0, a differential voltage can be produced at the input of a2, which can advantageously achieve what is commonly referred to as "ramping" -i.e., the separation between the negative and positive outputs of amplifier a2 when IIN is 0, which allows the full range of amplifier a2 to be used. The diagram 420 of fig. 4 further shows a line 426 and a vertical dash-dot line 428 representing the common mode voltage Vcm. The portion of the plot 420 shown to the left of line 428 shows the negative and positive outputs of amplifier a2 when IIN is minimum (e.g., when IIN is 0, which is minimum for a single polarity input current at the input of amplifier a 0). The portion of the plot 320 shown to the right of line 428 shows the negative and positive outputs of amplifier a2 as IIN is gradually increased. Both the left and right portions of line 428 show the deviation between the negative and positive outputs of amplifier a2, which is the "tilt" of amplifier a2 by appropriate selection of the output offset current I0. This is in contrast to the diagram of fig. 3, where the output offset current I0 is equal to zero, and thus, when IIN is 0, the left portion of line 328 in diagram 320 of fig. 3 has no deviation between the negative and positive outputs of amplifier a 2.

Multi-level TIA with clamping based on output offset current

As described above, the output offset current I0 may be provided to the replica amplifier a1 to generate a voltage at the positive input of the differential amplifier a2 that allows better utilization of the input linear range of the amplifier a 2. As described above, the optimum output offset current I0_optMay be equal to half the linear range of the output of amplifier a0, i.e., half the linear range current defined by equation (1) above, which results in the optimum voltage VREF at the positive input of amplifier a2_optAccording to the above equation (2), the optimum voltage is V_min,A0And V_max,A0Average value of (a). In various embodiments, the arrangement of TIAs 104 with amplifiers a0, a1, and a2 as described herein may be used with different ADCs (or different other electronic components that receive differential outputs as inputs from amplifier a2), where the different ADCs may have different input ranges, and thus, the second stage of the multi-stage TIA104 may have different input ranges. Additionally, if the input range of the differential ADC is less than the input range of the TIA, the input range of the TIA should be limited so that the output of the TIA does not exceed the input range of the ADC. Therefore, the optimum output offset current I0_optMay vary depending on the implementation of the multi-level TIA 104. Thus, the multi-stage TIA may be configured such that the output offset current I0 may be controlled by an external signal, such as an external voltage signal. Such voltage signals may be provided as the output of a digital-to-analog converter (DAC), or by any other circuitry suitable for generating such control signals. The external voltage signal may then be converted to an output offset current I0 using a voltage-to-current converter.

The inventors of the present disclosure have recognized that even with an output offset current that is controllable by an external signal as described above, it may not always function as intended to prevent overloading of various components of a multi-stage TIA (such as the multi-stage TIA 104). In particular, the inventors of the present disclosure recognized that it is even possible to use an external control signal to attempt to produce an I0 equal to optimal_optThe actual output offset current I0 received by the replica amplifier a1_actMay also deviate from the optimum I0_opt. Some of the reasons that the value of the actual output offset current may deviate from the optimum value include PVT variations, and the fact that external control signals and voltage-to-current converter circuits that may be used to generate the output offset current based on the control voltage may vary. Make the actual output offset current I0_actDeviation from optimal output offset current I0_optProblems such as overloading of the amplifier a2 may arise. For example, if the actual output offset current I0_actLess than I0_optThe maximum differential input of amplifier a2 may exceed dV and overload amplifier a 2. Similarly, based on realityThe actual output offset current deviates from the optimum current I0_optCausing the voltage at the positive input of amplifier a2 to drop below some minimum value may cause problems.

Embodiments of the present disclosure are based on the recognition that: the actual output offset current I0 may be compensated by providing a clamp circuit_actAnd the optimum output offset current I0_optCoupled to the negative input of the amplifier a2 and configured to offset the current I0 based on the actual output defining the voltage at the positive input of the amplifier a2_actTo clamp either the maximum voltage or the minimum voltage at the negative input of amplifier a 2. In this way, the actual output offset current I0_actMay happen to deviate from the optimum output offset current I0_optResulting in the actual voltage at the positive input of amplifier a2 deviating from the optimum value VREF_optBut is configured to clamp the voltage at the negative input of amplifier a2 correspondingly to an offset current I0 based on the actual output_actThe clamp circuit of the value of (a) may compensate for the deviation at the positive input to ensure that, for example, amplifier a2 is not overloaded.

Figure 5 is a circuit diagram illustrating a LIDAR receiver 500 with a multi-stage TIA504 having an adjustable input range, in accordance with some embodiments of the present disclosure. As shown in fig. 5, the LIDAR receiver 500 may include the optical sensor 102 and the ADC106, as described above. Additionally, the TIA504 may include a first stage having an amplifier a0 and a resistor RT, as described above, the amplifier a0 configured to receive the input current signal IIN, and may further include a second stage having an amplifier a2, also as described above. Furthermore, the TIA504 may further include circuitry, such as a replica amplifier a1, configured to set the voltage at the positive input of the amplifier a2 using the output offset current I0, also as described above. Thus, the TIA504 may be substantially similar to the TIA104 shown in fig. 2. The TIA504 differs in that it further includes a clamp circuit 520 coupled to the output of the amplifier a0 (or, equivalently, to one of the differential inputs of the amplifier a2, i.e., to the negative input of the amplifier a2) and configured to clamp the voltage of the signal at the output of the amplifier a0 (or, equivalently, the voltage of the signal at the negative input of the amplifier a2) to a clamped value, where the clamped value is based on the output offset current I0 provided to the replica amplifier a 1.

Consider first the case where clamp 520 is a high-side clamp.

To avoid overloading amplifier A2, the maximum voltage at the output of amplifier A0 may need to be limited to less than V_max,A0. To this end, the clamp circuit 520(C0) shown in fig. 5 may be a high side clamp 520 coupled to the output of amplifier a 0. The clamp C0 may be coupled directly or indirectly to the output of the amplifier a0 in order to limit the maximum output voltage of the amplifier a 0. In particular, the clamp C0 may be programmed by the same value of the output offset current I0 as used by the replica amplifier a1 to generate a reference voltage at the positive input of the amplifier a2, such that the output voltage of the amplifier a0 may be clamped to a maximum value V defined based on the output offset current I0_CLHI. For example, the maximum output voltage of amplifier a0 may be clamped by the linear input range dV of amplifier a2 to not exceed the output voltage of amplifier a1, i.e.:

V_CLHI＝V_out,A1+dV， (4)

wherein the term V_CLHIThe abbreviation "CLHI" in (1) indicates the voltage V_CLHIIs the High (HI) Clamp (CL) voltage. Equation (4) can be rewritten as:

it should be noted that TIA504 shown in fig. 5 shows a current source that produces output offset current I0 twice (once to provide input to amplifier a1 and once to provide input to clamp 520). In some embodiments, this may mean that the same current source is used to generate the output offset current I0 in both cases (i.e., a single current source is used to provide the output offset current I0 as an input to the amplifier a1 and an input to the clamp 520). For example, in some such embodiments, a single current mirror having multiple outputs may be used to produce currents having the same value. In other embodiments, the current source that generates current I0 as an input to amplifier a1 and as an input to clamp circuit 520 may be different current sources that are both set to the same value, e.g., both are programmed using an external voltage, as described above. In some embodiments of fig. 5, amplifier a1 may be a scaled (e.g., smaller) version of amplifier a0 (e.g., to save silicon area and/or quiescent current drawn from the power supply). For example, scaling may be implemented by using a feedback resistor of resistance N RT, where the scaling factor N may be a number greater than 1 (while fig. 5 shows the feedback resistor of amplifier a1 with N1). In such embodiments, the current source at the input of amplifier a1 would scale down to I0/N by the same factor.

When inputs are involved, such a clamp circuit 520 is used to clamp the maximum voltage at the output of amplifier A0 to a clamp voltage V_CLHICorresponding to (or causing to) effectively adjust the linear input range of the amplifier a0 (i.e., the first stage of the TIA 504) based on the output offset current (thus, the TIA504 may be referred to as a "multi-stage TIA with an adjustable input range"). In particular, equation (1) can now be rewritten as V_max,A0Is replaced by V_CLHIThe following are:

will be V in equation (6)_CLHIReplace with the right side of equation (5), input the linear range I_LRThe dependence on the output offset current I0 becomes clear:

the proposed high-side clamp 520 may not only reduce or eliminate the possibility of overloading the amplifier a2, but may also adjust the input linear range of the amplifier a0 to maintain a linear transfer function between the single-ended input IIN of the amplifier a2 and the differential outputs OUT + and OUT-. Equation (7) shows that the input linear range nowIs a function of the output offset current I0, where the maximum value is (V)_max,A0±V_min,A0)/RT＝VREF_optand/RT. The maximum input linear range is the input linear range before the high-side clamp is introduced.

Figure 6 is a circuit diagram illustrating a first stage 600 of an exemplary TIA according to some embodiments of the present disclosure. The first stage 600 may be used to implement the first stage of the TIA504 shown in figure 5, i.e., to implement the amplifier a0 with resistor RT as shown in figure 5. In particular, the example of wide bandwidth high dynamic range amplifier 105(a0) of fig. 5 is shown in fig. 6 as circuit 605 (enclosed within a dashed outline). As shown in fig. 6, the amplifier 605 may include transistors Q1 and Q2 (both shown as NPN transistors), a load element 610 (e.g., a load resistor) R1, and a current source I2. Fig. 6 further shows a feedback resistor 107(RT) connected between the input terminal IIN of the amplifier a0 and the output terminal (labeled out, a0 in fig. 6) of the amplifier a 0. Fig. 6 also shows Vee (i.e., the negative supply of the circuit, which may be ground) and Vcc (i.e., the positive supply of the circuit).

Fig. 7A and 7B are circuit diagrams of fig. 6 showing examples of operating points for minimum and maximum output swings, respectively.

Fig. 7A shows the default operating point with no input current under the following conditions: positive power supply Vcc-3.3V, negative power supply Vee-0.0V, and zero input current. Further, for each of the transistors shown in fig. 7A, a base-emitter voltage (V) is assumed_BE) Is 0.8V and the base current is assumed to be negligible. The input terminal IIN at the base of Q1 is Vee + V_BE0.8V and the output terminal out, as does a 0. Thus, the minimum voltage output swing may be V_min,A0＝0.8V。

Fig. 7B shows the maximum output swing. When I is_C,Q1(i.e., collector current of Q1) tends to zero, the base voltage of Q2 will tend to the positive supply of 3.3V, and thus the maximum output voltage on the output terminal out, a0 will be 0.8V lower than the positive supply, i.e., V_max,A0＝2.5V(V_max,A0＝Vcc-V_BE2.5V). At maximum output swing, the input current (under this condition) is for a feedback resistance RT of 17 kohmAlso equal to the input linear range) will be 100 microamps. Applying an output offset current of 50 microamps at input amplifier A1 will result in the optimum reference voltage VREF according to equation (2) above_opt＝1.65V。

Figure 8 is a circuit diagram illustrating an example of a first stage 800 of a multi-stage TIA504 with adjustable input range implemented by a clamp circuit 520 as a voltage controlled high side clamp circuit, according to some embodiments of the present disclosure. Fig. 8 provides an illustration similar to the first stage 600 shown in fig. 6, further showing a transistor Q3 for implementing the clamp circuit 520 as a high side clamp circuit 820 (an approximate outline of the clamp circuit shown in fig. 8 with a dashed outline labeled with reference numeral 820). As shown in fig. 8, transistor Q3 may be controlled by control voltage 825 (e.g., by having its base terminal coupled to control voltage 825), which may be set to V as described above_CLHII.e., where the control voltage 825 is a function of the output offset current I0. The transistor Q3 is indirectly coupled to the output (out, a0) of the amplifier a0 by being coupled to the transistor Q2, as shown in fig. 8, and may therefore limit the maximum output swing of the amplifier a 0. As shown in FIG. 8, in some embodiments, the transistor Q3 may be implemented as a PNP transistor, wherein the base of the transistor Q3 may be coupled to a control voltage (high clamp voltage) V_CLHIThe collector of the transistor Q3 may be coupled to the negative power supply Vee, and the emitter of the transistor Q3 may be coupled to the base of the load transistor R1 and the transistor Q2 implemented as the amplifier a0 of the circuit 605, as described above. In this arrangement, if the output offset current is set to zero, and further assume that V_BE,Q2＝|V_BE,Q3I, will V_CLHISetting equal to 1.65V (according to equation (5) above) limits the input linear range to 50 microamps (according to equation (7) above).

In other embodiments, the clamp 520 may be implemented as a voltage controlled low side clamp. An example of such an implementation is shown in fig. 9, providing a circuit diagram illustrating an example of a first stage 900 of a multi-stage TIA with adjustable input range implemented by a voltage controlled low side clamp 920, according to some embodiments of the present disclosure.The circuit diagram shown in fig. 9 is similar to the circuit diagram shown in fig. 8, except that: all PNP transistors have been replaced by NPN transistors and vice versa, the supply voltages Vcc and Vee have been swapped, and reference numbers given to the various elements begin with "9" instead of "8", "6" or "1". In the first stage 900, the term V_CLLOThe abbreviation "CLLO" in (1) indicates that the control signal 925 is a Low (LO) Clamp (CL) voltage V_CLLO. High clamping voltage V similar to that described above_CLHILow clamping voltage V_CLLOIs the voltage applied by clamp circuit 520 to the output of amplifier a0 to ensure that the output does not fall below a minimum value, V_CLLO. Also similar to the above-mentioned high clamping voltage V_CLHILow clamping voltage V_CLLODepending on the actual output offset current I0. In particular, the clamp may be programmed by the same value of the output offset current I0 as used by the replica amplifier a1 to generate a reference voltage at the positive input of the amplifier a2, such that the output voltage of the amplifier a0 may be clamped to a minimum value V defined based on the output offset current I0_CLLO. For example, the minimum output voltage of amplifier a1 may be clamped by the linear input range dV of amplifier a2 so as not to fall below the output voltage of amplifier a1, i.e.:

V_CLLO＝V_out,A1-dV。 (8)

equation (8) can be rewritten as:

one may note the symmetry between the high side clamp equations (4), (5) and the low side clamp equations (8), (9): the power supply and current directions have been reversed, so + dV in equation (4) becomes-dV in equation (8), + I0 RT in equation (5) becomes-I0 RT in equation (9), and V in equation (5) becomes_min,A0＝Vee+V_BEBecomes V in equation (9)_max,A0＝(Vcc-|V_BE|)。

When relating toAnd at input, clamping the minimum voltage at the output of amplifier a0 to a clamping voltage V using clamp 520 as a low side clamp_CLLOThe linear input range of the second stage of TIA504 is adjusted corresponding to (or caused to) according to equation (9).

The embodiments shown in fig. 8 and 9 illustrate a voltage controlled clamp circuit configured to clamp the voltage at the negative input of amplifier a2 to ensure that the voltage at the negative input of amplifier a2, respectively, does not exceed a voltage set by V, which is dependent on the output offset current_CLHIThe maximum value set (for the embodiment shown in fig. 8) and the voltage at the negative input of amplifier a2 does not drop below V, which is determined by the output offset current_CLLOThe set minimum value (for the embodiment shown in fig. 9). However, in other embodiments, the voltage control clamp may be implemented differently than the circuits 820 or 920 shown in fig. 8 and 9, and/or the first stage of the TIA504 may be implemented using a circuit different from the circuits 805 or 905 shown in fig. 8 and 9, so long as such other circuits allow for the implementation of V as described herein_CLHIAnd V_CLLOAnd (4) finishing. Further, in still other embodiments, clamp 520 may be implemented as a current-controlled clamp, i.e., where voltage V is replaced_CLHIOr V_CLLOThe control signal dependent on the output offset current is the high side current I_CLHIOr low-side current I_CLLO。

Figure 10 is a circuit diagram illustrating an example of a first stage 1000 of a multi-stage TIA504 with adjustable input range implemented by a clamp circuit 520 as a current control high side clamp circuit, according to some embodiments of the present disclosure. FIG. 10 provides an illustration of a first stage 800 similar to that shown in FIG. 8, except that: the high clamp voltage control circuit 820 shown in fig. 8 is now replaced by a high clamp current control circuit 1020 in fig. 10, i.e., a circuit 1020 (an approximate outline of the clamp circuit shown in fig. 10 with a dashed outline labeled with reference numeral 1020). As shown in fig. 10, the clamp circuit 1020 may include a transistor Q3 coupled to the first stage of the amplifier, as described with reference to fig. 8. In contrast to the illustration of FIG. 8, of transistor Q3 of clamp circuit 1020The base terminal is coupled to further devices which may, for example, include transistors Q3 and Q4 and resistor R4, as shown in fig. 10. The further apparatus may couple a base terminal of the transistor Q3 of the clamp circuit 1020 to a control current 1025 that may be set to I as a function of the output offset current I0_CLHIFor example, such as:

the equation can be rewritten as:

in some embodiments, R4 may be set to RT. The voltage V in these equations_BEIs the base-emitter voltage across transistor Q2.

Since the transistor Q3 of the clamp 1020 is indirectly coupled to the output (out, A0) of the amplifier A0 by being coupled to the transistor Q2, as shown in FIG. 10, the control current I coupled to the clamp 520_CLHIThe transistor Q3 of the clamp circuit 1020 may limit the maximum output swing of the amplifier a0 (by limiting the output voltage of the amplifier a0 to V_CLHI)。

In other embodiments, the clamp 520 may be implemented as a current-controlled low-side clamp. An example of such an implementation is shown in fig. 11, providing a circuit diagram illustrating an example of a first stage 1100 of a multi-stage TIA504 with adjustable input range implemented by a clamp 520 as a current-controlled low-side clamp, according to some embodiments of the present disclosure. The circuit diagram shown in fig. 11 is similar to the circuit diagram shown in fig. 10, except that: all PNP transistors have been replaced by NPN transistors and vice versa, the supply voltages Vcc and Vee have been swapped, and reference numbers given to the various elements begin with "11" instead of "10". In the first level 1100, the term I_CLLOThe abbreviation "CLLO" in (1) indicates that the control signal 1125 is a Low (LO) clampBit (CL) current I_CLLO. High clamping current I similar to that described above_CLHILow clamping current I_CLLOAllowing the clamp circuit 520 to apply a voltage V to the output of the amplifier A0_CLLOTo ensure that the output does not fall below a certain minimum voltage value, which is V_CLLO. Also similar to the above-mentioned high clamping current I_CLHILow clamping current I_CLLODepending on the actual output offset current I0, for example, as:

the equation can be rewritten as:

let ve be 0. In some embodiments, R4 may be set to RT. The voltage V in these equations_BEIs the base-emitter voltage across transistor Q2 (negative for PNP transistors).

Using clamp 520 as a low side clamp when input is involved is based on clamp current I_CLLOClamping the minimum voltage at the output of the amplifier a0 corresponds to (or results in) adjusting the linear input range of the second stage of the TIA504 according to equation (12).

The embodiments shown in fig. 10 and 11 show a current control clamp configured to clamp the voltage at the negative input of amplifier a2 to ensure that the voltage at the negative input of amplifier a2, respectively, does not exceed the output offset current dependent I_CLHIThe maximum value set (for the embodiment shown in fig. 10) and the voltage at the negative input of amplifier a2 does not drop below the value set by I, which depends on the output offset current_CLLOThe set minimum value (for the embodiment shown in fig. 11). However, in other embodiments, the current control clamp may be implemented differently than the circuits 1020 or 1120 shown in fig. 10 and 11, and/or the first stage of the TIA504 may useCircuitry other than circuitry 1005 or 1105 shown in fig. 10 and 11, provided such other circuitry allows V to be implemented as described herein_CLHIAnd V_CLLOAnd (4) finishing.

Figures 5-11 illustrate some specific example implementations of a multi-level TIA with a programmable clamp of a first level, according to some embodiments of the present disclosure. Some variations of these arrangements according to other embodiments of the present disclosure have been described above. Other variations/embodiments are also possible and within the scope of the present disclosure, i.e., various other programmable clamps (high-side or low-side and voltage-controlled or current-controlled clamps) as long as the clamp is dependent on the output offset current I0 as described herein. Some of these further variations/embodiments are described below.

In some embodiments, a multi-stage TIA having clamping that is programmable using an output offset current as described herein may have additional passive and/or active components to set or adjust a desired common-mode output voltage, e.g., to match an input common-mode of an ADC or any other electronic component configured to receive a differential input from the multi-stage TIA.

Furthermore, although the illustrations of fig. 6-11 are provided for circuits employing bipolar transistors, the illustrations may be readily applied to circuits employing FETs or a combination of bipolar transistors and FETs. For example, in further embodiments of the multi-stage TIA504 with adjustable input range as described herein, any NPN transistor shown in fig. 6-11 may be replaced with an NMOS transistor and/or any PNP transistor shown in fig. 6-11 may be replaced with a PMOS transistor. In such embodiments, for a transistor implemented as a FET, reference to the base terminal of the aforementioned bipolar transistor may be replaced by a "gate terminal", for a transistor implemented as a FET, reference to the emitter terminal of the aforementioned bipolar transistor may be replaced by a "source terminal", and for a transistor implemented as a FET, reference to the collector terminal of the aforementioned bipolar transistor may be replaced by a "drain terminal". Also, as is known in the art, the positive power supply Vcc of the bipolar transistor will be the positive power supply VDD for the FET, and the negative power supply Vee of the bipolar transistor will be the negative power supply VSS for the FET.

Exemplary System

The multi-level TIA with adjustable input range as described herein may be used in any type of system. One example of such a system is shown in fig. 12, providing a block diagram of an exemplary laser ranging (e.g., LIDAR) system 1200 in accordance with some embodiments of the present disclosure. As shown in fig. 12, system 1200 may include a transmitter signal chain 1210, a receiver signal chain 1230, a processor 1250, and a controller 1260. In some cases, receiver signal chain 1230 may be implemented separately from transmitter signal chain 1210. As shown in fig. 12, the transmitter signal chain 1210 may include a digital-to-analog converter (DAC)1212, a Low Pass Filter (LPF)1214, a Programmable Gain Amplifier (PGA)1216, a laser driver 1218, and a laser 1220. The receiver chain 1230 may include an optical sensor (e.g., a Photodiode (PD)1232), a transimpedance amplifier (TIA)1234, an LPF 1236, an analog-to-digital converter (ADC) driver 1238, and an ADC 1240. In some cases, the receiver chain may include a PGA coupled between TIA1234 and LPF 1236. Such a PGA may be implemented in place of or in addition to the ADC driver 1238.

Processor 1250 may be configured to generate a digital signal indicating that a laser pulse is to be emitted by laser 1220. The digital signal from the processor 1250 may then be converted to an analog signal by the DAC 1212, further processed by the optional LPF1214, amplified by the PGA 1216, and provided to the laser driver 1218. In some embodiments, laser 1220 may be a laser diode, such as an inductively resonant laser diode.

Light emitted by the laser 1220 may reach an object or target, and the reflected light may be received by the optical sensor 1232 of the receiver signal chain 1230. Thus, the reflected light may be detected at the optical sensor 1232. For example, the optical sensor 1232 may be an Avalanche Photodiode (APD). The optical sensor 1232 may generate a current pulse indicative of the received reflected light, and the current pulse may be converted to a voltage pulse by TIA1234 and, optionally, further processed by LPF 1236. In some embodiments, the LPF 1236 may be a tunable filter. As shown, LPF 1236 may be coupled in the signal path between TIA1234 and ADC driver 1238. In some other implementations, the LPF 1236 may be coupled in the signal path between the ADC driver 1238 and the ADC 1240. The ADC driver 1238 may generate a driving signal based on the output of the TIA1234 to drive the ADC 1240. ADC1240 may convert the received drive signals to digital signals for further processing by processor 1250. TIA1234 and/or ADC1238 may include any embodiment of a multi-stage TIA with programmable clamping as described herein, such as any of the embodiments of the multi-stage TIA with programmable clamping described with reference to fig. 5-11.

In some embodiments, processor 1250 may be a hardware processor. In some embodiments, processor 1250 may be a baseband digital signal processor. In some embodiments, processor 1250 may determine the distance between the object and laser ranging system 1200. In some embodiments, processor 1250 may output a signal indicative of the determined distance. In some embodiments, the processor 1250 may identify an object from which the pulse of light reflected from the object is based at least in part on the width of the pulse generated by the TIA 1234. In some embodiments, processor 1250 may output data identifying the object. In some embodiments, one instance of processor 1250 may be associated with receiver signal chain 1230 and another instance of processor 1250 may be associated with transmitter signal chain 1210.

The controller 1260 may be used to control aspects of the system 1200, and in particular aspects of the disclosure relate to a multi-level TIA with programmable clamping as described herein. For example, the controller 1260 may generate control signals that control the operation of various elements of a multi-level TIA with programmable clamping as described herein. In some embodiments, the controller 1260 may be implemented as the data processing system shown in FIG. 13.

Figure 13 provides a block diagram illustrating an example data processing system 1300 that may be configured to implement or control at least part of implementing a multi-level TIA with adjustable input range implemented using programmable clamping, in accordance with some embodiments of the present disclosure. For example, in some embodiments, the data processing system 1300 may be configured to control the functionality of the control voltage VCLHI, as described herein. In some embodiments, the controller 1260 may be implemented as a data processing system 1300.

As shown in FIG. 13, the data processing system 1300 may include at least one processor 1302 (e.g., a hardware processor 1302) coupled to memory elements 1304 through a system bus 1306. In this manner, the data processing system may store program code within the memory elements 1304. Further, the processor 1302 may execute program code accessed from the memory elements 1304 via the system bus 1306. In one aspect, a data processing system may be implemented as a computer adapted to store and/or execute program code. It should be understood, however, that the data processing system 1300 may be implemented in the form of any system including a processor and memory capable of performing the functions described within this disclosure.

In some embodiments, the processor 1302 may execute software or algorithms to perform the activities discussed in this specification, particularly the activities associated with a multi-level TIA with programmable clamping as described herein. Processor 1302 may include any combination of hardware, software, or firmware that provides programmable logic, including a microprocessor, Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), application specific Integrated Circuit (IC) (ASIC), or virtual machine processor, as non-limiting examples. The processor 1302 may be communicatively coupled to the memory element 1304 (e.g., in a Direct Memory Access (DMA) configuration) such that the processor 1302 may read from or write to the memory element 1304.

In general, memory elements 1304 may include any suitable volatile or non-volatile memory technology, including Double Data Rate (DDR) Random Access Memory (RAM), Synchronous RAM (SRAM), Dynamic RAM (DRAM), flash memory, Read Only Memory (ROM), optical media, virtual memory, magnetic or tape memory, or any other suitable technology. Unless otherwise specified, any memory element discussed herein should be construed as being encompassed within the broad term "memory. The information measured, processed, tracked, or sent to or from any component of the data processing system 1300 can be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable time frame. Any such storage options may be included in the broad term "memory" as used herein. Similarly, any potential processing elements, modules, and machines described herein should be construed as being encompassed within the broad term "processor. Each of the elements shown in this figure (e.g., any of the circuits/components shown in fig. 5-12) may also include suitable interfaces for receiving, sending, and/or otherwise communicating data or information in a network environment, such that they may communicate with, for example, a data processing system 1300 of another of these elements.

In certain example embodiments, the mechanisms associated with a multi-level TIA with programmable clamping as outlined herein may be implemented by logic (e.g., embedded logic provided in an ASIC) encoded in one or more tangible media (which may include non-transitory media), logic in DSP instructions, software (possibly including object code and source code) to be executed by a processor, or other similar machine, etc. In some of these examples, a memory element (such as, for example, memory element 1304 shown in fig. 13) may store data or information for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor may execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, a processor (such as, for example, processor 1302 shown in fig. 13) may transform an element or an article (e.g., data) from one state or thing to another state or thing. In another example, the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software/computer instructions executed by a processor), and the elements identified herein could be some type of a programmable processor, programmable digital logic (e.g., an FPGA, a DSP, an erasable programmable read-only memory (EPRPM), an electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

Memory elements 1304 may include one or more physical memory devices such as, for example, local memory 1308 and one or more mass storage devices 1310. Local memory may refer to RAM or other volatile memory devices that are typically used during actual execution of the program code. The mass storage device may be implemented as a hard disk drive or other persistent data storage device. Processing system 1300 may also include one or more cache memories (not shown) that provide temporary storage of at least some program code in order to reduce the number of times program code must be retrieved from mass storage device 1310 during execution.

As shown in fig. 13, the memory element 1304 may store an application 1318. In various embodiments, the applications 1318 may be stored in local memory 1308, one or more mass storage devices 1310, or separate from local memory and mass storage devices. It is to be appreciated that the data processing system 1300 may further execute an operating system (not shown in FIG. 13) that may facilitate execution of the application 1318. The application 1318, embodied in executable program code, may be executed by the data processing system 1300, for example by the processor 1302. In response to executing the application, data processing system 1300 may be configured to perform one or more operations or method steps described herein.

Input/output (I/O) devices, depicted as input device 1312 and output device 1314, may optionally be coupled to the data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, and the like. Examples of output devices may include, but are not limited to, a monitor or display, speakers, and the like. In some embodiments, output device 1314 may be any type of screen display, such as a plasma display, a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an Electroluminescent (EL) display, or any other indicator, such as a dial, barometer, or LED. In some implementations, the system can include a driver (not shown) for the output device 1314. The input and/or output devices 1312, 1314 may be coupled to the data processing system either directly or through intervening I/O controllers.

In an embodiment, the input and output devices may be implemented as a combined input/output device (shown in fig. 13 with dashed lines around input device 1312 and output device 1314). An example of such a combined device is a touch sensitive display, sometimes also referred to as a "touch screen display" or simply a "touch screen". In such embodiments, input to the device may be provided by movement of a physical object (such as, for example, a user's stylus or finger) on or near the touch screen display.

Optionally, a network adapter 1316 may also be coupled to the data processing system to enable it to be coupled to other systems, computer systems, remote network devices, and/or remote storage devices through intervening private or public networks. A network adapter may include a data receiver for receiving data transmitted by the system, device, and/or network to the data processing system 1300, and a data transmitter for transmitting data from the data processing system 1300 to the system, device, and/or network. Modems, cable modem and Ethernet cards are examples of different types of network adapters that may be used with data processing system 1300.

Fig. 14 provides an illustration 1400 of a LIDAR system integrated with an automobile, in accordance with some embodiments of the present disclosure. This is an exemplary application in which any of the multi-level TIAs with adjustable input ranges implemented using programmable clamping as described herein may be implemented. Fig. 14 shows two LIDAR systems 1402 and 1404 integrated with an automobile 1406. The first LIDAR system 1402 may be positioned near a right front light of the automobile 1406, while the second LIDAR system 1404 may be positioned near a left front light of the automobile 1406. As described herein, the LIDAR systems 1402 and/or 1404 may implement any suitable principles of a multi-stage TIA with programmable clamping. The LIDAR systems 1402 and/or 1404 may detect a distance between the automobile 1406 and the object 1408.

As shown, the emitter of the LIDAR system 1402 may emit a pulse of light 1410 at an angle 1412. At least some of the pulses of light 1410 may be generated by a laser diode (e.g., laser diode 1220 shown in fig. 12). The penetrating light 1410 may travel through air and reach the object 1408. The object 1408 may reflect the pulses of light 1414 back to a receiver of the LIDAR system 1402. Embodiments discussed herein may generate information for identifying the object 1408. The pulses of light 1410 may be emitted in three dimensions to obtain three dimensional information of the surrounding environment.

One or more additional LIDAR systems may be integrated with the automobile 1406 to cover a greater range of detection areas and/or to obtain additional information about selected areas. In some embodiments, the data collected by each LIDAR system may be combined to analyze information from a wider area and/or to provide additional information about the selected area. In some embodiments, angle 1412 may be adjusted and angle 1412 may be within any suitable range.

The illustrations of fig. 5-11 provide only a few non-limiting examples in which various embodiments of a multi-level TIA, such as TIA504, with adjustable input ranges as described herein may be used. In other embodiments, the TIA504 may be implemented in systems other than the LIDAR system shown in fig. 5 (i.e., the input current IIN provided to the TIA504 may be provided from any other source and not necessarily any input current provided from the optical sensor 102). The various teachings related to a multi-level TIA with adjustable input range as described herein are applicable to a wide variety of other systems. In some cases, various embodiments of the multi-level TIA with adjustable input range as described herein may be used in automotive systems, safety critical industrial applications, medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be highly accurate), and various digital processing-based systems. In other cases, various embodiments of a multi-stage TIA with adjustable input ranges as described herein may be used in an industrial market that includes process control systems that help to improve productivity, energy efficiency, and reliability. In further cases, various embodiments of a multi-level TIA with adjustable input ranges may be used for consumer applications.

Selection example

The following paragraphs provide examples of various ones of the embodiments disclosed herein.

Example a1 provides a multi-stage TIA including a high-side clamp associated with a first stage.

Example a2 provides a multi-level TIA according to example a1, wherein the TIA includes coupling between components as shown in fig. 5.

Example A3 provides a multi-level TIA according to example a1, wherein the TIA includes coupling between components as shown in fig. 8.

Example a4 provides an electronic assembly including a multi-level TIA according to any of the preceding examples a.

Example a5 provides the electronic component according to example a4, wherein the electronic component is a TIA or an ADC driver.

Example a6 provides the electronic component according to example a4, wherein the electronic component is a LIDAR receiver.

Example B1 provides a system (such as a TIA) configured to convert a single-ended current input to a differential voltage output. The system comprises: a first amplifier circuit (e.g., amplifier a0 described herein) having an output for providing a first amplifier output generated by the first amplifier circuit based on a single-ended current input; an output offset current generating circuit (e.g., amplifier a1 described herein) configured to generate an output offset current; a second amplifier circuit (e.g., amplifier a2 described herein) having a differential input comprising a first input and a second input and configured to generate a differential voltage output based on: a signal based on the first amplifier output is received at a first input of a differential input of the second amplifier circuit (e.g., at a negative input IN-), and a signal based on the output offset current is received at a second input of the differential input of the second amplifier circuit (e.g., at a positive input IN +. The system further comprises: a clamp circuit coupled to an output of the first amplifier circuit and further coupled to a control signal configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on the output offset current generated by the output offset current generation circuit.

In such a system, the clamp circuit is configured to clamp the first amplifier output based on a control signal provided to the clamp circuit to ensure that the first amplifier output does not drop below a minimum voltage or exceed a maximum voltage set by the control signal. The clamped version of the first amplifier output is then provided to a first input of the differential inputs of the second amplifier circuit. Since the second input of the differential input of the second amplifier circuit receives a signal based on the output offset current and since the first input of the differential input of the second amplifier circuit receives a clamped version of the first amplifier output in which the clamping depends on a control signal also based on the output offset current, the system may advantageously ensure that the differential input of the second amplifier circuit is not overloaded.

Example B2 provides the system of example B1, wherein the first amplifier circuit includes a first transistor (e.g., transistor Q1 shown in fig. 8 or 9) and a second transistor (e.g., transistor Q2 shown in fig. 8 or 9), and the clamp circuit includes a third transistor (e.g., transistor Q3 shown in fig. 8 or 9). In a further example of the system according to example B2, each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal, wherein the first terminal of the third transistor is coupled to the third terminal of the second transistor, the first terminal of the second transistor is coupled to the output of the first amplifier circuit, the first amplifier circuit is configured to receive the single-ended current input at the third terminal of the first transistor, and the second terminal of the first transistor is coupled to the third terminal of the second transistor.

Example B3 provides the system of example B2, wherein the control voltage signal sets a maximum voltage value, each of the first transistor and the second transistor is an N-type transistor, and the third transistor is a P-type transistor. In a further example of the system according to example B3, the second terminal of the third transistor and the first terminal of the first transistor may be coupled to a negative power supply (e.g., Vee for bipolar transistor implementations, or VSS for FET implementations), and the second terminal of the second transistor may be coupled to a positive power supply (e.g., Vcc for bipolar transistor implementations, or VDD for FET implementations).

Example B4 provides the system of example B3, wherein the control signal is based on a positive supply voltage of the first amplifier circuit and the clamp circuit (e.g., voltage Vcc for bipolar transistor implementations, or voltage VDD for FET implementations).

Example B5 provides the system of example B2, wherein the control voltage signal sets a minimum voltage value, each of the first transistor and the second transistor is a P-type transistor, and the third transistor is an N-type transistor. In a further example of the system according to example B5, the second terminal of the third transistor and the first terminal of the first transistor may be coupled to a positive power supply (e.g., Vcc for bipolar transistor implementation or VDD for FET implementation) and the second terminal of the second transistor may be coupled to a negative power supply (e.g., Vee for bipolar transistor implementation or VSS for FET implementation).

Example B6 provides the system of example B5, wherein the control signal is based on a negative supply voltage of the first amplifier circuit and the clamp circuit (e.g., voltage Vee for bipolar transistor implementations, or voltage VSS for FET implementations).

Example B7 provides the system according to any one of examples B2-B6, wherein the control signal is configured to be further based on a voltage difference between the first terminal and the third terminal of the first transistor (e.g., based on the voltage V, in the case where Q1 is a bipolar transistor, for example)_BE,Q1) To set one of a minimum voltage value or a maximum voltage value of the first amplifier output. In other example B, the control signal is configured to be further based on Vee-dependent V_min,A0To set the maximum of the first amplifier outputOne of a small voltage value or a maximum voltage value.

Example B8 provides the system according to any one of examples B2-B7, wherein the control signal is configured to be further based on a voltage difference between the first terminal and the third terminal of the second transistor (e.g., based on the voltage V, in the case where Q2 is a bipolar transistor, for example)_BE,Q2) To set one of a minimum voltage value or a maximum voltage value of the first amplifier output. In other example B, the control signal is configured to be further based on V depending on Vcc_max,A0To set one of a minimum voltage value or a maximum voltage value of the first amplifier output.

Example B9 provides the system according to any one of examples B2-B8, wherein the control signal is configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output further based on a resistance of a feedback component (e.g., a resistance RT across the amplifier a0) having a first terminal coupled to a third terminal of the first transistor (i.e., coupled to an input of the first amplifier circuit) and having a second terminal coupled to a third terminal of the second transistor (i.e., coupled to an output of the first amplifier circuit).

Example B10 provides the system of any of examples B2-B9, wherein for any of the first transistor, the second transistor, and the third transistor that are bipolar transistors, the first terminal is an emitter terminal, the second terminal is a collector terminal, and the third terminal is a base terminal.

Example B11 provides the system of any of examples B2 to B10, wherein for any of the first transistor, the second transistor, and the third transistor that are Field Effect Transistors (FETs), the first terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal.

Example B12 provides the system according to any one of examples B1-B11, wherein the control signal is a control voltage signal.

Example B13 provides the system according to any one of examples B1-B11, wherein the control signal is a control current signal.

Example B14 provides the system according to any of the preceding examples B, wherein the system is a driver for an analog-to-digital converter.

In a further example B, the system according to any of the preceding examples B may be a LIDAR system.

Example B15 provides a system (such as a TIA) configured to convert a single-ended current input to a differential voltage output, the system comprising: a first stage configured to receive a single-ended current input and to generate a single-ended output based on the single-ended current input; a clamping circuit configured to generate a clamped single-ended output by clamping the single-ended output when one of the following is true: 1) the clamped single-ended output is the same as the single-ended output generated by the first stage if/when the single-ended output exceeds a maximum voltage value (if the single-ended output does not exceed the maximum voltage value, the clamped single-ended output is the same as the single-ended output generated by the first stage), wherein the maximum voltage value is based on the output offset current, or 2) if/when the single-ended output falls below a minimum voltage value (if the single-ended output does not fall below the minimum voltage value, the clamped single-ended output is the same as the single-ended output generated by the first stage), the minimum voltage value is based on. The system further comprises: a second stage configured to receive a signal based on the clamped single-ended output as a first input of a differential input of the second stage, receive a signal based on the output offset current as a second input of the differential input of the second stage, and generate a differential voltage output based on the differential input.

Example B16 provides the system of example B15, wherein each of the single-ended output, the clamped single-ended output, and the signal based on the output offset current is a voltage signal.

Example B17 provides the system of example B15 or B16, wherein the first stage comprises: an amplifier having an input for receiving a single-ended current input and having an output for providing a single-ended output; and a feedback resistor having a first terminal coupled to the input of the amplifier and having a second terminal coupled to the output of the amplifier.

Example B18 provides the system according to any one of examples B15-B17, further comprising a circuit configured to generate the output offset current.

Example B19 provides the system according to example B18, wherein the circuit is coupled to a control voltage and the circuit is a voltage-to-current converter configured to generate the output offset current based on the control voltage.

Example B20 provides a system configured to convert a single-ended signal to a differential signal, the system comprising an amplifier and a clamp circuit, wherein the amplifier has a differential input and a differential output, a first input of the differential input of the amplifier is configured to receive a signal based on the single-ended signal that has been clamped by the clamp circuit based on a clamp control signal, wherein the clamp control signal is based on an output offset current, a second input of the differential input of the amplifier is configured to receive a signal based on the output offset current, and the amplifier is configured to generate the differential signal based on the signal received at the differential input of the amplifier.

Example B21 provides a system according to example B20, wherein the system further includes features according to one or more of examples B1 to B19.

Example B22 provides a system according to example B20 or B21, wherein the system is a driver for an ADC or LIDAR system.

Example B23 provides a method comprising steps performed by a system or apparatus according to any one of the preceding examples.

Example B24 provides a method comprising the step of causing the system to operate in accordance with any of the preceding examples.

Example B25 provides a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform at least part of a method according to any one of examples B23 and B24.

Example B26 provides a computer program product comprising instructions that, when executed by a processor, cause the processor to perform at least part of a method according to any one of examples B23 and B24.

Description of other embodiments, modifications and applications

The principles and advantages discussed herein may be used in any device in which a restriction on the TIA output needs to be made. For example, aspects of the present disclosure may be implemented in various ranging systems. For example, aspects of the present disclosure may be implemented in any suitable LIDAR system (such as, for example, automotive LIDAR, industrial LIDAR, spatial LIDAR, military LIDAR, etc.). LIDAR systems may include a receiver or a transmitter and a receiver. The LIDAR system may be integrated with a vehicle such as an automobile, an unmanned aircraft such as an unmanned aerial vehicle, an autonomous robot, or a spacecraft. The LIDAR system may emit and/or receive laser light. LIDAR systems may be used for three-dimensional sensing applications. LIDAR systems may be used with augmented reality technologies. Further, aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, electronic products, components of electronic products (such as integrated circuits), vehicle electronics (such as automotive electronics), and the like. Further, the electronic device may include unfinished products.

While certain embodiments have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the disclosure. For example, although some embodiments relate to an APD coupled to an input port of a TIA, the embodiments are equally applicable to any other device that can generate a current pulse to provide an input to a TIA (e.g., to any other type of PD). In another example, while some embodiments may relate to a PD that sinks current from a TIA, these embodiments may be modified to a PD that provides current to a TIA in a manner apparent to one of ordinary skill in the art, and thus, all of these embodiments are within the scope of the present disclosure. Indeed, the novel methods, apparatus, and systems described herein relating to a multi-level TIA with programmable clamping may be implemented in various other forms. Furthermore, various omissions, substitutions and changes in the form of the methods, devices, and systems described herein may be made without departing from the spirit of the disclosure. For example, circuit blocks and/or circuit elements described herein may be deleted, moved, added, subdivided, combined, and/or modified. Each of these circuit blocks and/or circuit elements may be implemented in a variety of different ways. The accompanying claims and their equivalents are intended to cover any such forms or modifications as would fall within the scope and spirit of the disclosure.

Any of the principles and advantages discussed herein may be applied to other systems, apparatuses, integrated circuits, electronic devices, methods, and not just to the above-described embodiments. The elements and operations of the various embodiments described above can be combined to provide further embodiments. The principles and advantages of embodiments may be employed in conjunction with any other system, apparatus, integrated circuit, device, or method that may benefit from any of the teachings herein.

It is to be understood that not necessarily all objectives or advantages may be achieved in accordance with any particular embodiment described herein. Thus, for example, those skilled in the art will recognize that certain embodiments may be configured to operate in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

In an exemplary embodiment, any number of the circuits in the figures may be implemented on a board of an associated electronic device. The board may be a universal circuit board that may house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board may provide electrical connections through which other components of the system may be in electrical communication. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc., may be suitably coupled to the board based on particular configuration needs, processing requirements, computer design, etc. Other components, such as external memory banks, controllers for configuring any of the components, and peripherals, may be attached to the board as a plug-in card via a cable, or integrated into the board itself. In various embodiments, the functions described herein may be implemented in emulated form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure that supports those functions. The software or firmware providing the emulation may be provided on a non-transitory computer readable storage medium containing instructions that allow the processor to perform those functions.

In another exemplary embodiment, the circuits described herein may be implemented as stand-alone modules (e.g., devices with associated components and circuitry configured to perform a particular application or function), or as plug-in modules into dedicated hardware of an electronic device. Note that certain embodiments of the present disclosure may be readily incorporated, partially or wholly, in a system-on-a-chip (SOC) package. An SOC represents an IC that integrates components of a computer or other electronic system into a single chip. It may contain digital functions, analog functions, mixed signal functions, and general radio frequency functions: all of these functions may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple individual ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package. In various other embodiments, the circuits described herein may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

It must also be noted that all specifications, dimensions, and relationships outlined herein (e.g., number of processors, logical operations, etc.) are provided for purposes of example and teaching only. Such information may vary considerably without departing from the spirit of the disclosure or the scope of the appended claims. The description applies to only one non-limiting example and, therefore, they should be so interpreted. In the foregoing specification, exemplary embodiments have been described with reference to specific arrangements of components. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Note that in many of the examples provided herein, interaction may be described in terms of two, three, four, or more electronic components. However, this is done for purposes of clarity and example only. It should be appreciated that the system may be integrated in any suitable manner. Along similar design alternatives, any of the components, modules, and elements shown in the figures may be combined in various possible configurations, all of which are clearly within the broad scope of the present disclosure. In some cases, it may be easier to describe one or more functions of a given flow set by only referencing a limited number of electrical elements. It will be appreciated that the circuits of the figures and their teachings are readily scalable and can accommodate a large number of components, as well as more complex/cumbersome arrangements and configurations. Thus, the examples provided should not limit the broad teachings of the range or suppression circuitry, as it may be applied to myriad other architectures.

Note that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment", "an exemplary embodiment", "an embodiment", "another embodiment", "some embodiments", "various embodiments", "other embodiments", "alternative embodiments", etc., are intended to mean that any such feature is included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained to one skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the appended selected examples. Note that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and the details of the examples may be used anywhere in one or more embodiments.

Claims (20)

1. A system configured to convert a single-ended current input to a differential voltage output, the system comprising:

a first amplifier circuit having an output for providing a first amplifier output generated by the first amplifier circuit based on the single-ended current input;

an output offset current generation circuit configured to generate an output offset current;

a second amplifier circuit having a differential input comprising a first input and a second input and configured to generate the differential voltage output based on:

receiving at the first input a signal based on the first amplifier output, an

Receiving a signal based on the output offset current at the second input; and

a clamp circuit coupled to the output of the first amplifier circuit and further coupled to a control signal configured to set one of a minimum voltage value or a maximum voltage value of the first amplifier output based on the output offset current.

2. The system of claim 1, wherein:

the first amplifier circuit includes a first transistor and a second transistor,

the clamping circuit comprises a third transistor which is connected to a second transistor,

each of the first transistor, the second transistor, and the third transistor includes a first terminal, a second terminal, and a third terminal,

the first terminal of the third transistor is coupled to the third terminal of the second transistor,

the first terminal of the second transistor is coupled to the output of the first amplifier circuit,

the first amplifier circuit is configured to receive the single-ended current input at the third terminal of the first transistor, and

the second terminal of the first transistor is coupled to the third terminal of the second transistor.

3. The system of claim 2, wherein:

the control voltage signal sets the maximum voltage value,

each of the first transistor and the second transistor is an N-type transistor, and

the third transistor is a P-type transistor.

4. The system of claim 3, wherein the control signal is based on a positive supply voltage of the first amplifier circuit and the clamp circuit.

5. The system of claim 2, wherein:

the control voltage signal sets the minimum voltage value,

each of the first transistor and the second transistor is a P-type transistor, and

the third transistor is an N-type transistor.

6. The system of claim 5, wherein the control signal is based on a negative supply voltage of the first amplifier circuit and the clamp circuit.

7. The system of claim 2, wherein the control signal is configured to set one of the minimum voltage value or the maximum voltage value of the first amplifier output further based on a voltage difference between the first terminal and the third terminal of the first.

8. The system of claim 2, wherein the control signal is configured to set one of the minimum voltage value or the maximum voltage value of the first amplifier output further based on a voltage difference between the first terminal and the third terminal of the second transistor.

9. The system of claim 2, wherein the control signal is configured to set one of the minimum voltage value or the maximum voltage value of the first amplifier output further based on a resistance of a feedback component having a first terminal coupled to the third terminal of the first transistor and having a second terminal coupled to the third terminal of the second transistor.

10. The system of claim 2, wherein for any of the first, second, and third transistors that are bipolar transistors, the first terminal is an emitter terminal, the second terminal is a collector terminal, and the third terminal is a base terminal.

11. The system of claim 2, wherein for any of the first, second, and third transistors that are Field Effect Transistors (FETs), the first terminal is a source terminal, the second terminal is a drain terminal, and the third terminal is a gate terminal.

12. The system of claim 1, wherein the control signal is a control voltage signal.

13. The system of claim 1, wherein the control signal is a control current signal.

14. The system of claim 1, wherein the system is a driver for an analog-to-digital converter.

15. A system configured to convert a single-ended current input to a differential voltage output, the system comprising:

a first stage configured to receive the single-ended current input and to generate a single-ended output based on the single-ended current input;

a clamping circuit configured to generate a clamped single-ended output by clamping the single-ended output when one of the following is true:

when the single-ended output exceeds a maximum voltage value, wherein the maximum voltage value is based on an output offset current,

or when the single-ended output falls below a minimum voltage value, wherein the minimum voltage value is based on the output offset current; and

a second stage configured to:

receiving a signal based on the clamped single-ended output as a first input of a differential input of the second stage,

receiving a signal based on the output offset current as a second input of the differential input of the second stage, and

generating the differential voltage output based on the differential input.

16. The system of claim 15, wherein each of the single-ended output, the clamped single-ended output, and the signal based on the output offset current is a voltage signal.

17. The system of claim 15, wherein the first stage comprises:

an amplifier having an input for receiving the single-ended current input and having an output for providing the single-ended output, an

A feedback resistor having a first terminal coupled to the input of the amplifier and having a second terminal coupled to the output of the amplifier.

18. The system of claim 15, further comprising a circuit configured to generate the output offset current.

19. The system of claim 18, wherein the circuit is coupled to a control voltage and the circuit is a voltage-to-current converter configured to generate the output offset current based on the control voltage.

20. A system configured to convert a single-ended signal to a differential signal, the system comprising:

an amplifier; and

a clamp circuit, wherein:

the amplifier has a differential input and a differential output,

a first input of the differential input of the amplifier is configured to receive a signal based on the single-ended signal having been clamped by the clamping circuit based on a clamping control signal, wherein the clamping control signal is based on an output offset current,

a second input of the differential input of the amplifier is configured to receive a signal based on the output offset current, and

the amplifier is configured to generate the differential signal based on the signal received at the differential input of the amplifier.

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